`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`No. 1:18-cv-00554-LY
`
`§§§§§§§§§§§
`
`AQUILA INNOVATIONS INC., a
`Delaware corporation,
`
`Plaintiff,
`
`v.
`
`ADVANCED MICRO DEVICES, INC., a
`Delaware corporation
`
`Defendant.
`
`REVISED JOINT CLAIM CONSTRUCTION STATEMENT
`
`Pursuant to the Court’s request during the August 23, 2019 Claims Construction Hearing,
`
`Plaintiff Aquila Innovations Inc. (“Aquila”) and Defendant Advanced Micro Devices, Inc.
`
`(“AMD”) submit this Revised Joint Claim Construction Statement for U.S. Patent Nos.
`
`6,895,519 (“the ’519 Patent) and 6,239,614 (“the ’614 Patent”). Alternative proposed
`
`constructions based on the Claims Construction Hearing are designated as “(Alternative based on
`
`CC hearing).”
`
`AQUILA - Ex. 2002
`
`
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 2 of 18
`
`I.
`
`’519 PATENT AGREED CONSTRUCTIONS
`
`Term
`Whether the preamble of claim 1 is limiting.
`
`“A system LSI having a plurality of ordinary
`operation modes and a plurality of special
`modes
`in response
`to clock frequencies
`supplied to a central processing unit”
`
`Agreed Construction
`The preamble of claim 1 is limiting. The
`disputed constructions for the term “system
`LSI” are below. No other terms within the
`preamble require construction.
`
`II.
`
`’519 PATENT DISPUTED CONSTRUCTIONS
`
`Exhibit A contains the parties’ respective proposed constructions of disputed claim terms
`
`in the ’519 Patent, together with an identification of supporting intrinsic and extrinsic evidence
`
`upon which they intend to rely. The proposed terms for construction are:
`
`(cid:120)
`(cid:120)
`(cid:120)
`(cid:120)
`
`(cid:120)
`(cid:120)
`
`(cid:120)
`(cid:120)
`(cid:120)
`
`(cid:120)
`
`“system LSI” (claim 1)
`“plurality of standard clocks” (claim 1)
`“generates a clock” (claim 1)
`“a clock control library for controlling a clock frequency transition between said ordinary
`operation modes” (claim 1)
`“user selectable” (claim 1)
`“an application program wherein calling of said clock control library and changing of said
`register value are programmably controlled by said application program to enable user
`selectable clock frequency transitions”1 (claim 1)
`“halted” (claim 1, 7)
`“principal constituents of said central processing unit” (claim 1)
`“a main library which is called by said application program and selects any one of said
`libraries” (claim 2)
`“a status register that judges a state of said central processing unit immediately after being
`released from said third special mode” (claim 7)
`
`
`1 The parties agree that this term is not subject to § 112, para. 6.
`
`-2-
`
`
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 3 of 18
`
`III.
`
`’614 PATENT DISPUTED CONSTRUCTIONS
`
`Exhibit B contains the parties’ respective proposed constructions of disputed claim terms
`
`in the ’614 Patent, together with an identification of supporting intrinsic and extrinsic evidence
`
`upon which they intend to rely. The proposed terms for construction are:
`
`(cid:120)
`(cid:120)
`(cid:120)
`(cid:120)
`(cid:120)
`(cid:120)
`
`“unit cells” (claim 1)
`“unit cell array” (claims 1, 3)
`“a unit cell array comprised of first and second unit cells laid in array form” (claim 1)
`“a power switch” (claims 1, 2, 3)
`“disposed around” (claim 1)2
`“parts of said power switch disposed within said unit cell array” (claim 3)
`
`IV.
`
`EXPERT IDENTIFICATION
`
`Patent
`
`Plaintiff’s Expert
`
`Defendant’s Expert
`
`’519 Patent
`
`’614 Patent
`
`Dr. Vojin Oklobdzija
`
`Dr. David Albonesi
`
`Dr. Vojin Oklobdzija
`
`Dr. Douglas Holberg
`
`The parties rely upon the opinions of their respective experts (identified above) regarding
`
`how a person of ordinary skill in the art (“POSITA”) would understand the meaning of each
`
`disputed term.
`
`
`2 The parties have agreed that “disposed around” is the disputed term for both previously
`proposed terms: “a power switch disposed around said unit cell array and comprised of a
`plurality of third MOS transistors” and “a plurality of input / output circuits disposed around
`said unit cell array.”
`
`-3-
`
`
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 4 of 18
`
`Dated: November 1, 2019
`
`Respectfully Submitted:
`
`/s/Jennifer Librach Nall
`Kevin J. Meek (SBN 13899600)
`Jennifer Librach Nall (SBN 24061613)
`Puneet Kohli (SBN 24090523)
`Aashish G. Kapadia (SBN 24097917)
`Clark Oberembt (SBN 24105897)
`BAKER BOTTS L.L.P.
`98 San Jacinto Blvd., Suite 1500
`Austin, TX 78701
`(512) 322-2500
`kevin.meek@bakerbotts.com
`jennifer.nall@bakerbotts.com
`puneet.kohli@bakerbotts.com
`aashish.kapadia@bakerbotts.com
`clark.oberembt@bakerbotts.com
`
`Attorneys for Defendant
`Advanced Micro Devices, Inc.
`
`/s/Jing H. Cherng
`Robert E. Freitas (admitted pro hac vice)
`Jing H. Cherng (admitted pro hac vice)
`FREITAS & WEINBERG LLP
`350 Marine Parkway, Suite 200
`Redwood Shores, CA 94065
`Telephone: (650) 593-6300
`rfreitas@fawlaw.com
`gcherng@fawlaw.com
`
`Henry B. Gonzalez III (SBN 00794952)
`Jeffrie B. Lewis (SBN 24071785)
`GONZALEZ, CHISCANO, ANGULO, &
`KASSON, PC
`9601 McAllister Freeway, Suite 401
`San Antonio, Texas 78216
`Tel: (210) 569-8500
`hbg@gcaklaw.com
`jlewis@gcaklaw.com
`
`Attorneys for Plaintiff
`Aquila Innovations Inc.
`
`-4-
`
`
`
`Microsoft Computer Dictionary (5th ed. 2002) at
`11;
`Electrical Engineering(CRC Press 1999) at 410-
`Laplante, P.A., Comprehensive Dictionaryof
`Technical Terms (6th ed. 2003) at 1334;
`McGraw-Hill Dictionary of Scientific and
`of Electronics(7th ed. 1999) at 470;
`“microcontroller”:Graf, R.F., Modern Dictionary
`Electrical Engineering(CRC Press 1999) at 361.
`Laplante, P.A., Comprehensive Dictionary of
`Computing(McGraw-Hill 10th ed. 1993) at 375;
`“LSI”: McDaniel, G., IBM Dictionary of
`
`Reference Numerals, Figs. 1, 2, claims 1–8.
`047696, ¶¶ [0002], [0010], Explanation of
`Certified Translation of Japanese Patent 2002-
`
`2:43-55, 9:7–11:17, 12:33-37; claims 1-11.
`’519 Patent: Figs. 1, 2, 1:5–15, 1:26–30, 2:10–30,
`
`based on CC hearing)
`system on a single integrated chip(Alternative
`
`OR
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`andI/O capability
`processing unit,first memory,second memory,
`single integrated chip, which has a central
`
`-5-
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`Electrical Engineering(CRC Press 2005) at 361.
`Laplante, P.A., Comprehensive Dictionary of
`Computing(McGraw-Hill 10th ed. 1993) at 375;
`“LSI”: McDaniel, G., IBM Dictionary of
`
`Cl. 1
`
`Fig. 1, 2
`
`’519 Patent1:5-10, 26-30, 2:10-30, 2:43-55.
`
`system on a chip
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Exhibit A
`
`(claim 1)
`“system LSI”
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 5 of 18
`
`
`
`-6-
`
`Electrical Engineering(CRC Press 1999) at 109;
`Laplante, P.A., Comprehensive Dictionary of
`Electronics(7th ed. 1999) at 122-23;
`“clock”:Graf, R.F., Modern Dictionary of
`
`1, 7, 8.
`Explanation of Reference Numerals, Fig. 4, claims
`047696, ¶¶ [0016], [0018], [0031], [0043], [0097],
`Certified Translation of Japanese Patent 2002-
`
`Action, Sept. 22, 2003.
`’519 Patent,File History, Response to Office
`
`8:14–19, 9:22–25, 9:26–37, 11:23–30; claims 1, 7.
`’519 Patent: Figs. 4, 9; 3:62–4:7, 5:41–48, 7:62–67,
`
`frequency
`multiple clock signals, each at a unique reference
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`2005) at 116-117;
`Dictionary of Electrical Engineering(CRC Press
`“clock”: Laplante, P.A., Comprehensive
`
`8:14–19, 9:22–25, 9:26–37, 11:23–30; claims 1, 7.
`’519 Patent: Figs. 4, 9; 3:62–4:7, 5:41–48, 7:62–67,
`
`multipleclock signals
`
`(claim 1)
`clocks”
`“plurality of standard
`
`Dictionary(6th ed. 1997) at 23.
`Sclater, N. & Markus, J., McGraw Hill Electronics
`Engineering(CRC Press 1999) at 31;
`Comprehensive Dictionary of Electrical
`Electronics(7th ed. 1999) at 34, 38; Laplante, P.A.,
`“ASIC”:Graf, R.F., Modern Dictionary of
`Dictionary(6th ed. 1997) at 288;
`Sclater, N. & Markus, J., McGraw Hill Electronics
`190–91, 337;
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 6 of 18
`
`
`
`047696, ¶¶ [0016], [0018], [0031], [0043], [0097],
`Certified Translation of Japanese Patent 2002-
`
`claims 1, 8.
`3:67-4:4, 7:24-27, 8:14-19, 9:26-37,11:23-30;
`’519 Patent: Figs. 4, 9; 1:44-62, 3:47-50, 3:51-54,
`
`(Alternative based on CC hearing)
`based on at least one of the multiple clock signals
`generates a signal for periodic circuit operation
`
`OR
`
`selecting the same
`frequency of another periodic signal, orby
`operation, by multiplying or dividing the
`creates a signal for controlling periodic circuit
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`-7-
`
`Terms (7th ed. 2000) at 177;
`The Authoritative Dictionary of IEEE Standards
`2005) at 116-117;
`Dictionary of Electrical Engineering(CRC Press
`“clock”: Laplante, P.A., Comprehensive
`
`8:14-19, 9:26-37, 11:23-30; claims 1, 6,8.
`3:67-4:4, 5:14-20, 6:66-7:4, 7:24-27,7:60-67,
`’519 Patent: Figs. 4, 9, 1:44-62, 3:47-50, 3:51-54,
`
`on CC hearing)
`“generates a periodic signal”(Alternative based
`
`OR
`
`signal
`Plain and ordinary meaning: outputs a clock
`
`(claim 1)
`“generates a clock”
`
`2001) at 979.
`Merriam-Webster’s Collegiate Dictionary (10th ed.
`Dictionary of Electronics(7th ed. 1999) at 729;
`“standard” / “reference”:Graf, R.F., Modern
`Dictionary(6th ed. 1997) at 76.
`Sclater, N. & Markus, J., McGraw Hill Electronics
`103;
`Microsoft Computer Dictionary (5th ed. 2002) at
`(McGraw-Hill 10th ed. 1993) at 108;
`McDaniel, G., IBM Dictionary of Computing
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 7 of 18
`
`
`
`’519 Patent, File History, Response to Office
`Response to Office Action, Sept. 22, 2003;
`’519 Patent, File History, Amendment and
`
`23, 12:24-64, 12:65-13:4, 13:5-23, claims 1-11.
`6:54-58, 9:7–10:29, 11:23-30, 11:57–12:11, 12:12-
`4:12-18, 4:29-44, 4:61–5:3, 6:1-7,
`’519 Patent: Figs. 2, 6, 7, 8a, 9b; Abstract, 3:38-42,
`
`Structure: indefinite
`
`ordinary operation modes
`(that is not a state transition) between said
`Function: controlling a clock frequency transition
`
`para. 6.
`operation modes” is subject to 35 U.S.C. §112,
`frequency transition between said ordinary
`“aclock control library for controlling a clock
`citations.
`See supra, “plurality of standard clocks,” additional
`
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`Electronics Dictionary(6th ed. 1997) at 37.
`“base”:Sclater, N. & Markus, J., McGraw Hill
`
`1, 7, 8.
`Explanation of Reference Numerals, Fig. 4, claims
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`-8-
`
`422.
`Modern Dictionary of Electronics(7th ed. 1999) at
`“library”:
`
`1126;
`of IEEE Standards Terms (7th ed. 2000) at 235,
`“control program”:The Authoritative Dictionary
`
`12:10,Fig. 6, 7, 8,Cl. 1, 5
`’519 Patent:4:29-44, 4:61-5:3, 9:7-10:29, 11:57-
`
`operation modes.
`frequency of the clock signals in the ordinary
`stores] software that controls the change in the
`Plain and ordinary meaning: [a first memory that
`
`Not subject to 35 U.S.C. §112, para. 6.
`
`(claim 1)
`operation modes”
`said ordinary
`transition between
`a clock frequency
`library for controlling
`“a clock control
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 8 of 18
`
`
`
`-9-
`
`Declaration of Dr. Albonesi, Dkt. 40-1.
`Systems (McGraw-Hill 2001) at 311.
`Patt, Y. N. & Patel, S.J., Introduction to Computing
`Standards Terms (7th ed. 2000) at 468;
`“function”:The Authoritative Dictionary of IEEE
`Systems (McGraw-Hill 2001) at 187-88, 230.
`Patt, Y. N. & Patel, S.J., Introduction to Computing
`1200;
`Scientific and Technical Terms (6th Ed. 2003) at
`“library routine”:McGraw-Hill Dictionary of
`Systems (McGraw-Hill 2001) at 182, 311.
`Patt, Y. N. & Patel, S.J., Introduction to Computing
`309;
`Microsoft Computer Dictionary (5th ed. 2002) at
`Computing (McGraw-Hill 10th ed. 1993) at 380;
`“library”:McDaniel, G., IBM Dictionaryof
`(McGraw-Hill 10th ed. 1993) at 146.
`McDaniel, G., IBM Dictionary of Computing
`1126;
`of IEEE Standards Terms (7th ed. 2000) at 235,
`“control program”:The Authoritative Dictionary
`
`8b, 9, claims 1–8.
`Explanation of Reference Numerals,Figs. 5, 7, 8a,
`047696, ¶¶ [0005], [0078], [0086], [0091]–[0093],
`Certified Translation of Japanese Patent 2002-
`Action, Apr. 19, 2004.
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 9 of 18
`
`
`
`’519 patent: Figs. 2, 5, 6; 3:51–54,4:47–61, 11:18–
`
`transitions
`to enable user selectable clock frequency
`control library and changing of said register value
`software thatprogrammably controls the clock
`Declaration of Dr. Albonesi,Dkt. 40-1.
`
`047696, Abstract, ¶¶ [0015], [0024], [0100].
`Certified Translation of Japanese Patent 2002-
`
`Action, Apr. 19, 2004.
`’519 Patent, File History, Response to Office
`Response to Office Action, Sept. 22, 2003;
`’519 Patent, File History, Amendment and
`
`61, 13:33–36, 14:10–14.
`’519 Patent: Figs. 2, 5, 6; 1:12–20, 3:28–33, 4:47–
`
`based on CC hearing)
`capable of being selected by a human(Alternative
`
`OR
`
`hearing)
`human selectable(Alternative based on CC
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`OR
`
`chosen by a person
`
`-10-
`
`value, such as to enable user selectable clock
`control library and changing of said register
`program that programmably controls the clock
`[a second memory that stores] an application
`
`Not subject to 35 U.S.C. §112, para. 6.
`
`register value are
`changing of said
`control library and
`calling of said clock
`program wherein
`“an application
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`’519 Patent: 4:50, 9:36-39
`
`selected by a user
`Plain and ordinary meaning: capable of being
`
`(claim 1)
`“user selectable”
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 10 of 18
`
`
`
`-11-
`
`11:17, 11:40–43.
`51, 8:6–11, 9:18–22, 10:30–45; 10:46–59, 10:60–
`’519 Patent: Figs. 2, 3, 4, 5; 5:8–10, 6:63–65, 7:46–
`
`stopped(Alternative based on CC hearing)
`
`8:19-20, 9:18-22, 10:30-11:49, cl.1, 6
`’519 Patent: 5:17-21, 5:30-36, 7:28-42, 8:6-13,
`
`CC hearing)
`No construction necessary. (Alternative based on
`
`OR
`
`OR
`
`cut off completely
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`Plain and ordinary meaning,stopped or paused.
`
`“halted” (claim 1, 7)
`
`(McGraw-Hill 10th ed. 1993) at 28.
`McDaniel, G., IBM Dictionary of Computing
`Dictionary of Electronics (7th ed. 1999) at 34;
`“applicationprogram”:Graf, R.F., Modern
`
`6, claims 1–3.
`[0083], [0084], [0091], [0092], [0094], [0100], Fig.
`[0021], [0023], [0024], [0039], [0077], [0080],
`047696, ¶¶ [0009], [0013], [0015], [0016], [0017],
`Certified Translation of Japanese Patent 2002-
`
`Action, Apr. 19, 2004.
`’519 Patent, File History, Response to Office
`Response to Office Action, Sept. 22, 2003;
`’519 Patent, File History, Amendment and
`
`14:5–14.
`22, 11:66–12:5, 12:65–13:9, 13:10–24, 13:33–36,
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`12:10, 12:11 –13:35 Fig. 6, 7, 8, Cl. 1, 5
`’519 Patent: 4:29-44,4:61-5:3, 9:7-10:29, 11:57-
`
`frequency transitions.
`
`(claim 1)
`transitions”
`clock frequency
`enable user selectable
`application programto
`controlledby said
`programmably
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 11 of 18
`
`
`
`2, claim 5.
`047696, ¶¶ [0027]–[0030], [0045], [0074], Figs.1,
`Certified Translation of Japanese Patent 2002-
`
`11:50–57.
`6:50–58, 7:28–37, 8:20–24, 9:19–23, 10:31–46,
`’519 Patent: Figs. 1, 2; 5:4–10, 5:30–40, 6:17–26,
`
`CC hearing)
`for responding to inputs(Alternative based on
`the processor cores but not circuitry responsible
`
`OR
`
`devices, or interrupts
`for responding to inputs,such as peripheral
`the processor cores but not circuitryresponsible
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`Dictionary (6th ed. 1997) at 107.
`Sclater, N. & Markus, J., McGraw Hill Electronics
`Computing (McGraw-Hill 10th ed. 1993) at 161;
`“cutoff”: McDaniel, G., IBM Dictionary of
`Technical Terms (6th Ed. 2003) at 953.
`“halt”: McGraw-Hill Dictionary of Scientific and
`
`Fig. 5, claim 5.
`047696, ¶¶ [0027]–[0030], [0048], [0076], [0077],
`Certified Translation of Japanese Patent 2002-
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`-12-
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`11:50–57.
`6:50–58, 7:28–37, 8:20–24, 9:19–23, 10:31–46,
`’519 Patent: Figs. 1, 2; 5:4–10, 5:30–40, 6:17–26,
`
`the processor cores
`
`(claim 1)
`processing unit”
`of said central
`“principal constituents
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`IEEE Standards Terms (7th ed. 2000) at 502;
`“haltinstruction”: The Authoritative Dictionary of
`
`Standards Terms (7th ed. 2000) at 502;
`“halt”: The Authoritative Dictionary of IEEE
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 12 of 18
`
`
`
`“register”:Laplante, P.A., Comprehensive
`
`Reference Numerals, Figs. 1, 3, claim6.
`047696, ¶¶ [0029],[0030], [0048], Explanation of
`Certified Translation of Japanese Patent 2002-
`
`’519 Patent:Figs. 1, 3; 5:21–23, 7:45–53, 9:51–58.
`
`indefinite
`
`citations.
`See supra, “clock control library … ,” additional
`
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`8b, 9, claims 1–8.
`Explanation of Reference Numerals, Figs. 5, 7, 8a,
`047696, ¶¶ [0005], [0078], [0086], [0091]–[0093],
`Certified Translation of Japanese Patent 2002-
`
`Action, Apr. 19, 2004.
`’519 Patent, File History, Response to Office
`Response to Office Action, Sept. 22, 2003;
`’519 Patent, File History, Amendment and
`
`12:23; 13:5–24.
`’519 Patent: Figs. 5, 6, 7, 8a, 8b; 11:18–22, 11:66–
`
`Defendant’s Proposed Construction and
`
`indefinite
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`Evidence
`
`-13-
`
`ed. 1999) at 734.
`Graf, R.F.,Modern Dictionary of Electronics (7th
`“status register”:
`
`’519 Patent: 5:20-23, 27-29, 7:45-57
`
`state ofthe CPU is stored
`astatus register in which the information of the
`
`mode”(claim 7)
`said third special
`being released from
`immediately after
`central processing unit
`judges a state of said
`“a status register that
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`45,11:18–22, 11:66–12:23; 13:5–24,Cl. 2
`’519 Patent: ’519 Patent: Figs. 5, 6, 7, 8a, 8b; 4:30-
`
`necessary.
`Plain and ordinary meaning, no construction
`
`(claim2)
`said libraries”
`and selects any one of
`application program
`is called by said
`“a main library which
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 13 of 18
`
`
`
`Declaration of Dr. Albonesi, Dkt. 40-1.
`
`1999) at 541.
`Dictionary of Electrical Engineering (CRC Press
`
`Defendant’s Proposed Construction and
`
`Evidence
`
`-14-
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`2005) at 662.
`Dictionary of Electrical Engineering(CRC Press
`“store instruction”LaPlant, P.A., Comprehensive
`
`Plaintiff’s Proposed Construction and Evidence
`U.S. Patent 6,895,519
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 14 of 18
`
`
`
`3:45-58, cl. 1.
`‘614 Patent: Fig. 1, Fig. 2, 2:3-7, 2:16-23, 3:11-17,
`regular arrangement or pattern
`a plurality of said first and second unit cells laid in a
`Declaration of Dr. Holberg, Dkt. 40-2.
`
`Design(2d ed. 1993) at 407-409.
`Weste, Neil H. E. et al, Principles of CMOS VLSI
`
`Electrical Engineering(CRC Press 1999)at 606;
`Laplante, P.A., Comprehensive Dictionary of
`
`Electronics (7th ed. 1999) at 729;
`“standard cell”: Graf, R.F.,Modern Dictionary of
`
`2000-208713, Abstract ¶¶ [0004], [0011], [0021].
`Certified Translation of Japanese Patent Application
`
`6:24-28, cl. 1.
`’614 Patent: Fig. 1, Fig. 2, 1:51-2:7,2:14-25, 3:45-58,
`
`gate array system(Alternative based on CC hearing)
`semiconductor integrated circuits implemented by a
`
`OR
`
`cell
`gate array system, cannot be a conventional standard
`semiconductor integrated circuits implemented by a
`Defendant’s Proposed Construction and Evidence
`
`-15-
`
`3:45-58, 5:14-24; 5:49-63; 6:46-55
`‘614 Patent: Fig. 1, Fig. 2,Fig. 3,2:14-25, 3:7-22,
`
`necessarily in a regular arrangement or pattern.
`An arrangement of first and second unit cells, not
`
`second unit
`first and
`comprised of
`array
`“a unit cell
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`no. 16, 22 (Apr. 2009) at 2.
`Nanoprocessor System, Nanotechnology, vol. 20,
`and Analysis of a CMOS/Nano Hybrid
`Cabe, A. and Das, S., Performance Simulation
`
`3:45-58,5:14-24; 5:49-63; 6:46-55
`‘614 Patent: Fig. 1, Fig. 2,Fig. 3,2:14-25, 3:7-22,
`
`functions (Alternative based on CC hearing)
`logic elements that perform Boolean or storage
`
`OR
`
`U.S. Patent 6,239,614
`
`logic elements of which a unit cell array is comprised
`Plaintiff’s Proposed Construction and Evidence
`
`Exhibit B
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 15 of 18
`
`(claim 1)
`“unit cells”
`Term
`
`
`
`-16-
`
`2, 3.
`’614 Patent: 2:20-25, 3:11-22, 3:55-62, 4:30-33, cl. 1,
`
`4:30-33, 6:56-59,6:62-64, 6:66-67
`‘614 Patent: Fig. 1, Fig. 2,2:14-25, 3:11-22, 3:55-59,
`
`a switch including a PMOS and an NMOS transistor
`
`Plain and ordinary meaning;
`
`3)
`(claims 1, 2,
`switch”
`“a power
`
`See supra, “a unit cell array …”
`
`Declaration of Dr. Holberg, Dkt. 40-2.
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`1999) at 544.
`Graf, R.F.,Modern Dictionary of Electronics (7th ed.
`“pattern”:
`
`1999) at 37.
`Graf, R.F.,Modern Dictionary of Electronics (7th ed.
`“array”:
`
`3:45-58, 5:14-24; 5:49-63; 6:46-55
`‘614 Patent: Fig. 1, Fig. 2,Fig. 3,2:14-25, 3:7-22,
`
`or pattern
`a plurality of unit cells laid in a regular arrangement
`
`regular arrangement or pattern.
`An arrangement of unit cells, not necessarily in a
`
`(claims 1, 3)
`array”
`“unit cell
`
`(claim 1)
`array form”
`cells laid in
`
`Term
`
`See supra, “unit cells,” additional citations.
`Declaration of Dr. Holberg, Dkt. 40-2.
`1999) at 37.
`Graf, R.F.,Modern Dictionary of Electronics (7th ed.
`(10th ed. 2001) at 64;
`“array”: Merriam-Webster’s Collegiate Dictionary
`Defendant’s Proposed Construction and Evidence
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`1999) at 544.
`Graf, R.F.,Modern Dictionary of Electronics (7th ed.
`“pattern”:
`
`1999) at 37.
`Graf, R.F.,Modern Dictionary of Electronics (7th ed.
`“array”:
`
`U.S. Patent 6,239,614
`
`Plaintiff’s Proposed Construction and Evidence
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 16 of 18
`
`
`
`-17-
`
`aroundsaid unit cell array.”
`aroundsaid unit cell array and comprised of a plurality of third MOS transistors” “a plurality of input / output circuits disposed
`3The parties have agreed that “disposed around” is the disputed term for both previously proposed terms “a power switch disposed
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(10th ed. 2001) at 335.
`“disposed”: Merriam-Webster’s Collegiate Dictionary
`2001) at 63.
`Merriam-Webster’s Collegiate Dictionary (10th ed.
`Dictionary(2002) at 120;
`“around”: Webster's Third New International
`
`‘614 Patent: Fig. 1, Fig. 2, 2:20-25, 3:11-22, cl. 1.
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`based on CC hearing)
`located along the entirety of allsides(Alternative
`
`Dictionary(2002) at 120;
`“around”: Webster’s Third New International
`
`OR
`
`‘614 Patent: Fig. 1, Fig. 2,2:14-25, 6:56-59
`
`encircling
`Declaration of Dr. Holberg, Dkt. 40-2.
`
`Collegiate Dictionary (10thed. 2001) at 1189).
`Electronics (7th ed. 1999) at 751; Merriam-Webster’s
`“switch”:Graf, R.F.,Modern Dictionary of
`
`Electronics (7th ed. 1999) at 583;
`“power switch”:Graf, R.F.,Modern Dictionary of
`
`located on all sides of
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`Defendant’s Proposed Construction and Evidence
`
`Plaintiff’s Proposed Construction and Evidence
`
`U.S. Patent 6,239,614
`
`(claim 1)
`around”3
`“disposed
`
`Term
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 17 of 18
`
`
`
`Declaration of Dr. Holberg, Dkt. 40-2.
`(10th ed. 2001) at 603.
`“inside”: Merriam-Webster’s Collegiate Dictionary
`(10th ed. 2001) at 1355.
`“within”: Merriam-Webster’s Collegiate Dictionary
`(10th ed. 2001) at 335.
`“disposed”: Merriam-Webster’s Collegiate Dictionary
`
`‘614 Patent: Fig. 2, 3:55-59, 4:30-37, cl. 1, 2, 3.
`
`based on CC hearing)
`are located inside the unit cell array(Alternative
`some of the third MOS transistors of the power switch
`
`OR
`
`are located inside the unit cell array
`a portion of the plurality of the third MOS transistors
`Declaration of Dr. Holberg, Dkt. 40-2.
`Defendant’s Proposed Construction and Evidence
`
`-18-
`
`Declaration of Vojin Oklobdzija, ECF No. 41-7.
`
`4:30-33, 6:56-59,6:62-64, 6:66-67
`‘614 Patent: Fig. 1, Fig. 2,2:14-25, 3:11-22, 3:55-59,
`
`switch located within said unit cell array
`Plain and ordinary meaning; parts of said power
`
`U.S. Patent 6,239,614
`
`Plaintiff’s Proposed Construction and Evidence
`
`Case 1:18-cv-00554-LY Document 54 Filed 11/01/19 Page 18 of 18
`
`(claim 3)
`unit cell array”
`within said
`disposed
`power switch
`“parts of said
`
`Term
`
`