Advanced Micro Devices, Inc.
`Petitioner
`v.
`Aquila Innovations, Inc.
`Patent Owner
`____________
`
`IPR2019-01526 (Patent No. 6,895,519)
`
`December 11, 2020
`
`1
`
`AMD EX1033
`AMD v. Aquila
`IPR2019-01526
`
`
`Petitioner
`v.
`Aquila Innovations, Inc.
`Patent Owner
`____________
`
`IPR2019-01526 (Patent No. 6,895,519)
`
`December 11, 2020
`
`1
`
`AMD EX1033
`AMD v. Aquila
`IPR2019-01526
`
`
`
`Agenda
`
`– Overview of the ’519 patent
`– Claim construction
`– Ober + Nakazato and “a plurality of ordinary operation modes”
`– Claims 2-6 and Windows ACPI
`– Claims 8 & 9 and Doblar
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`2
`
`
`
`Instituted Grounds
`
`IPR2019-01526 (’519 Patent)
`
`Claim(s)
`
`References
`
`Ground 1
`
`1, 7, 10, 11
`
`Ober and Nakazato
`
`Ground 2
`
`Ground 3
`
`2-6
`
`8, 9
`
`Ober, Nakazato, Cooper and Windows ACPI
`
`Ober, Nakazato and Doblar
`
`DI, 70; Pet., 2.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`3
`
`
`
`Introduction to ’519 Patent
`
`EX1001, ’519 patent, Figs. 5 and 9; Pet., 3.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`4
`
`
`
`’519 Patent – Claim 1
`
`Claim 1
`[1.p] A system LSI having a plurality of ordinary operation modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit, comprising:
`[1.1] a first memory that stores a clock control library for controlling a clock frequency transition between said ordinary
`operation modes;
`[1.2] a system control circuit which has a register, wherein said system control circuit carries out the clock frequency
`transition between said ordinary operation modes and said special modes in response to a change of a value in said
`register, and also carries out the clock frequency transition among said ordinary operation modes in response to
`said clock control library;
`[1.3] a clock generation circuit that receives a plurality of standard clocks, wherein said clock generation circuit generates a
`clock supplied to said central processing unit according to control by said system control circuit; and
`[1.4] a second memory that stores an application program, wherein calling of said clock control library and changing of said
`register value are programmably controlled by said application program to enable user selectable clock frequency
`transitions,
`[1.5] wherein said special modes comprise a first special mode in which clock supply to principal constituents of said
`central processing unit is halted, a second special mode in which clock supply to an entirety of said central processing unit
`is halted, and a third special mode in which supply of power to the entirety of said central processing unit is halted.
`
`’519 patent, 14:15-46.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`5
`
`
`
`’519 Patent – Undisputed Elements
`
`Claim 1
`[1.p] A system LSI having a plurality of ordinary operation modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit, comprising:
`[1.1] a first memory that stores a clock control library for controlling a clock frequency transition between said ordinary
`operation modes;
`[1.2] a system control circuit which has a register, wherein said system control circuit carries out the clock frequency
`transition between said ordinary operation modes and said special modes in response to a change of a value in said
`register, and also carries out the clock frequency transition among said ordinary operation modes in response to said clock
`control library;
`[1.3] a clock generation circuit that receives a plurality of standard clocks, wherein said clock generation circuit generates a
`clock supplied to said central processing unit according to control by said system control circuit; and
`[1.4] a second memory that stores an application program, wherein calling of said clock control library and changing of said
`register value are programmably controlled by said application program to enable user selectable clock frequency
`transitions,
`[1.5] wherein said special modes comprise a first special mode in which clock supply to principal constituents of said
`central processing unit is halted, a second special mode in which clock supply to an entirety of said central processing unit
`is halted, and a third special mode in which supply of power to the entirety of said central processing unit is halted.
`
`Undisputed
`
`’519 patent, 14:15-46; POR, i-ii..
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`6
`
`
`
`Claim Construction
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`7
`
`
`
`Disputed Issues – Claim Construction
`
`1. A system LSI having a plurality of ordinary operation modes and
`a plurality of special modes in response to clock frequencies supplied
`to a central processing unit, comprising:
`
`Patent Owner’s Proposed Constructions
`
`AMD’s Proposed Constructions
`
`“The Board should construe ‘plurality of ordinary
`operation modes’ to require that the CPU execute
`instructions at different frequencies.”
`
`• Does not require CPU to execute instructions
`• Dispute is non-dispositive
`
`POR, 25; Pet. Reply, 1-5.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`8
`
`
`
`CPUs Execute Instructions During Normal Operations
`
`Nakazato:
`
`EX1008, Nakazato, Abstract.
`
`Patent Owner’s Expert:
`Q: [I]f one were to divide the system clock,
`you would agree with me that would affect
`the frequency of the CPU. Correct? . . .
`
`A: If you divide the system clock during run
`mode, that would affect the frequency of
`the core and the execution of
`instructions.
`EX1029, Pryzybyslki Depo Trans., 90:9-16 (emphasis added).
`
`Pet. Reply, 3-4, 6.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`9
`
`
`
`Ober in View of Nakazato
`Discloses “a plurality of ordinary
`operation modes”
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`10
`
`
`
`Petition Relies on Both Ober and Nakazato
`
`“Ordinary operation modes” is defined over several claim elements
`
`Claim 1
`[1.p] A system LSI having a plurality of ordinary operation modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit, comprising:
`[1.1] a first memory that stores a clock control library for controlling a clock frequency transition between said ordinary
`operation modes;
`[1.2] a system control circuit which has a register, wherein said system control circuit carries out the clock frequency
`transition between said ordinary operation modes and said special modes in response to a change of a value in said
`register, and also carries out the clock frequency transition among said ordinary operation modes in response to
`said clock control library;
`[1.3] a clock generation circuit that receives a plurality of standard clocks, wherein said clock generation circuit generates a
`clock supplied to said central processing unit according to control by said system control circuit; and
`[1.4] a second memory that stores an application program, wherein calling of said clock control library and changing of said
`register value are programmably controlled by said application program to enable user selectable clock frequency
`transitions,
`[1.5] wherein said special modes comprise a first special mode in which clock supply to principal constituents of said
`central processing unit is halted, a second special mode in which clock supply to an entirety of said central processing unit
`is halted, and a third special mode in which supply of power to the entirety of said central processing unit is halted.
`
`’519 patent, 14:15-46.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`11
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`The Board agrees that the “varying” CPU frequencies is discussed in element [1.1]:
`
`DI, 19.
`
`DI, 19.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`12
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`The Petition explained “ordinary operation modes” in multiple different elements:
`
`[Preamble]: Adjusting system clock frequency adjusts the frequency of the CPU
`
`Pet., 24.
`
`Pet., 24.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`13
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`The Petition explained “ordinary operation modes” in multiple different elements:
`
`[Element 1.1]: A POSA could have used Register 62 to effectuate CPU frequency
`changes in Ober during “ordinary operations”:
`
`Pet., 27.
`
`Pet., 27.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`14
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Nakazato describes adjusting CPU frequency during ordinary operations, and
`describes the software mechanisms that accomplish such adjustments:
`
`Pet., 17.
`
`Pet., 17-18.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`15
`
`Pet., 18.
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Nakazato discloses a CPU executing instructions at different frequencies
`
`Nakazato, 5:44-49.
`
`Nakazato, Abstract.
`
`Pet., 17-18; Pet. Reply, 3-4.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`16
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Ober discloses operating at different CPU clock speeds
`
`Ober’s SFR register 116
`
`EX1004, Ober, 9:65-10:2.
`Ober’s SFR register 62
`
`Ober, 11:31-33.
`
`Pet., 17, 27; Pet. Reply, 6; POR, 12.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`17
`
`Ober, 12:14-33.
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`A POSITA would have been motivated to combine Ober and
`Nakazato to achieve a “plurality of ordinary operation modes”
`
`Patent Owner’s Expert:
`Q: [I]t was known before the '519 patent that you could
`use CPU frequency adjustments to -- for dynamic
`power management. Right?
`
`A: Yes, that idea was known in the art.
`EX1029, 54:20-55:2.
`
`Dr. Albonesi:
`
`EX1003, Albonesi Decl., ¶ 88.
`
`Pet., 17; Pet. Reply, 4.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`18
`
`EX1028, Albonesi Reply Decl., ¶ 17.
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Adjusting Ober’s system clock adjusts Ober’s CPU’s frequency
`
`Ober, 11:31-33.
`
`Patent Owner’s Expert:
`
`EX1029, 90:14-16.
`
`Ober, Fig. 1 (annotated).
`
`Pet., 27; Pet. Reply, 6-7.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`19
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Ober in view of Nakazato Discloses “plurality of ordinary operation
`modes,” even under PO’s construction
`
`Nakazato, 5:44-49.
`
`Nakazato, Abstract.
`
`Nakazato, 7:19-24;
`Fig. 2.
`
`Pet., 17-18; Pet. Reply, 3-5, 29-30.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`20
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Patent Owner’s Arguments
`
`Ober’s Register 116 never adjusts the clock of the CPU
`Ober’s CPU is incapable of operating at reduced clock speeds
`If a POSITA wrote to “undefined” bits of register 62, it would cause
`unpredictable behavior
`If a POSITA reduced CPU clock during normal operations, Ober’s state
`machine would behave unpredictably
`If a POSITA divided Ober’s system clock, Ober’s peripherals would behave
`unpredictably
`Ober teaches away from Nakazato because Ober is “decentralized” and
`Nakazato is “centralized”
`
`POR, 29-30, 35, 43, 44, 46, 48, 52, 55-58.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`21
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Patent Owner: Ober’s Register 116 never adjusts the clock of the CPU
`Patent Owner:
`
`POR, 29.
`But the Petition describes modifying register 62, NOT register 116:
`
`Pet., 28.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`22
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Ober’s clock division applies to Ober’s CPU
`See Pet., 16-17.
`
`Ober, 7:36-41.
`
`Pet. Reply, 9; Pet., 22-23.
`
`Ober, Fig. 1 (annotated); Pet. Reply, 9; Pet., 22-23.
`
`Pet., 32.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`23
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Ober’s CPU is incapable of operating at reduced clock speeds
`Ober:
`
`Patent Owner:
`
`POR, 35.
`
`But:
`• Nothing in Ober links “ Low Speed Clocks” to system clock
`
`Ober, 17:15-26.
`
`changed
`In the proposed combination a POSA would simply have set “ Low
`Speed Clocks” to “ true”
`
`•
`
`Pet. Reply, 10-12.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`24
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`If a POSITA wrote to “undefined” bits of register 62, it would cause
`unpredictable behavior
`
`Patent Owner:
`
`Dr. Albonesi:
`
`POR, 44.
`
`EX1028, ¶ 49.
`
`Pet. Reply, 7, 15-16.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`25
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`If a POSITA reduced CPU clock during normal operations, Ober’s state
`machine would behave unpredictably
`
`That something “might” or “may” behave unpredictably is not enough
`Pet. Reply, 16-17.
`
`Patent Owner:
`
`POR, 48.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`26
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`If a POSITA reduced CPU clock during normal operations, Ober’s state
`machine would behave unpredictably
`
`EX1028, ¶ 52.
`
`Pet. Reply, 15, 17.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`27
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`If a POSITA divided Ober’s system clock, Ober’s peripherals would behave
`unpredictably
`
`Patent Owner:
`
`POR, 52.
`
`But as Dr. Albonesi
`Explains:
`
`EX1028, ¶ 44.
`
`Pet. Reply, 18.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`28
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Ober teaches away from Nakazato because Ober is “decentralized” and
`Nakazato is “centralized”
`
`But Ober is not “decentralized”:
`
`Petitioner’s Expert:
`
`Ober, 5:37-41.
`
`Patent Owner’s Expert:
`
`EX1029, 71:22-72:2.
`
`EX1028, ¶ 39-40.
`Pet., 23; Pet. Reply, 19.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`29
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Ober teaches away from Nakazato because Ober is “decentralized” and
`Nakazato is “centralized”
`
`The Petition does not propose modifying any core functionality of Ober:
`
`Pet. Reply, 19.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`30
`
`
`
`GROUND 2:
`Ober, Nakazato, Cooper and
`Windows ACPI
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`31
`
`
`
`Claim 2
`
`2. A system LSI as claimed in claim 1, wherein said
`clock control library comprises:
`a plurality of libraries that control said system
`control circuit and said clock generation circuit to
`transition the clock frequencies supplied to said
`central processing unit; and
`a main library which is called by said application
`program and selects any one of said libraries in
`correspondence with the clock frequency supplied to
`said central processing unit.
`‘519 patent, 14:47-57.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`32
`
`
`
`Disputed Issues – Windows ACPI Qualifies as Prior Art
`
`Paper 32, 3.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`33
`
`
`
`Disputed Issues – Windows ACPI Is Authentic
`
`Wayback machine:
`
`Albonesi Reply Declaration:
`
`Albonesi Petition Declaration:
`
`EX1028, ¶ 61.
`
`EX1003, ¶ 43.
`
`EX1021, 1.
`
`Pet., 12-13; Pet. Reply, 23-24.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`34
`
`
`
`Disputed Issues – Windows ACPI Is Authentic
`
`EX1005 is Self-Authenticating:
`
`EX1005, 1.
`
`Pet., 12-13; Paper 32, 3-4.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`35
`
`
`
`Disputed Issues – Ober + Nakazato + Cooper + Windows ACPI
`
`Petition explained motivation for incorporating ACPI
`
`Pet., 52.
`
`Pet., 56.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`36
`
`
`
`Disputed Issues – Ober + Nakazato + Cooper + Windows ACPI
`
`Patent Owner’s Argument:
`Ober and Nakazato must be ACPI-incompatible
`because they do not state they are ACPI-compatible
`
`POR, 63.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`37
`
`
`
`Disputed Issues – Ober + Nakazato + Cooper + Windows ACPI
`
`Patent Owner does not cite to any expert opinion that Ober is ACPI incompatible
`
`Petitioner’s Expert:
`
`EX1028, ¶ 54.
`
`Patent Owner’s Expert:
`Q: So a hardware manufacturer would have some
`motivation to support something like ACPI because
`that would allow their system to [] leverage the
`standardized support of ACPI. Right? . . .
`
`A: Yes, if [] you were interested in providing dynamic
`power management, then they would be motivated to
`use a standard, as opposed to their own system. . . .
`EX1029, 162:20-163:12.
`
`Pet. Reply, 22-23.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`38
`
`
`
`Ground 3:
`Ober, Nakazato and Doblar
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`39
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar
`
`Claim 8
`
`Claim 9
`
`8. A system LSI as claimed in claim 1, wherein said
`clock generation circuit comprises:
`a PLL that receives a plurality of standard clocks and
`generates the clock if needed by multiplying said
`standard clocks; and
`a frequency division/selection portion that carries out
`frequency division or selection of said standard clocks
`or said multiplied standard clock.
`
`’519 Patent, 15:14-16:6.
`
`9. A system LSI as claimed in claim 8, wherein one of said
`standard clocks uses a frequency of 32.768 kHz as a base
`oscillation.
`
`’519 Patent, 16:7-16:9.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`40
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar
`
`Doblar Figure 4:
`
`Modification to Ober:
`
`Doblar, 3:39-43, FIG. 4.
`
`Pet., 67.
`
`Pet., 66-67.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`41
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar
`
`The Petition established a Motivation to Combine Ober and Nakazato with Doblar
`
`Pet., 64-65.
`
`Pet., 65.
`
`Pet., 66-67.
`
`Pet., 64-67.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`42
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar Motivation to Combine
`
`Patent Owner:
`
`POR, 68.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`43
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar Motivation to Combine
`
`Ober’s “Fault” Mode
`
`Pet., 48; Pet. Reply, 26.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`44
`
`Ober, 16:45-67.
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar Motivation to Combine
`
`Attorney argument only; Failsafes not redundant
`Pet. Reply, 26.
`
`EX1028, ¶ 65.
`
`EX1028, ¶ 65.
`
`Ober, 16:55-57.
`
`Pet. Reply, 26.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`45
`
`
`
`Disputed Issues – Ober + Nakazato + Doblar Motivation to Combine
`
`Even if redundant, would be beneficial to have multiple failsafes
`Pet. Reply, 26-27.
`
`Pet. Reply, 26.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`46
`
`EX1028, ¶ 66.
`
`
`
`Appendix
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`47
`
`
`
`Disputed Issues – “Plurality of Ordinary Operation Modes”
`
`Patent Owner: Ober’s Register 116 never adjusts the clock of the CPU
`
`Register 62 divides the system clock, while registers 117 divides the clock to the subsystems
`
`Ober’s Table 5: register 62
`
`Ober’s Table 4: registers 117
`
`Ober, 11:1-13.
`
`Ober, 9:31-47.
`
`Pet., 27.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`48
`
`
`
`Disputed Issues – EX1005 Qualifies as Prior Art
`
`Step 1: Navigate
`to Microsoft.com
`Step 2: Click
`“Windows” under
`“Product Families”
`
`Pet. Reply, 23-25.
`
`EX1028, ¶ 57; EX1030, 0001.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`49
`
`
`
`Disputed Issues – EX1005 Qualifies as Prior Art
`
`Step 3: Click “Windows
`Driver & Hardware
`Development” under
`“For Developers”
`
`Pet. Reply, 23-25.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`50
`
`EX1028, ¶ 58; EX1031, 0001.
`
`
`
`Disputed Issues – EX1005 Qualifies as Prior Art
`
`Step 3: Click “OnNow
`and ACPI Resources”
`under “More Topics of
`Interest”
`
`Pet. Reply, 23-25.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`51
`
`EX1028, ¶ 59; EX1032, 0001.
`
`
`
`Disputed Issues – EX1005 Qualifies as Prior Art
`
`Step 4: Click “ACPI
`Driver Interface Design
`Notes and References”
`under “White Papers”
`
`EX1028, ¶ 60; EX1020, 0001.
`
`EX1028, ¶ 61.
`
`Pet. Reply, 23-25.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`52
`
`
`
`Disputed Issues – EX1005 Qualifies as Prior Art
`
`Step 5: Open
`downloaded .zip file
`
`Paper 32, 3.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`53
`
`
`
`Disputed Issues – EX1005 Qualifies as Prior Art
`
`Step 6: unzip .zip file
`contents
`
`Pet., 12-13; Pet. Reply, 24-25; EX1005, 0001.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`54
`
`
`
`Disputed Issues – Board’s Application of Ober Is Proper
`
`The Petition relied on the challenged portion of Ober
`Pet. Reply, 20.
`
`Pet. Reply, 20-21.
`
`Pet. Reply, 21.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`55
`
`
`
`Disputed Issues – Board’s Application of Ober Is Proper
`
`The Board’s reliance on the challenged portion of Ober follows legal precedent
`Pet. Reply, 21.
`
`Pet. Reply, p. 21
`
`Pet. Reply, 21.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`56
`
`
`
`’519 Patent – Undisputed Issues
`
`Ober discloses a “system LSI”
`
`Pet., 19.
`
`Pet., 24.
`
`Pet., 19-25.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`57
`
`Ober, FIG. 1 (annotated); Pet., 22.
`
`
`
`’519 Patent – Undisputed Issues
`
`Ober in view of Nakazato discloses a “clock control library”
`
`Nakazato, 6:19-21.
`
`Nakazato, 7:3-6.
`
`Pet., 18, 25-31.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`58
`
`Nakazato, FIG. 2.
`
`
`
`’519 Patent – Undisputed Issues
`
`Ober discloses a “system control circuit . . . [that] carries out the
`clock frequency transition . . . ”
`
`Ober, 3:51-56.
`
`Ober, 7:36-41.
`
`Ober, 10:16-28.
`
`Pet., 32-34.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`59
`
`
`
`’519 Patent – Undisputed Issues
`
`Ober discloses a “clock generation circuit that receives a plurality of
`standard clocks”
`
`Ober, 8:53-58.
`
`Ober, 9:4-8.
`
`Pet., 32-34.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`60
`
`Ober, FIG. 3 (annotated); Pet., 35.
`
`
`
`’519 Patent – Undisputed Issues
`
`Ober in view of Nakazato discloses a “second memory that stores an
`application program . . .”
`
`Ober, 5:50-53.
`
`Nakazato, 7:19-24.
`
`Pet., 37-40.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`61
`
`Nakazato, FIG. 2.
`
`
`
`’519 Patent – Undisputed Issues
`
`Ober discloses the first, second and third “special modes”
`
`First Special Mode
`
`Ober, 15:14-16.
`
`Second Special Mode
`
`Ober, 16:9-15.
`
`Third Special Mode
`
`Pet., 40-44.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`62
`
`Ober, 16:9-15.
`
`
`
`Undisputed Issues
`
`IPR2019-01526 (’519 Patent)
`Ober discloses the claimed system LSI having a plurality of special modes
`
`Ober discloses the claimed system control circuit
`
`Ober discloses the claimed clock generation circuit
`
`Ober in view of Nakazato discloses the claimed second memory
`Ober discloses wherein said special modes comprise a first special mode .
`. ., a second special mode . . ., and a third special mode
`Ober in view of Nakazato discloses dependent claims 7, 10 and 11
`Ober in view of Nakazato, Cooper and Windows ACPI discloses dependent
`claims 2-6
`Ober in view of Nakazato and Doblar discloses dependent claims 8 and 9
`
`POR, i-ii.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`63
`
`
`
`’519 Patent Admissions
`
`“Ordinary operation
`modes” were well-known
`
`“Special modes” were well-known
`
`Software control of ordinary
`and special modes was known
`
`’519 Patent’s Background:
`
`’519 patent, 1:56-61.
`
`’519 patent, 2:63-67.
`
`’519 patent, 3:6-10.
`
`Pet., 1.
`
`Petitioner’s Demonstrative Exhibit - Not Evidence
`
`64
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
