UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`AQUILA INNOVATIONS, INC., a
`Delaware Corporation,
`
`Plaintiff,
`
`v.
`ADVANCED MICRO DEVICES, INC.,
`a Delaware corporation
`Defendant.
`
`No. 1:18-cv-554-LY
`
`
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`
`AQUILA INNOVATIONS, INC.’S
`PRELIMINARY INFRINGEMENT CONTENTIONS
`Pursuant to the Court’s Scheduling Order, D.I.23, Plaintiff Aquila
`
`
`
`Innovations, Inc. (“Aquila”) submits the following preliminary infringement
`
`contentions for U.S. Patents 6,239,614 (“’614 Patent”) and 6,895,519 (“’519 Patent”).
`
`These preliminary infringement contentions were prepared without the benefit of
`
`the Court’s claim construction or the parties’ exchange of constructions. Discovery
`
`has been stayed, and AMD has not produced any information concerning the
`
`Accused Products. Thus, this chart is based on publicly available evidence, and
`
`based upon information and reasonable belief in light of such evidence. As such,
`
`Aquila reserves the right to amend or supplement its contentions to address any
`
`issues arising from the Court’s constructions or to account for new information that
`
`becomes available.
`
`
`
`AMD EX1012
`U.S. Patent No. 6,895,519
`
`0001
`
`
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`AQUILA INNOVATIONS, INC., a
`Delaware Corporation,
`
`Plaintiff,
`
`v.
`ADVANCED MICRO DEVICES, INC.,
`a Delaware corporation
`Defendant.
`
`No. 1:18-cv-554-LY
`
`
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`
`AQUILA INNOVATIONS, INC.’S
`PRELIMINARY INFRINGEMENT CONTENTIONS
`Pursuant to the Court’s Scheduling Order, D.I.23, Plaintiff Aquila
`
`
`
`Innovations, Inc. (“Aquila”) submits the following preliminary infringement
`
`contentions for U.S. Patents 6,239,614 (“’614 Patent”) and 6,895,519 (“’519 Patent”).
`
`These preliminary infringement contentions were prepared without the benefit of
`
`the Court’s claim construction or the parties’ exchange of constructions. Discovery
`
`has been stayed, and AMD has not produced any information concerning the
`
`Accused Products. Thus, this chart is based on publicly available evidence, and
`
`based upon information and reasonable belief in light of such evidence. As such,
`
`Aquila reserves the right to amend or supplement its contentions to address any
`
`issues arising from the Court’s constructions or to account for new information that
`
`becomes available.
`
`
`
`AMD EX1012
`U.S. Patent No. 6,895,519
`
`0001
`
`
`
`(a) Identification of asserted claims
`
`’614 Patent: Claims 1, 2
`
`’519 Patent: Claims 1, 2, 3, 5, 6, 7, 10
`
`(b) Identification of accused products
`’614 Patent Accused Products:
`
`
`
`
`
`Aquila contends that all AMD processor products containing power gate rings
`
`infringe each of the asserted claims of the ’614 Patent. This specifically includes but
`
`is not limited to processors with cores having microarchitectures belonging to the
`
`following families:
`
`o AMD 12h Llano Fusion APUs
`o AMD 15h Bulldozer APUs
`o AMD 15h Piledriver APUs
`o AMD 15h Excavator APUs
`AMD products belonging to each product family are identified in Exhibits C.1
`
`through C.4. The identification of specific products was prepared without the
`
`benefit of discovery from AMD and may not include OEM or custom processor
`
`products. Aquila reserves the right to amend or supplement its identification of
`
`accused products as AMD provides more information.
`
`’519 Patent Accused Products:
`
`Aquila contends that all AMD processor products capable of entering/exiting
`
`the CC1, PC1, and PC6 states infringe each of the asserted claims of the ’519 Patent.
`
`This specifically includes but is not limited to processors with cores having
`
`microarchitectures belonging to the following families:
`
`-2-
`
`0002
`
`
`
`o AMD Family 12h
`o AMD Family 14h
`o AMD Family 15h
`o AMD Family 16h
`o AMD Family 17h
`AMD products belonging to each product family are identified in Exhibits C.1
`
`through C.5. The identification of specific products was prepared without the
`
`benefit of discovery from AMD and may not include OEM or custom processor
`
`products. Aquila reserves the right to amend or supplement its identification of
`
`accused products as AMD provides more information.
`
`(c) Claim Charts
`
`Claim charts for each asserted claim corresponding to each representative
`
`accused product are contained in the exhibits below.
`
`
`
`
`
`
`
`’614 Patent: Exhibit A
`
`’519 Patent: Exhibit B
`
`(d) Doctrine of Equivalents
`
`Aquila contends that each limitation in each asserted claim is met literally.
`
`The Court has not construed the asserted claims, and AMD has not yet provided
`
`discovery on the accused products or provided non-infringement contentions. Aquila
`
`reserves the right to respond if AMD provides non-infringement contentions, which
`
`response may include doctrine of equivalents contentions.
`
`
`
`-3-
`
`0003
`
`
`
`(e) Identification of Priority Date
`
`
`
`’614 Patent: Each asserted claim of the ’144 Patent is entitled to a priority
`
`date as late as January 14, 1999.
`
`
`
`’519 Patent: Each asserted claim of the ’519 Patent is entitled to a priority
`
`date as late as February 25, 2002.
`
`
`
`Dated: February 13, 2019
`
`
`
`
`
`Respectfully submitted,
`
`
`
`
`
`
`/s/Jing H. Cherng
`Robert E. Freitas (admitted pro hac vice)
`Jing H. Cherng (admitted pro hac vice)
`FREITAS & WEINBERG LLP
`350 Marine Parkway, Suite 200
`Redwood Shores, CA 94065
`Telephone: (650) 593-6300
`rfreitas@fawlaw.com
`gcherng@fawlaw.com
`
`
`Henry B. Gonzalez III
`State Bar No. 00794952
`Jeffrie B. Lewis
`State Bar No. 24071785
`GONZALEZ, CHISCANO, ANGULO,
`& KASSON, PC
`9601 McAllister Freeway, Suite 401
`San Antonio, Texas 78216
`Tel: (210) 569-8500
`hbg@gcaklaw.com
`jlewis@gcaklaw.com
`
`Attorneys for Plaintiff
`Aquila Innovations, Inc.
`
`-4-
`
`0004
`
`
`
`I hereby certify that on this 13th day of February, 2019, a true and correct
`copy of the foregoing was forwarded to the following:
`Jennifer Librach Nall
`Kevin J. Meek
`Aashish Kapadia
`Puneet Kohli
`jennifer.nall@bakerbotts.com
`kevin.meek@bakerbotts.com
`aashish.kapadia@bakerbotts.com
`puneet.kohli@bakerbotts.com
`DLWiLAN_AMD_BakerBotts@BakerBotts.com
`BAKER BOTTS LLP
`
`
`
`
`
`
`
`
`
`
`CERTIFICATE OF SERVICE
`
`Jing H. Cherng
`Jing H. Cherng
`
`
`
`
`-5-
`
`0005
`
`
`
`Accused Product: AMD Famil 12h Fusion Processors
`
`
`
`Exhibit A.l: Preliminar Infrin ement Contention Claim Chart for US. Patent 6 239 614
`
`These preliminary infringement contentions were prepared without the benefit of the Court’s claim construction or the parties’ exchange of constructions.
`As of the date of these contentions, AMD has not produced any information concerning the Accused Products. Thus, this chart is based on publicly available
`evidence, and based upon information and reasonable belief in light of such evidence. As such, Aquila reserves the right to amend or supplement its
`contentions to address any issues arising from the Court’s constructions or to account for new information that becomes available.
`
`Ewen—tin
`
`A semiconductor
`
`integrated circuit device,
`
`s'oiréelAizb’s “LLANO” FUSION APU, Hot Chips 23, 19th August 2011, page 6.
`
`Graphics SIMD
`Array
`
`Display
`
`“0 Controllers
`
`0006
`
`
`
`
`Limitation
`Contention
`
`The Accused Products contain a plurality of first unit cells:
`
`a plurality of first unit
`cells each including a
`plurality of first MOS
`transistors, each of the
`first MOS transistors
`
`having a first threshold
`
`cells.
`
`As is typical of multi-VT standard cell design methodologies and structures, the Llano Accused Products use a mix
`of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt (LC-Hvt) standard
`
`,
`
`-
`
`‘
`
`Graphics sumo
`Array
`
`Dlsplay
`
`UO Controllers
`
`SafiiééLL‘Mb’S “LLANO” FUSION APU, Hot Chips 23, 19th August 2011, page 6.
`
`0007
`
`
`
`threshold voltage:
`
`The Accused Products contain a plurality of first MOS transistors, each of the first MOS transistors having a first
`
`0008
`
`
`
`
`
`
`
`JUTWANI (I All. AN nab-M (‘ORE IN ‘2 am ‘SOI ('MUS
`
`Contention
`
`Post Swapping
`
`- 32nm
`100%
`
`‘
`
`Pu Swapping
`
`“\‘MRV"
`
`The Accused Products contain a plurality of second unit cells:
`
`'
`
`75
`
`:00
`
`125
`
`no
`
`Timing Slack (p3)
`(b)
`
`I6FWI MEI”I
`
`Dynamic
`
`Static
`
`(a) Core device width hi~tngram by Vi type. ih) Using VI swaps in
`Fig. Ill
`wimp: ctiiicnl path liming opyxliunisiically.
`
`l V. «in Rdaiwc pom-r impmsrmcm
`ta) TDP [um-er dwnhulion at
`Fig ll.
`wilh tum-cl lo 45 nm gcnemiion cure (Minimal in: mrfunnnncci.
`
`0009
`
`
`
`Contention
`.
`I
`7L44_A44 ,_A
`
`Graphics SIMD
`Array
`
`Display
`
`”NO Controllers
`
`‘3‘
`
`Limitation
`
`transistors, each of the
`second MOS transistors
`
`having a second threshold
`
`voltage;
`
`
`
`
`fl5917 wok}.
`4.38hbqlflovfldnl1:1"«w r aNI
`~‘WWW~'
`
`0010
`
`
`
`
`
`ion
`
`Contention
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standard cells.
`
`
`
`DVFS Characteristics Modern computer chips are designtxl using multiple
`types of transistors, Le. a mixture of low—, medium-, and high—threshold transis-
`tors, to target different design tradeofl's, e.g. high-performance vs. low power.
`luw—thrmhold voltage (low-Vt) devices are usul in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`
`0011
`
`
`
`
`
`Limitation
`
`Contention
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`The Accused Products contain a plurality of second MOS transistors, each of the second MOS transistors having a
`second threshold voltage:
`
`CustomMactos - 35*
`smug - 28%
`'-‘7‘/~
`
`Clock
`
`0% 20% 40% ems 50%
`(a)
`
`I 45nm I 32nm
`
`100%
`
`100%
`
`N0. 1, JANUARY2011.
`
`w
`
`75
`
`too
`
`125
`
`150
`
`68%
`I
`
`84%
`
`I
`
`Timing Slack (ps)
`
`Static
`
`Dynamic
`
`0012
`
`
`
`
`
`Limitation
`
`Contention
`
`The Accused Products contain a unit cell array comprised of said first and second unit cells laid in array form:
`
`comprised of said first and
`second unit cells laid in
`
`array form;
`
`L404M
`
`Graphics SIMD
`Array
`
`Display
`
`IIO Controllers
`
`11.
`: .8
`1
`
`
`
`1:1“H"”
`
`0013
`
`
`
`
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standard cells.
`
`
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, Le. a mixture of low-, medium-, and high-threshold transis—
`tors, to target dilIerent design tradeolis, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in tiniiug-(n'itical paths,
`
`Lvl
`
`~.
`
`‘
`
`0014
`
`
`
`
`
`Limitation"
`
`Contention
`
`low leakage power but are slower, and are typically used in circuits that are
`off the timing—mitienl paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeolf between High-Vt and Low-Vt devicw. by having medium power re-
`quirements and medium delay. In general, low power chips are (lwignrxl using a
`larger percentage of High—Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`The Accused Products contain a power switch disposed around said unit cell array:
`LLANO CPU CORE RING GATING
`WITH PACKAGE LAYER ASSIST
`
`-..~.- .....
`
`a power switch disposed
`around said unit cell
`
`array and comprised of a
`plurality of third MOS
`transistors, each of the
`third MOS transistors
`
`having the second
`threshold voltage; and
`
`\finual voltage spreads uniformly
`Bumps near hot spots can exwed max limit:
`
`:24.
`rrrrrrr‘ rrrrr 1-1-4
`‘l i“““ififixar
`
`0015
`
`
`
`Kosonocky, page 50.
`
`'Contention
`
`The Accused Products contain a plurality of third MOS transistors:
`LLANO CPU CORE RING GATING
`
`WITH PACKAGE LAYER ASSIST
`
`Wtual voltage spreads uniformly
`Bumps near hol spots can exceed max limits
`
`
`
`High Rvsscan create nonse Issues E
`cuos‘JSSC m2011
`Source. PRACTICALPOWER GATING AND DYNAMC VOLTAGE/FREQUENCY SCALING by Stephen
`
`~
`
`IIII.III.I g
`
`.
`
`www.mmmswnw,
`MWNWFAMmem
`WWfAan-nznmsa
`
`m
`undue-J
`up
`
`.
`
`.
`
`0016
`
`
`
`
`
`Limitation
`
`Contention
`
`Vll. POWER GATING
`
`We defined a low~power mode called cone-level C6 (C(76) to
`allow core-level power gating [5] during periods of inactivity.
`The core is isolated front the supply during CC6 by a power-gate
`ring surrounding the CPU and L2 cache pair. allowing core level
`power down in a chip with multiple cores attached to a common
`power supply. The SCI process enables the gating of VSS (not
`vom. constructing th—Ogic
`devices without the need for extra processing steps to reduce
`on-state resistance [6]. Fig. l2(a) describes the core operations
`controlled by the power management system for C(‘6 entry and
`exit sequences.
`Fig. l2(b) details the connections of the power-gate ring with
`respect to the core and the C4 bumps. in addition to two I6X
`
`M It) and MI I on—die metal layers. a low-impedance package
`layer connected to the die by C4 bumps is dedicated for use as a
`vinual-grou nd layer. eliminating the need for any ultra-thick sil-
`icon metallization layer [6]. The low-impedance package layer
`
`
`
`Source: An x86-64 Core in 32 nm 501 CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1,
`JANUARY 2011, page 6.
`
`0017
`
`
`
`
`
`Contention
`
`LLANO CPU CORE RING GATTNG
`WITH PACKAGE LA YER ASSIST
`E
`
`coon-coo.
`
`on....£.uo‘
`
`o
`
`.-.i!III!S
`
`Vlnual voltage spteads unitotmly
`Bumps neax hot spots an exwed max limits
`
`The power gate ring of the Accused Products is turned off during standby and turned on when taken active.
`
`Ne: Sena-10v. Vlcbv F. macaw”,
`WW 'MMSOCO'IIIZIZMSCI
`MS'JSSC ”.20"
`
`Source: PRACTICAL POWER GATING AND DYNAMIC VOLTAGE/FREQUENCY SCALING by Stephen
`Kosonocky, page 50.
`
`0018
`
`
`
`
`
`Limitagion:
`
`.C‘ontention
`
`Two maior knobs have emerged for controlling power
`
`1. Dynamic Voltage and Frequency Scaling
`
`— Optimize performance for the application while it's
`running
`
`2. Power Gating
`
`- Gate power during idle griods
`
`
`
`Each present unique challenges for
`
`implementation and optimization
`
`1"." ..":rrL. .-
`
`.—‘ v.’ ..'..‘-4'-...n !--.n
`
`,1“
`
`'I...u._.
`
`n
`
`I
`
`Source: PRACTICAL POWER GATING AND DYNAMIC VOLTAGE/FREQUENCY SCALING by Stephen
`Kosonocky, page 8.
`
`0019
`
`
`
`Accused Products: AMD Family 15h Bulldozer/Piledriver APU Processom
`
`Exhibit A.2: Preliminary Infringement Contention Claim Chart for US. Patent 6,239,614
`
`These preliminary infringement contentions were prepared Without the benefit of the Court’s claim construction or the parties’ exchange of constructions.
`As of the date of these contentions, AMD has not produced any information concerning the Accused Products. Thus, this chart is based on publicly available
`evidence, and based upon information and reasonable belief in light of such evidence. As such, Aquila reserves the right to amend or supplement its
`contentions to address any issues arising from the Court’s constructions or to account for new information that becomes available.
`
`
`Limitation
`
`
`
`Contention
`
`‘ A semiconductor integrated circuit
`1 device, comprising:
`
`‘ To the extent the preamble is a limitation, the Accused Products are a semiconductor integrated device.
`
`
`
`0020
`
`
`
`Limitation
`
`Contention
`
`a plurality of first unit cells each
`including a plurality of first MOS
`transistors, each of the first MOS
`
`transistors having a first threshold
`
`The Accused Product discloses a
`
`lurali of first unit cells.
`
`THE DIE | Photo
`llu,lfllllll‘i‘
`
`-
`
`0021
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Floorplan (315 mmZ)
`
`I
`
`2MB L3 Cache
`
`‘
`
`
`
`
`‘
`:7, Hawker
`.1 Module v 7‘
`
`Source: Sean White, HIGH-PERFORMNCE POWER-EFFICIENTX86—64 SERVER AND DESKTOP PROCESSORS: Using the
`
`0022
`
`
`
`
`
`Limitation
`
`Contention
`
`The Bulldozer module contains 84 unique custom macros and
`3l7,000 scannable flops. Module-level VSS power gating (C6)
`is used to reduce leakage power by approximately 95% when
`both cores are idle [4]. The 32 nm 801 process provides three
`transistor VT types (low, regular, and high), with longer channel
`lengths used to achieve even finer-grained trade-offs between
`leakage and delay. V T’s used across the design consist mostly
`of regular (47%) and long-channel regular (46%), with less than
`1% low—VT used for the most critical paths.
`
`
`
`Source: McIntyre et 0]., Design Of Me Two-Core 3:86-64 AMD “Bulldozer” Module In 32 nm S01 CMOS, IEEE Journal of Solid-
`State Circuits, Vol. 47, No. 1, January 2012, page 165.
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standard cells.
`
`0023
`
`
`
`
`
`Limitation
`
`Contention
`
`DVFS Characteristics Modern computer chips are dosignul using multiple
`types of transistors, Le. a mixture of low-, medium-, and high-threshold transis-
`tors, to target difi'erent design tradeoli's, e.g. high-performance vs. low power.
`law-threshold voltage (Low-Vt) devices are used in timing—critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`
`low linkage power but are slower, and are typically used in circuits that are
`off the timing—critical paths. Medium—threshold voltage (Mid-Vt) device; offer
`a traded? between High-Vt and Low-Vt devices by having medium [xmer re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High—Vt devices and high— performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`
`
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`The Accused Products contain a plurality of first MOS transistors, each of the first MOS transistors having a first threshold
`voltage.
`
`0024
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Process Technology
`
`- 32mm Silicon-On-lnsulator (SOI) Hi-K Metal Gate
`(HKMO) process from GlobalFoundries
`
`- 11 metal-layer-stack
`
`- Low-k dielectric
`
`transistors.
`
`- Dual strain liners and eSiGe to improve
`performance.
`
`' Multiple V1 (HVT, WT. LVT) and long-channel
`
`0025
`
`
`
`
`
`“MAN! «I ul AN IM 64 “RE IN 32 um SUI (‘MOS
`
`- 455nm I 32nm
`100%
`100%
`
`bB'EI-n
`
`84‘.“
`
`
`
`‘0
`
`7‘
`
`.
`
`.
`
`Tmtng Slack (ps)
`(b)
`
`Static
`
`Dynamic
`
`(b)
`
`tap (.‘nn: deuce wutlh hmogrnm by VI type. thl [Mug VI \wnp In
`Fig. ltl
`mature cn‘lkal path Ilmtng twmmlisllwlly
`
`I V. (b) Rclum: pout-t Impnnclmnl
`ta) TDP [KNIT didn‘hutum LII
`Fig. ll.
`with mp“! to 45 nm generation con: annualized tut pertmmnnccn.
`
`0026
`
`
`
`Limitation
`
`Contention
`
`second MOS transistors having a
`
`THE DIE I Photograph
`\ nu...
`‘
`
`E
`um'
`um 3:222“-
`‘Il-IIII “I- I
`
`second threshold voltage;
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS: Using the
`core code named “Bulldozer ”, August 18, 2011, page 3.
`
`0027
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Floorplan (315 mm?)
`
`
`
`
`0028
`
`
`
`Limitation
`
`Contention
`
`THE DIEI Process Technology
`
`' 32-I'Irn Silicon-On-lnsulator (SOI) Hi-K Metal Gate
`(HKMG) process from GlobalFoundries
`
`' 11-rneIaI-layer-stack
`
`° Low-k dielectric
`
`transistors.
`
`‘ Dual strain liners and eSiGe to improve
`performance.
`
`- Multiple VT (HVT, RVT, LVT) and long-channel
`
`0029
`
`
`
`
`
`Limitation
`
`Contention
`
`The Bulldozer module contains 84 unique custom macros and
`317,000 scannable flops. Module-level VSS power gating (C6)
`is used to reduce leakage power by approximately 95% when
`both cores are idle [4]. The 32 nm 801 process provides three
`transistor VT types (low, regular, and high), with longer channel
`lengths used to achieve even finer-grained trade-offs between
`leakage and delay. V T’s used across the design consist mostly
`of regular (47%) and long-channel regular (46%), with less than
`1% low—VT used for the most critical paths.
`
`
`
`Source: McIntyre et al., Design Of The Two-Core 3:86-64 AMD “Bulldozer” Module In 32 nm S01 CMOS, IEEE Journal of Solid-
`State Circuits, Vol. 47, No. 1, January 2012, page 165.
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standard cells.
`
`0030
`
`
`
`
`
`Limitation
`
`Contention
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, Le. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeofl's, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in mining—critical paths,
`but have high leakage power. High—threshold voltage (High—Vt) devices have
`
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-crititml paths. Medium-threshold voltage (Mid—Vt) devices offer
`a tradeoll' between High-Vt and Low—Vt devices by having medium power re-
`quirements and medium: delay. In general, low power chips are designed using a
`larger percentage of High—Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high—performance device.
`
`a second threshold voltage:
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`The Accused Products contain a plurality of second MOS transistors, each of the second MOS transistors having
`
`0031
`
`
`
`
`
`
`
`The Accused Products contain a unit cell array comprised of said first and second unit cells laid in array form:
`
`Flg. H (a) TD? power distribution at l V. (bl Relative power Impmvemenl
`with mwcu in 45 nm generainn core lmrmalizcd for pcrfonnancei.
`
`'
`
`‘0
`
`7‘
`
`[00
`
`.
`
`_
`
`,
`
`Timing Slack (ps)
`(b)
`
`1a) Con: device width histogram by V! type. It» Usmg Vt maps to
`IO.
`Fig.
`reshape cnlical path limlng opportunistically.
`
`. 45m“
`100%
`
`'3' 0 “/c.
`
`Static
`
`Dynamic
`
`(b)
`
`ES (
`
`a)
`
`I
`
`RVt : LCRVt
`
`0032
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Photograph
`1
`[‘1‘ LI llu.'. JLIJ \l‘LLH ’- -
`
`m-
`
`Source: Sean White, HIGH-PERFORMANCE PO WER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS: Using the
`core code named “Bulldozer", August 18, 2011, page 3.
`
`0033
`
`
`
`
`
`
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, Le. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different dwign tradeofl's, e.g. high-performance vs. low power.
`low-thmahold voltage (Low-Vt) devices are usal in timing—critiml paths,
`but have high leakage power. High-threshold voltage (High-Vt) device; have
`
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critimil paths. Medium—threshold voltage (Mid-Vt) devices offer
`
`0034
`
`
`
`Limitation
`
`Contention
`
`a power switch disposed around
`said unit cell array and comprised
`of a plurality of third MOS
`transistors, each of the third MOS
`
`transistors having the second
`threshold voltage: and
`
`The Accused Products contain a power switch disposed around said unit cell array and comprised of a pluraility of third MOS
`transistors.
`
`TWWER MANAGEMENT| Core cs State (006)
`
`' Core C6:
`
`if a core isn’t active,
`
`remove power
`
`- Implemented in this physical
`design by a power gating ring
`that isolates the Core VSS for
`each Bulldozer module from the
`“Real" VSS
`
`- CC6 entry: when both Bulldozer
`cores in the module are idle,
`
`flush caches and dump register
`state to CC6 save space, then
`gate Core VSS
`
`interrupts, etc.)
`
`.
`
`*
`
`animus
`l'vlozlula
`
`'
`
`powemfllmgu-ls
`
`0035
`
`
`
`Limitation
`
`Contention
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS: Using the
`core code named “Bulldozer”, August 18, 2011, page 21.
`
`Each of the third MOS transistors of the Accused Products has the second threshold voltage:
`
`k?! fl
`
`i11133‘Qs.A‘S
`
`11
`
`_.-VIId1|--yl31' 21“1
`n‘.<-.l‘4‘
`
`—_-
`
`THE DIE | Process Technology
`
`' 32mm Silicon-On-lnsulator (SOI) Hi-K Metal Gate
`(HKMG) process from GlobalFoundries
`
`- 11mml-layer-stack
`
`' Low-k dielectric
`
`- Dual strain liners and eSiGe to improve
`performance.
`
`' Multiple VT (HVT, RVT, LVT) and long-channel
`transistors.
`
`
`
`‘7
`‘17
`mn—
`"Il
`l‘r?
`'
`'
`
`3
`
`Vii l4::g
`1!-“E
`
`0036
`
`
`
`
`
`Limitation
`
`Contention
`
`core code named “Bulldozer", August 18, 2011, page 6.
`
`Each of the third MOS transistors of the power gate ring has the second threshold voltage.
`
`Vll. POWER GATING
`
`
`
`We defined a low-power mode called core-level C6 (CCO) to
`
`allow core-level power gating [5] during periods of inactivity.
`
`The core is isolated from the supply during CC6 by a powersgatc
`ring surrounding the CPU and L2 cache pair. allowing core level
`power down in a chip with multiple cores attached to a common
`
`power supply. The 801 process enables the gating of VSS (not
`VDD). constructing th_logic
`devices without the need for extra processing steps to reduce
`on-state resistance [6]. Fig. IZta) describes the core operations
`
`controlled by the power management system for C0) entry and
`
`exit sequences.
`
`Fig. 12m» details the connections ol'the power-gate ring with
`respect to the core and the C4 bumps. In addition to two IOX
`Mill and Ml I on-die metal layers. a low-impedance package
`layer connected to the die by C4 humps is dedicated for use as a
`
`virtual-ground layer. eliminating the need for any ultra-thick sil-
`
`icon metallization layer [6]. The low-impedance package layer
`
`0037
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Floorplan (315 mm?)
`
`axflzmfi." -Mlm{0- -'
`w-*-_ ,
`
`.7
`core code named “Bulldozer”, August 18, 2011, page 5.
`H
`
`Bulldoier
`'7 Module jv
`
`,
`
`-,
`
`‘
`
`;, .i
`
`
`
`0038
`
`
`
`
`
`Limitation
`
`Contention
`
`device according to claim 1,
`wherein said power switch is turned
`off during standby and turned on
`
`
`
`The Bulldozer module contains 84 unique custom macros and
`3l7.000 scannable flops. Module-level VSS power gating (C6)
`is used to reduce leakage power by approximately 95% when
`both cores are idle [4]. The 32 nm SO] process provides three
`transistor VT types (low. regular. and high). with longer channel
`lengths used to achieve even finer-grained trade-offs between
`leakage and delay. V T’s used across the design consist mostly
`of regular (47%) and long-channel regular (46%). with less than
`
`1% low-VT used for the most critical paths.
`
`Source: McIntyre et al., Design Q’ The Two—Core x86—64 AMD “Bulldozer ” Module In 32 nm 301 CMOS, IEEE Journal of Solid-
`State Circuits, Vol. 47, No. 1, January 2012, page 165.
`
`
`
`0039
`
`
`
`Limitation
`
`Contention
`
`° Core C6:
`
`if a core isn’t active,
`
`remove power
`
`l
`1
`
`' Implemented in this physical
`design by a power gating ring
`that isolates the Core VSS for
`each Bulldozer module from the
`“Real" VSS
`
`,
`
`. Bulldozer
`’
`l‘vloglula
`
`interrupts, etc.)
`
`° 006 entry: when both Bulldozer
`
`‘ ‘-
`
`" '
`
`Power GaungFF [5
`
`cores in the module are idle,
`
`flush caches and dump register
`state to CC6 save space, then
`gate Core VSS
`
`- CC6 exit: ungate Core VSS,
`
`reload CC6 saved state, resume
`
`execution (ex: service
`
`0040
`
`
`
`Accused Product: AMD APUs containing Excavator cores (Representative Product: AMD Carrizo APU Processors)
`
`Exhibit A.3: Preliminary Infringement Contention Charts for US. Patent 6,239,614
`
`These preliminary infringement contentions were prepared without the benefit of the Court’s claim construction or the parties’ exchange of constructions.
`As of the date of these contentions, AMD has not produced any information concerning the Accused Products. Thus, this chart is based on publicly available
`evidence, and based upon information and reasonable belief in light of such evidence. As such, Aquila reserves the right to amend or supplement its
`contentions to address any issues arising from the Court’s constructions or to account for new information that becomes available.
`
`
`To the extent the preamble is a limitation, the Accused Products are semiconductor integrated circuits. circuit device, comprising:
`
`A semiconductor integrated
`
`Exhibit A.3
`
`0041
`
`-1—
`
`0041
`
`
`
`Limitation
`
`Contention
`
`AMD 6TH GENERATION
`
`A-SERIES PROCESSOR
`
`
`
`DDR/PHY
`
`Q}
`00
`13
`1:
`J:
`J:4.-
`I:
`(3«0
`
`Source: Krishnan, Energy Efficient Graphics and Multimedia in 28nm Carrizo APU | Hot Chips 27, p. 2.
`
`To the extent that the power gate ring implemented in this product operates similarly to the Bulldozer or Llano
`power gate rings, for example in terms of the threshold voltages of the MOS transistors in the various unit cells
`and the power switch, Aquila contends that the charts applicable to those products apply equally to this product,
`
`Exhibit A3
`
`0042
`
`0042
`
`
`
`a plurality of first unit cells
`each including a plurality of
`first MOS transistors, each of
`the first MOS transistors
`
`having a first threshold
`
`The Accused Products disclose a plurality of first unit cells:
`
`
`Limitation
`Contefiion
`
`.— and incorporates those charts by reference.
`
`voltage;
`
`Exhibit A3
`
`0043
`
`-3-
`
`0043
`
`
`
`
`
`Limitation
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standard cells.
`
`Lvt Lvt L“ W
`u' “ ~’
`filler
`
`7'
`
`Lvt Lvt L“ 339'}
`. U'
`A
`filler 9!
`
`DVFS Characteristics Modern computer chips are drsigned using multiple
`types of transistors, Le. a mixture of low-, medium-, and high-threshold transisp
`tors, to target diflereut design tradeoll's, c.g. high-performance vs. low power.
`IAN-threshold voltage (Low-Vt) devices are used in timing-critiml paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`
`low let-110180 powm but are slower. and are typically used in circuits that are
`off the timing-critiml paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoll between Higth and Low.Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High-Vt devices and high- performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. The host mm: is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`
`
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`Exhibit A.3
`
`0044
`
`0044
`
`
`
`Linlitation
`
`Contention
`
`The Accused Products disclose a plurality of first MOS transistors, each of the first. MOS transistors having a
`first threshold voltae, e. _., RVt:
`
`DYNAMIC UVD POWER GATING
`
`AMDCI
`
`
`
`.
`A Dynamic Inter frame powet gating controlled by
`mlcroconuoller furmware
`
`— Plovluw ldlv' detect-on enables m-adm/loolm
`powm gnxnng of the nnmo- 09
`
`Dynarmc power gahng along wuth low DOWE‘I
`hardemng of (he vndeo demder enables (I to
`negate the bigger vndeo detoder needed for
`H.265 offload
`
`'3X better man XV m net leakage prohlv"
`
`.01 ll 1) 1mm: uwm llu- wh ll!‘ l mp
`"kavm ' 1ND Mr.
`
`
`I I_y I ‘ H, '
`
`
`
`‘
`"
`I
`I'
`—.h——
`"u"
`"“'
`n
`
`
`
`,
`
`‘(anuo’wnua“m",“u .mw J'ur-‘J‘HI'SIl‘m‘n'flnll u... -.
`
`w
`
`.:.
`
`Source: ENERGY EFFICIENT GRAPHICS AND MULTIMEDIA IN 28NM CARRIZO APU, page 2] HOT CHIPS
`27 — AUGUST 2015
`
`Exhibit A3
`
`0045
`
`0045
`
`
`
`
`Limitation
`Contefiion
`
`a plurality of second unit cells
`each including a plurality of
`second MOS transistors, each
`of the second MOS transistors
`
`The Accused Products disclose a plurality of second unit cells:
`
`having a second threshold
`voltage;
`
`
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`
`Exhibit A3
`
`0046
`
`0046
`
`
`
`
`
`Limitation
`
`mm
`
`(LC-Hvt) standard cells.
`
`17—1‘
`
`i 777—” 7
`
`ass
`
`{1.1
`
`
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, Le. a mixture of low—, medium-, and high-threshold transis-
`tors, to target difl'erent design tradeolfs, e.g. high—performance vs. low power.
`low-thmshold voltage (Low-Vt) devices are used in timing—critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devicw have
`
`low leakage power but are slower. and are typically used in circuits that are
`off the timing—mitieal paths. Medium-threshold voltage (Mid—Vt) devices offer
`a tradeofl" between High—Vt and Low-Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are desigrwd using a
`larger percentage of High-Vt devices and high—performance chips with a larger
`percentage of Mid-Vt and Low-Vt devicm. The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-perfonnanoe device.
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`Exhibit A3
`
`0047
`
`0047
`
`
`
`Limitation
`
`Contention
`
`The Accused Products disclose a plurality of second unit cells each including a plurality of second MOS
`transistors having a second threshold voltage:
`
` DWNANHLUVDVOWTRGAHNG
`
`10
`
`a unit cell array comprised of
`said first and second unit cells
`
`laid in array form;
`
`Source: ENERGY EFFICIENT GRAPHICS AND MULTIMEDIA IN 28NM CARRIZO APU, HOT CHIPS 2 7 —
`AUGUST 2015, page 21.
`
`The Accused Products disclose a unit cell array comprised of said first and second unit cells laid in array form:
`
`Exhibit A?)
`
`0048
`
`0048
`
`
`
`
`Contention
`Limitation
`
`
`
`a power switch disposed
`around said unit cell array and
`comprised of a plurality of
`third MOS transistors, each of
`the third MOS transistors
`
`The Accused Products disclose a power gate ring disposed around said unit cell array:
`
`having the second threshold
`
`Exhibit A3
`
`0049
`
`0049
`
`
`
`
`
`Limitation
`
`Contention
`
`vol
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