Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 1 of 24
`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`No. 1:18-cv-554-LY
`
`
`
`
`
`§§§§§§§§§
`
`AQUILA INNOVATIONS, INC., a
`Delaware corporation,
`
`
`Plaintiff,
`
`v.
`
`ADVANCED MICRO DEVICES, INC., a
`Delaware corporation
`
`Defendant.
`
`AQUILA INNOVATIONS, INC.’S OPENING CLAIM CONSTRUCTION BRIEF
`
`
`
`
`
`AMD EX1011
`U.S. Patent No. 6,895,519
`
`

`

`
`I.
`
`II.
`
`
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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 2 of 24
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`TABLE OF CONTENTS
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`
`Page
`
`F.
`G.
`
`H.
`I.
`J.
`
`K.
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`U.S. PATENT 6,895,519 ................................................................................................... 1
`A.
`Overview ................................................................................................................ 1
`B.
`“system LSI” .......................................................................................................... 1
`C.
`plurality of standard clocks (claim 1) .................................................................... 2
`D.
`“generates a clock” (claim 1) ................................................................................. 3
`E.
`“[a first memory that stores] a clock control library for controlling a clock
`frequency transition between said ordinary operation modes” (claim 1) .............. 3
`“user selectable” (claim 1) ..................................................................................... 7
`“[a second memory that stores] an application program [wherein calling of
`said clock control library and changing of said register value are
`programmably controlled] to enable user selectable clock frequency
`transitions” (claim 1) .............................................................................................. 8
`“halted” (claim 1, 7) ............................................................................................... 9
`“principal constituents of said central processing unit” (claim 1) ....................... 10
`“a main library which is called by said application program and selects
`any one of said libraries” (claim 2) ...................................................................... 10
`“a status register that judges a state of said central processing unit
`immediately after being released from said third special mode” (claim 7) ......... 11
`U.S. PATENT 6,239,614 ................................................................................................. 12
`A.
`Overview .............................................................................................................. 12
`B.
`“unit cells” ........................................................................................................... 13
`C.
`“a unit cell array comprised of first and second unit cells laid in array
`form” / “unit cell array” ....................................................................................... 15
`“a power switch” .................................................................................................. 16
`“a power switch disposed around said unit cell array and comprised of a
`plurality of third MOS transistors” ...................................................................... 16
`“a plurality of input/output circuits disposed around said unit cell array” .......... 18
`“parts of said power switch disposed within said unit cell array” ....................... 19
`
`D.
`E.
`
`F.
`G.
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`-i-
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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 3 of 24
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`
`
`Federal Cases
`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Apple Inc. v. Motorola, Inc.,
`757 F.3d 1286 (Fed. Cir. 2014)..................................................................................................5
`
`Cias, Inc. v. All. Gaming Corp.,
`504 F.3d 1356 (Fed. Cir. 2007)................................................................................................19
`
`Epistar Corp. v. ITC,
`566 F.3d 1321 (Fed. Cir. 2009)................................................................................................14
`
`Hoganas AB v. Dresser Indus.,
`9 F.3d 948 (Fed. Cir. 1993) .......................................................................................................2
`
`Pacing Techs., LLC v. Garmin Int’l, Inc.,
`778 F.3d 1021 (Fed. Cir. 2015)................................................................................................14
`
`Personalized Media Communications, L.L.C. v. I.T.C.,
`161 F.3d 696 (Fed. Cir. 1998)....................................................................................................8
`
`St. Isidore Research, LLC v. Comerica Inc.,
`No. 2:15-cv-1390-JRG-RSP, 2016 U.S. Dist. LEXIS 126866 (E.D. Tex. Sep.
`18, 2016) ....................................................................................................................................3
`
`TEK Glob., S.R.L. v. Sealant Sys. Int’l,
`920 F.3d 777 (Fed. Cir. 2019)................................................................................................6, 9
`
`U.S. Surgical Corp. v. Ethicon, Inc.,
`103 F.3d 1554 (Fed. Cir. 1997)..................................................................................................1
`
`Federal Statutes
`
`35 U.S.C. § 112, para. 6 ......................................................................................................... passim
`
`Other Authorities
`
`Graf, R.F., Modern Dictionary of Electronics (7th ed. 1999) .......................................................15
`
`IBM Computer Dictionary ...............................................................................................................5
`
`Microsoft Computer Dictionary .......................................................................................................6
`
`Modern Dictionary of Electronics .............................................................................................6, 12
`
`Webster’s Third New International Dictionary 120 (2002) ...........................................................17
`
`-ii-
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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 4 of 24
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`Pursuant to the Court’s Scheduling Order, ECF No. 36, Plaintiff Aquila Innovations Ltd.
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`(“Aquila”) respectfully submits this opening claim construction brief in support of its proposed
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`constructions for the terms identified in the Joint Claim Construction and Prehearing Statement
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`for U.S. Patent 6,895,519 (“’519 patent”) and U.S. Patent 6,239,614 (“’614 patent”).
`
`I.
`
`U.S. PATENT 6,895,519
`
`A.
`
`Overview
`
`The ’519 patent is entitled “System LSI.” The ’519 patent addresses a System On a Chip
`
`(System LSI) that dynamically controls its clocks in order to achieve power reduction.
`
`B.
`
`“system LSI”
`
`Aquila Construction
`“system on a chip”
`
`AMD Construction
`“single integrated chip, which has a central
`processing unit, first memory, second
`memory, and I/O capability”
`
`
`The ’519 patent claims priority to a Japanese patent application filed in February 2002.
`
`“System LSI” is a Japanese term of art used to refer to a “system on a chip,” and would be
`
`understood by a person having ordinary skill in the art to carry that meaning. Oklobdzija Decl. ¶
`
`27. The remainder of the preamble recites that the system LSI has ordinary and special operation
`
`modes, and a central processing unit. These elements do not require construction.
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`The “system on a chip” recited in the preamble of claim 1 is a single integrated chip, but
`
`there is no need to mention that in a construction. Claim construction “is not an obligatory
`
`exercise in redundancy.” U.S. Surgical Corp. v. Ethicon, Inc., 103 F.3d 1554, 1568 (Fed. Cir.
`
`1997). There is also no need to mention “a central processing unit” because the preamble recites
`
`“a central processing unit.” The Court need not “repeat or restate every claim term.” Id. AMD’s
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`construction of “system LSI” includes a CPU (mentioned in the preamble), first memory (not
`
`mentioned in the preamble, but mentioned in the body of the claim), and second memory (also
`
`-1-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 5 of 24
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`
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`not mentioned in the preamble, but mentioned in the body of the claim). These elements are
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`explicitly identified in the preamble or the body of the claim as elements of the “system on a
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`chip,” and there is no need to mention them in a construction of the preamble.
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`“It is improper for a court to add ‘extraneous’ limitations to a claim, that is, limitations
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`added ‘wholly apart from any need to interpret what the patentee meant by particular words or
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`phrases in the claim.’” Hoganas AB v. Dresser Indus., 9 F.3d 948, 950 (Fed. Cir. 1993) (citing
`
`E.I. du Pont de Nemours & Co. v. Phillips Petroleum Co., 849 F.2d 1430, 1433 (Fed. Cir. 1988).
`
`AMD’s inclusion of “I/O capability” is both unnecessary and extraneous. Neither claim 1 nor the
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`specification requires that the system LSI have input or output capability. The purported I/O
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`capability does not play a role in any other limitation of claim 1 or any of the other claims, and
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`would simply be an extraneous limitation “wholly apart from any need to interpret what the
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`patentee meant” by the term “system LSI.”
`
`C.
`
`“plurality of standard clocks (claim 1)
`
`Aquila Construction
`“multiple clock signals”
`
`AMD Construction
`“multiple clock signals, each at a unique
`reference frequency”
`
`
`The parties agree on the use of “multiple clock signals,” but dispute whether each of the
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`multiple clock signals has a unique reference frequency. The “plurality of standard clocks” are
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`the clock signals received by the “clock generation circuit” mentioned in the third element of
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`claim 1. While the disclosed preferred embodiment has three oscillators, each of which generates
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`a clock signal having a different frequency, nothing in the specification requires that each of the
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`clock signals received by the “clock generation circuit” have a unique frequency. A person of
`
`skill in the art would understand that the “clock generation circuit” could also accept two clock
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`signals having the same frequency, but different phases, or the clock signals from two crystals
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`-2-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 6 of 24
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`
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`generating clock signals with the same frequency. Oklobdzija Decl. ¶ 29.
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`D.
`
`“generates a clock” (claim 1)
`
`Aquila Construction
`“outputs a clock signal”
`
`AMD Construction
`“creates a signal for controlling periodic
`circuit operation, such as by multiplying or
`dividing the frequency of another periodic
`signal, or by selecting the same”
`
`“Generates a clock” means “outputs a clock signal.” In claim 1, the clock generation
`
`circuit “generates a clock supplied to said central processing unit.” The specification uses the
`
`word “generate” to describe various types of outputs of clock signals, such as the clock outputs
`
`of the quartz oscillators, the PLL, and the clock generator. Dr. Albonesi admits that the plain and
`
`ordinary meaning of “generates” is “output.” See Albonesi Decl. ¶ 90.
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`AMD’s construction requires, instead of, or in addition to, “output,” the “creation” of a
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`signal. The ’519 patent does not limit generation to “creation,” or require both the “output” and
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`“creation” of a signal. Dr. Albonesi admits that a person of skill would not have understood
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`“generates” to mean “create.” Albonesi Decl. ¶ 90.
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`The “such as” clause in AMD’s proposed construction does not clarify the scope of the
`
`claims, and would mislead the jury into believing that “generation” is limited to “multiplying or
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`dividing the frequency of another periodic signal, or by selecting the same.” See St. Isidore
`
`Research, LLC v. Comerica Inc., No. 2:15-cv-1390-JRG-RSP, 2016 U.S. Dist. LEXIS 126866, at
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`*64 (E.D. Tex. Sep. 18, 2016) (rejecting construction with exemplary language).
`
`E.
`
`“[a first memory that stores] a clock control library for controlling a clock
`frequency transition between said ordinary operation modes” (claim 1)
`
`Aquila Construction
`AMD did not disclose this invalidity theory in
`its invalidity contentions or its proposed terms
`for construction
`
`
`AMD Construction
`subject to 35 U.S.C. § 112, para. 6.
`
`Function: controlling a clock frequency
`transition (that is not a state transition)
`between said ordinary operation modes
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`-3-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 7 of 24
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`
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`Not subject to 35 U.S.C. § 112, para. 6.
`“[a first memory that stores] software that
`controls the change in the frequency of the
`clock signals in the ordinary operation
`modes”
`
`
`
`Structure: indefinite
`
`
`According to claim 1, the “clock control library” is “software that controls the clock
`
`frequency transitions” between the ordinary operation modes. The first memory of the system
`
`LSI stores the clock control library. Claim 2 further provides that the clock control library
`
`comprises a plurality of libraries that control the clock generator and the system control circuit,
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`and a main library that selects any one of the plurality of libraries. The specification teaches that
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`the clock control library calls each of the plurality of libraries “according to parameters such as
`
`input parameters and jump parameters as shown in the table in Fig. 7. ’519 patent, col. 12, lines
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`12-15. The specification also teaches that each of the libraries is associated with a specific
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`memory address. Id., col. 12, lines 17-19. Each library has a corresponding set of parameters
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`with which it switches the clock and switches the clock mode. Id., col. 12, lines 24-30; Fig. 8.
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`AMD did not identify this limitation as one subject to the former 35 U.S.C. section112,
`
`paragraph 6 in its list of proposed terms for construction, or disclose a “means plus function”
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`indefiniteness theory in its invalidity contentions. Although the limitation does not use the word
`
`“means,” and is therefore presumed not to be subject to section 112, paragraph 6, AMD now
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`contends that “[a first memory that stores] a clock control library for controlling a clock
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`frequency transition between said ordinary operation modes” is a “means plus function” term,
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`and is indefinite because no structure for carrying out the alleged function of “controlling a clock
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`frequency transition (that is not a state transition) between said ordinary operation modes.” AMD
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`should not be permitted to inject this untimely contention into the case, but if it is, AMD’s
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`belated argument should be rejected.
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`-4-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 8 of 24
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`
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`A software limitation need not recite traditional physical structure to avoid the
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`application of section 112, paragraph 6. Apple Inc. v. Motorola, Inc., 757 F.3d 1286, 1298 (Fed.
`
`Cir. 2014). Indeed, “looking for traditional ‘physical structure’ in a computer software claim is
`
`fruitless because software does not contain physical structures.” Id. “[T]o one of skill in the art,
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`the ‘structure’ of computer software is understood through, for example, an outline of an
`
`algorithm, a flowchart, or a specific set of instructions or rules.” Id. at 1298-99 (citing Typhoon
`
`Touch Techs., Inc. v. Dell, Inc., 659 F.3d 1376, 1385 (Fed. Cir. 2011)).
`
`Figure 6 is a chart that “shows the structure of the clock control library according to the
`
`embodiment of the invention,” ’519 patent, col. 11, lines 63-65; Fig. 6, confirming that the
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`“clock control library” is structural in nature. Apple, 757 F.3d at 1298-99.
`
`A software limitation is not also subject to section 112, paragraph 6 where the claim
`
`language and specification disclose the software’s operation within the context of the invention,
`
`including the inputs, outputs, and how certain outputs are achieved. Id. at 1301. According to
`
`claim 1, the clock control library is stored in the first memory. The clock control library controls
`
`the system control circuit that carries out the clock frequency transitions. The clock control
`
`library itself is called by the application program. Claim 2 further elaborates on the structure of
`
`the clock control library – the clock control comprises a plurality of libraries that control the
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`system control circuit and clock generation circuit, and a main library that selects any one of the
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`plurality of libraries. The disclosure of the operation of the clock control library within the
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`system LSI described above confirms that “clock control library” is not subject to section 112,
`
`paragraph 6.
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`The term “library” also has a known meaning that refers to a class of software structure
`
`and is therefore not a substitute for the word “means.” The IBM Computer Dictionary defines
`
`-5-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 9 of 24
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`
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`“library” as “a collection of functions, calls, subroutines, or other data.” See JCCS, Attachment
`
`B, AQUILA00000000034, ECF 39. The Modern Dictionary of Electronics defines “library” as
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`“a collection of computer programs or subroutines for special purposes,” or “a group of standard,
`
`proven computer routines that can be incorporated into larger routines.” See JCCS, Attachment
`
`B, AQUILA00000000040, ECF 39-5. The Microsoft Computer Dictionary defines “library” as
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`“a collection of routines stored in a data file. Each set of instructions in a library has a name, and
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`each performs a different task.” JCCS, Attachment A, p. 203. As Dr. Oklobdzija opines, these
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`definitions confirm that the term “library” described a class of software structures to a person of
`
`ordinary skill at the time of the invention. Oklobdzija Decl. ¶ 34, 35.
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`Another problem for AMD’s new argument is that the prosecution history clearly
`
`demonstrates the applicant’s intent to avoid the application of section 112, paragraph 6. “The
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`subjective intent of the inventor when he used a particular term is of little or no probative weight
`
`in determining the scope of a claim, but that is not necessarily true when the intent is
`
`documented in the prosecution history.” TEK Glob., S.R.L. v. Sealant Sys. Int’l, 920 F.3d 777,
`
`786 (Fed. Cir. 2019). An inventor’s documented intent to avoid the application of section 112,
`
`paragraph 6 supports a construction of the term as not subject to section 112, paragraph 6. Id.
`
`The prosecution history of the ’519 patent confirms that the applicant sought to avoid means plus
`
`function treatment for his claims. As originally filed, the claims referred to “the first memory
`
`means storing a clock control library for controlling the clock state transition between said
`
`ordinary operation modes.” Ex. B, ’519 patent file history excerpt, Sept. 22, 2003 Amendment,
`
`at 8. The applicant amended the claims to omit the word “means,” resulting in the limitation now
`
`under dispute. The amendment omitting the word means documents an intent not to subject the
`
`claims to means plus function treatment, and supports the conclusion that this limitation is not
`
`-6-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 10 of 24
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`
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`properly construed as subject to means plus function treatment.
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`AMD’s related indefiniteness theory must be rejected because it is based upon a flawed
`
`construction. AMD’s proposed function of “controlling a clock frequency transition (that is not a
`
`state transition)” incorrectly attempts to distinguish between a “clock frequency transition” and a
`
`“clock state transition,” when the specification does not. The clock control library controls
`
`“clock state transitions” between the ordinary operation modes. ’519 patent, Abstract. Claim 1
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`states that the clock control library controls clock frequency transitions between ordinary
`
`operation modes. ’519 patent, col. 3, lines 39-42. Similarly, the specification discloses that “the
`
`system control circuit carries out the clock state transition between the ordinary operation mode
`
`and the special mode in response to the change of the value of the register, and also carrying out
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`the clock state transition among the ordinary operation modes in response to the clock control
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`library.” Id., col. 3, lines 43-48. Claim 1 mirrors this language, except using “clock frequency
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`transition” instead of “clock state transition.” There is no basis to exclude state transitions from
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`frequency transitions, as the ’519 patent does not distinguish between the two.
`
`F.
`
`“user selectable” (claim 1)
`
`Aquila Construction
`No construction required
`
`AMD Construction
`“chosen by a person”
`
`“User selectable” needs no construction. Both parts of the phrase have common
`
`meanings, and there is no evidence of a special meaning known to those of skill in the art.
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`“Selectable” means “capable of being selected,” not, “already selected,” or, as AMD
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`would have it, already “chosen by a person.” Claim 1 states that the calling of the clock control
`
`library and the changing of “said register value” are “programmably controlled by said
`
`application program to enable user selectable clock frequency transitions.” The point is to make
`
`it possible for clock frequency transitions to be selected by a user, not to enable something that
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`-7-
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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 11 of 24
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`
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`has already been chosen. AMD’s construction contradicts the plain meaning of “selectable.”
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`AMD describes the frequency transitions as already “chosen.”
`
`G.
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`“[a second memory that stores] an application program [wherein calling of
`said clock control library and changing of said register value are
`programmably controlled] to enable user selectable clock frequency
`transitions” (claim 1)
`
`Aquila Construction
`Not subject to 35 U.S.C. § 112, para. 6.
`
`“[a second memory that stores] an application
`program that enables user selectable clock
`frequency transitions by calling the clock
`control library and changing said register
`value”
`
`AMD Construction
`Subject to 35 U.S.C. § 112, para. 6.
`
`Function: enables user selectable clock
`frequency transitions
`
`Structure: software
`
`Algorithm: responsive to user selection,
`calling the clock control library and changing
`a register value that dictates a clock frequency
`transition
`
`No construction is necessary for this term. The term is directed at the second memory of
`
`the system LSI and the contents of the second memory – an application program that enables
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`user selectable clock frequency transitions, and that does so “by calling the clock control library
`
`and changing said register value.”
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`AMD’s means plus function argument should be rejected. Like the other terms for which
`
`AMD seeks means plus function treatment, this limitation does not use the word “means,” and is
`
`therefore presumed not to be subject to section 112, paragraph 6. The limitation is not a means
`
`plus function limitation because it recites the structure AMD asserts is necessary to perform the
`
`asserted claimed function. See Personalized Media Communications, L.L.C. v. I.T.C., 161 F.3d
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`696, 704 (Fed. Cir. 1998).
`
`AMD’s proposed function is “to enable user selectable clock frequency transitions,” and
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`the structure for performing the asserted function is “calling the clock control library and
`
`changing the register value.” However, these steps are explicitly recited in the disputed
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`-8-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 12 of 24
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`
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`limitation. It is unnecessary to look to the specification for guidance on structure because the
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`claim already recites what AMD calls structure. For the same reason, the term “application
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`program” is not a “black box” that encompasses any means of accomplishing AMD’s asserted
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`function. Oklobdzija Decl., ¶ 83.
`
`The prosecution history also confirms that the applicant intended to avoid section 112
`
`paragraph 6. The claims as originally filed claimed a “second memory means that stores a
`
`application program.” An amendment deleted the word “means,” showing an intent to avoid the
`
`application of section 112, paragraph 6. The “[second memory that stores] an application
`
`program” is also not subject to section 112, paragraph 6. See TEK Glob., 920 F.3d at 786.
`
`H.
`
`“halted” (claim 1, 7)
`
`Aquila Construction
`No construction required
`
`AMD Construction
`“completely cut off”
`
`“Halted” is a word that is readily understandable in plain English and needs no
`
`construction. The term “halted” appears in claims 1 and 7 in describing the status of the clock
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`and power supplies to CPU during each of the three special modes.
`
`AMD’s construction of “completely cut off” is unsupported by the intrinsic or extrinsic
`
`evidence. Dr. Albonesi admits that when the voltage or clock supply drop below operational
`
`levels, but are not completely cut off, they are “halted.” Albonesi Decl. ¶ 131. In the context of
`
`power, cutoff means “the minimum value … that just stops output current.” Id. This definition
`
`contemplates a non-zero value for the cutoff of voltage supply. Similarly, in the context of a
`
`signal such as a clock signal, Dr. Albonesi’s cited definition is “the point of degradation … at
`
`which a signal becomes unusable.” Id. Here also the definition does not specify that the signal is
`
`completely cutoff, but merely becomes unusable. Dr. Albonesi also admits in footnote 3 that
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`“halt” can mean “stop or pause.” AMD’s proposed construction is unsupported and incorrect.
`
`-9-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 13 of 24
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`
`
`I.
`
`“principal constituents of said central processing unit” (claim 1)
`
`Aquila Construction
`“the processor cores”
`
`AMD Construction
`“the processor cores but not circuitry
`responsible for responding to inputs, such as
`peripheral devices, or interrupts”
`
`This limitation is in claim 1 in connection with the first special mode in which the clock
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`supply to the principal constituents of the central processing unit is halted. The parties agree that
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`“principal constituents of the central processing units” includes the processor cores. AMD seeks
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`to exclude “circuitry responsible for responding to inputs, such as peripheral devices, or
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`interrupts” from the scope of the term. The specification’s disclosure of a peripheral bus and
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`associated components that are still under operation during the first special mode does not
`
`support adding “circuitry for responding to inputs” to the construction. AMD agrees with what
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`the principal constituents are, but seeks to add limitations regarding what they are not, which is
`
`unnecessary.
`
`J.
`
`“a main library which is called by said application program and selects any
`one of said libraries” (claim 2)
`
`AMD Construction
`
`indefinite
`
`
`Aquila Construction
`AMD’s invalidity contentions stated that this
`term is indefinite because “it is unclear which
`libraries are subject to selection.”
`
`The libraries that are subject to selection are
`the “plurality of libraries that control said
`system control circuit and said clock
`generation circuit to transition the clock
`frequencies supplied to said central
`processing unit.”
`
`No further construction necessary
`
`AMD asserted that this term is indefinite because “it is unclear which libraries are subject
`
`to selection.” See Exs. D, E, AMD Invalidity Contention Excerpts. Neither the original
`
`contentions, nor the amended contentions served without leave, disclosed any other theories.
`
`-10-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 14 of 24
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`Perhaps because there is no indefiniteness in this regard, Dr. Albonesi’s declaration advances
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`two new theories, each dependent on an undisclosed construction: (1) the “main library” is
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`subject to section 112, paragraph 6, and is indefinite for failure to disclosure structure, and (2)
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`the term “in correspondence with the clock frequency supplied to the CPU” is indefinite. AMD’s
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`undisclosed theories lack merit.
`
`“Main library” is not subject to section 112, paragraph 6. Claim 2 shows that the main
`
`library is a software structure that is part of the clock control library. It describes structure as
`
`“clock control library” does. See Fig. 6.
`
`The term “in correspondence with the clock frequency supplied to the CPU” is not
`
`indefinite. The specification of the ’519 patent describes the correspondence between the clock
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`frequency supplied to the CPU. The specification makes the analogy that the transitions carried
`
`out by the plurality of libraries selected by the main library are similar to gear changes in a car.
`
`’519 patent, col. 13, lines 55-60. Figures 7 and 8 depict the calling of the clock control library
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`and a table for explaining parameters possessed by the library, wherein (a) indicates input
`
`parameters to the library and (b) indicates the contents of the input parameters. There is no
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`support for the assertion that “in correspondence with the clock frequency supplied to the CPU”
`
`does not inform a person of ordinary skill of the scope of the claim with reasonable certainty.
`
`K.
`
`“a status register that judges a state of said central processing unit
`immediately after being released from said third special mode” (claim 7)
`
`Aquila Construction
`
`“a status register in which the information of
`the state of the CPU is stored”
`
`Indefinite
`
`AMD Construction
`
`The ’519 patent’s status registers store information regarding the status of the CPU or
`
`peripheral devices. ’519 patent, col. 8, lines 45-53. The specification discloses that the status
`
`register stores information that notifies the handshaking state after being released from the third
`
`-11-
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`

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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 15 of 24
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`
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`special mode. Id., col. 7, lines 45-53. A person of skill in the art would therefore understand the
`
`term “a status register that judges a state of said central processing unit immediately after being
`
`released from said third special mode” to mean “a status register in which the information of the
`
`state of the CPU is stored” immediately after being released from the third special mode.
`
`Oklobdzija Decl. ¶ 47. The term is not indefinite.
`
`Status registers were known structures at the time of the invention. Oklobdzija Decl., ¶
`
`47. The Modern Dictionary of Electronics defines “status register” as “a register used in a
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`computer to hold status information.” Similarly, “status word register” is defined as “a group of
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`binary numbers that informs the user of the present condition of the microprocessor.”
`
`Dr. Albonesi argues that the term is indefinite because the specification states that the
`
`status register “judges,” “controls,” and “notifies.” The specification does not state that the status
`
`register “controls” the transition to the third special mode. Instead, the status register makes it
`
`possible to control the transition to the third special mode. ’519 patent, col. 5, lines 36-39. As the
`
`specification teaches, judging and notifying can result in information about the state of the CPU
`
`being conveyed or stored. A person of skill in the art would understand that a status register
`
`judges a state by storing or conveying information related to the status of the device. Oklobdzija
`
`Decl. ¶ 47.
`
`II.
`
`U.S. PATENT 6,239,614
`
`A.
`
`Overview
`
`The ’614 Patent is directed generally to an improved semiconductor integrated circuit
`
`layout that utilizes MOS transistors of varying threshold-voltages, described in the ’614 Patent as
`
`a Multithreshold-Voltage CMOS or MTCMOS. See ’614 patent, col. 1, lines 26-27. The
`
`MTCMOS consumes less power than conventional semiconductor integrated circuits because it
`
`can operate at a lower voltage when active and leaks less power current when it is inactive.
`
`-12-
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`Case 1:18-cv-00554-LY Document 41 Filed 07/02/19 Page 16 of 24
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`
`
`B.
`
`“unit cells”
`
`Aquila Construction
`
`“logic elements of which a unit cell array is
`comprised”
`
`AMD Construction
`“semiconductor integrated circuits
`implemented by a gate array system, cannot
`be a conventional standard cell”
`
`Claim 1 claims a semiconductor integrated circuit device with five parts: transistors, unit
`
`cells, a unit cell array, a power switch, and input/output circuits. See generally id., col. 6, lines
`
`45-61. The device has two types of unit cells. The first type of unit cell has a plurality of MOS
`
`transistors, each having “a first threshold voltage.” The second type also has a plurality of MOS
`
`transistors, but these transistors have “a second threshold voltage.” These two types of unit cells
`
`are arranged to form a unit cell array. See id., col. 6, lines 53-54. The power switch and
`
`input/output circuits are arranged around the unit cell array. See id., col. 6, lines 55-