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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.,
`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.,
`Patent Owner
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`Case IPR2019-01526
`Patent 6,895,519
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`PETITIONER ADVANCED MICRO DEVICES, INC.’S REPLY TO
`PATENT OWNER’S RESPONSE
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`IPR2019-01526
`U.S. Patent No. 6,895,519
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`TABLE OF CONTENTS
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`
`INTRODUCTION ........................................................................................... 1
`I.
`CLAIM CONSTRUCTION ............................................................................ 1
`II.
`III. GROUND 1 – OBER IN VIEW OF NAKAZATO ........................................ 3
`A.
`The Ober-Nakazato combination discloses a “plurality of
`ordinary operation modes.” ................................................................... 3
`1.
`It would have been obvious to reduce Ober’s CPU clock
`frequency during “ordinary operations.” .................................... 6
`Ober’s CPU is capable of operating at reduced clock
`speeds. .......................................................................................10
`The Ober-Nakazato combination discloses “a first memory
`storing a clock control library for controlling clock frequency
`transitions between said ordinary operation modes.” .........................13
`A POSITA would have been motivated to combine Ober and
`Nakazato and would have had a reasonable expectation of
`success .................................................................................................14
`1. Modifying Ober’s register would not cause it to behave
`unpredictably. ............................................................................15
`Combining Ober with Nakazato would not cause Ober’s
`“power management state machine” to behave
`unpredictably. ............................................................................16
`Ober’s peripheral devices would not behave
`unpredictably in the combination of Ober and Nakazato .........17
`Ober does not “teach away” from Nakazato .............................18
`4.
`The Board properly instituted this IPR. ..............................................20
`D.
`IV. GROUND 2 – OBER IN VIEW OF NAKAZATO, COOPER AND
`WINDOWS ACPI .........................................................................................22
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`B.
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`C.
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`2.
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`2.
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`3.
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`A.
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`The combination of Ober, Nakazato, Cooper, and Windows
`ACPI renders obvious claims 2-6 .......................................................22
`Exhibit 1005 qualifies as a printed publication. ..................................23
`B.
`V. GROUND 3 – OBER IN VIEW OF NAKAZATO AND DOBLAR ...........25
`VI. THE DEPENDENT CLAIMS ARE UNPATENTABLE FOR THE
`REASONS SET FORTH IN THE PETITION. .............................................27
`VII. CONCLUSION ..............................................................................................27
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`PETITIONER’S UPDATED EXHIBIT LIST
`
`
`Description
`U.S. Patent No. 6,895,519 B2 to Endo (“the ’519 patent”)
`File history of U.S. Patent No. 6,895,519 B2 to Endo (“’519 file
`history”)
`Declaration of Dr. David Albonesi
`U.S. Patent No. 6,665,802 to Ober (“Ober”)
`“Draft ACPI Driver Interface Design Notes and Reference,”
`Microsoft Hardware White Paper, Microsoft Corporation, 1998
`(“Windows APCI”)
`U.S. Patent No. 6,516,422 to Doblar et al. (“Doblar”)
`U.S. Patent No. 6,823,516 to Cooper (“Cooper”)
`U.S. Patent No. 6,681,336 to Nakazato et al. (“Nakazato”)
`Curriculum vitae of Dr. David Albonesi
`McDaniel, G., IBM Dictionary of Computing, McGraw-Hill, 10th
`ed., (1993) (“IBM Dictionary”)
` “Aquila Innovations, Inc.’s Claim Construction Brief,” Aquila
`Innovations, Inc. v. Advanced Micro Devices, Inc., Case No. 1:18-
`cv-00554-LY (W.D. Tex.) (filed July 2, 2019). (“Claim
`Construction Brief”)
`“Aquila Innovations, Inc.’s Preliminary Infringement
`Contentions,” Aquila Innovations, Inc. v. Advanced Micro Devices,
`Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.) (filed Feb. 3, 2019).
`(“Preliminary Infringement Contentions”)
`Compaq Computer Corporation et al., “Advanced Configuration
`and Power Interface Specification, Revision 2.0” (July 27,2000)
`(“ACPIspec”)
`U.S. Patent No. 5,952,890 to Fallisgaard et al. (Fallisgaard)
`Intel Pentium III Processor/840 Developer Kit Manual (April
`2001) (“Intel Pentium III Manual”)
`TMS320C55x DSP Functional Overview (June 2000) (“TMS
`Overview”)
`ST7 8-Bit MCU Family User Guide (July 2002)(“ST7 User Guide)
`
`Exhibit
`No.
`1001
`1002
`1003
`1004
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`1005
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`1006
`1007
`1008
`1009
`1010
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`1011
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`1012
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`1013
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`1014
`1015
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`1016
`1017
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`IPR2019-01526
`U.S. Patent No. 6,895,519
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`Exhibit
`No.
`1018
`1019
`1020
`1021
`1022
`1023
`1024
`1025
`1026
`1027
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`1028
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`1029
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`1030
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`1031
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`1032
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`Description
`U.S. Patent No. 7,155,617 B2 to Gary et al. (“the ’617 patent”)
`Microsoft Computer Dictionary, Microsoft Press, 5th ed.,
`(2002)(“Microsoft Dictionary”)
`MICROSOFT.COM, OnNow and Power Management (“OnNow”)
`Affidavit of Christopher Butler
`Olukotun et al., The Case for a Single-Chip Multiprocessor (1996)
`Albonesi et al., Tradeoffs in the Design of Single Chip
`Multiprocessors (1994)
`Bossen et al, Power4 Systems: Design for Reliability (2001)
`U.S. Patent No. 5,260,979 to Parker et al. (“the ’979 patent)
`U.S. Patent No. 5,530,726 to Toshiaki Ohno (“the ’726 patent)
`Trevor Mudge, “Power: A First-Class Architectural Design
`Constraint,” IEEE Computer, April 2001
`Declaration of Dr. David Albonesi in Support of Petitioner’s Reply
`to Patent Owner’s Response
`Deposition Transcript of Dr. Steven A. Przybylski, August 14,
`2020.
`Internet Archive capture of http://www.microsoft.com, June 10,
`2001 (accessed August 27, 2020).
`Internet Archive capture of
`http://www.microsoft.com/windows/default.asp, June 9, 2001
`(accessed August 27, 2020).
`Internet Archive capture of http://www.microsoft.com/HWDev/,
`June 11, 2001 (accessed August 27, 2020).
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`IPR2019-01526
`U.S. Patent No. 6,895,519
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`I.
`
`INTRODUCTION
`The ’519 patent claims nothing more than a combination of concepts that
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`were well known long before the ’519 patent. This fact is undisputed. And
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`combining those concepts would have been obvious to a POSITA.
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`Patent Owner (“PO”) focuses its arguments primarily on two related
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`elements of the independent claim: 1) “a plurality of ordinary operation modes”;
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`and 2) “a first memory storing a clock control library for controlling clock
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`frequency transitions between said ordinary operation modes.” These elements,
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`however, are taught by the combination of Ober and Nakazato.
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`Rather than challenging this combination, PO focuses on Ober alone. And
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`PO’s criticisms are simply wrong or mischaracterizations of AMD’s actual
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`positions. The remainder of PO’s arguments fail for similar reasons. Accordingly,
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`the Board should reject PO’s arguments and find all claims of the ’519 patent
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`unpatentable.
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`II. CLAIM CONSTRUCTION
`PO does not challenge any of the constructions set forth in the Petition. PO
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`instead argues that (1) the preamble of claim 1 is limiting; and (2) that the term
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`“plurality of ordinary operation modes,” which is recited in the preamble, requires
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`“that the CPU execute instructions at different frequencies.” POR, 21, 25. But
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`U.S. Patent No. 6,895,519
`PO’s arguments need not be addressed, because they are not relevant to the
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`obviousness of claim 1 over the prior art at issue.
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`The dispute between the parties is whether the combination of Ober and
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`Nakazato discloses changing a CPU’s clock frequency, not whether the CPU
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`executes instructions after it has changed clock frequencies. PO’s constructions
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`attempt to inject a requirement that claim 1’s CPU must execute instructions at the
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`different clock frequencies. Although AMD does not believe that is a requirement
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`of the claims, it’s also irrelevant because it’s taught by the prior art.
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`AMD has consistently stated that the combination of Ober and Nakazato
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`discloses changing CPU clock frequencies during “normal” operations of a CPU.
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`Neither party disputes that CPUs execute instructions during “normal” operations.
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`But PO’s constructions appear to be premised on a mistaken belief that Ober’s
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`CPU core only operates at a single frequency. Thus, PO argues that Ober’s core is
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`incapable of executing instructions at different frequencies. POR, 27. But PO has
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`never disputed that Ober’s core actually executes instructions during “normal”
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`operations. PO has only disputed that Ober’s core operates at more than one
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`frequency.
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`Accordingly, the Board need not decide whether the preamble is limiting, or
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`whether “ordinary operation modes” requires executing instructions. Rather, the
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`Board need only decide that the combination of Ober and Nakazato discloses a
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`U.S. Patent No. 6,895,519
`CPU that operates at different frequencies. If the CPU of Ober and Nakazato ican
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`change clock frequencies, PO doesn’t dispute that it would execute instructions at
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`those frequencies.
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`III. GROUND 1 – OBER IN VIEW OF NAKAZATO
`A. The Ober-Nakazato combination discloses a “plurality of ordinary
`operation modes.”
`The Petition explains that the combination of Ober and Nakazato discloses
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`the claimed “plurality of ordinary operation modes.” And the Petition provides
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`several motivations for making this combination. PO’s rebuttal arguments
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`improperly focus solely on Ober—without addressing the combined teachings of
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`Ober and Nakazato that AMD actually relies on. See EX1028, ¶¶15-27.
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`In particular, the Petition explains that Ober discloses a variety of clocks that
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`are divided, including during “normal mode” (i.e. ordinary operation). Pet., 16-17.
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`As a result, the Petition explains, it would have been obvious to also divide Ober’s
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`CPU core clock during “normal mode” too. Id. The Petition acknowledges,
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`however, that “Ober does not explicitly describe how [this] occurs” Id. at 17. This
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`is where Nakazato fits in—“Nakazato discloses a ‘CPU speed control circuit 152’
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`that ‘controls the processing speed of the CPU 11’” Id. (citing EX1008, 5:44-49).
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`Nakazato further explains that these CPU frequency changes occur during user
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`operation (i.e., an ordinary operation mode): “the power-saving driver waits . . .
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`until user operation to a computer system is enabled, and then sets the processing
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`speed of the CPU. . .” EX1008, Abstract (emphasis added)
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`The Petition further explains that a POSITA would have been motivated to
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`combine Ober and Nakazato, because they each “explicitly relate to managing the
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`power of computing system.” Pet., 18 (citing EX1003, ¶ 91). Moreover, as Dr.
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`Albonesi explains, the CPU is one of the largest power consumers in any
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`computing system, especially for systems on a chip, such as those described in
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`Ober. EX1028, ¶17. And Ober and both experts agree, it was well known that
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`reducing a CPU’s clock frequency was one method of reducing its power
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`consumption. EX1004, 2:17-20, EX1028, ¶17; EX1029, 54:19-55:2, 62:18-63:5.
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`This would have further motivated a POSITA to reduce the CPU’s speed during a
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`computer’s “normal mode” of operation to achieve even greater power savings.
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`Focusing on Ober alone, PO argues that doesn’t disclose the claimed
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`“ordinary operation modes.” See POR, 28-29 (arguing that (1) Ober’s clock
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`division doesn’t apply to Ober’s CPU core and (2) Ober cannot divide the CPU
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`clock during “sleep mode” or “normal mode”). By attacking Ober alone, PO is
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`focusing on the wrong analysis. AMD relies on the combination of Ober and
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`Nakazato. Thus, PO needs to address the combination as a whole, not just the
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`teachings of Ober. PO ignores Nakazato’s explicit teachings regarding reducing
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`CPU clock frequency during “ordinary operations.” As explained above, Nakazato
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`describes a “CPU speed control circuit 152,” which can vary the CPU speed by
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`simply changing the value in a register. EX1008, 6:19-21. And this occurs during
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`the “ordinary operation mode” of a computer by way of a computer utility, shown
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`in Figure 2 from Nakazato below:
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`EX1008, FIG. 2.
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`The Petition cited repeatedly to these teachings, yet PO simply ignores that fact.
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`See Pet., 28-30. Accordingly, the Board should reject PO’s arguments, because
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`they improperly focus on Ober alone, instead of what the Petition sets forth—the
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`combination of Ober and Nakazato. In addition, as explained further below, the
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`Board should also reject PO’s arguments, because they mischaracterize the
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`teachings of Ober and the positions set forth in the Petition.
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`It would have been obvious to reduce Ober’s CPU clock
`frequency during “ordinary operations.”
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`1.
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`As explained above, the Petition relies on the combination of Ober and
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`Nakazato to show a CPU that operates at different clock frequencies. But PO
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`improperly focuses its criticisms on Ober alone rather than the combination of
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`Ober and Nakazato. Specifically, PO argues that the divided clock programmed by
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`SFR register 116 is only available to Ober’s “subsystems 30-40” during “normal
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`mode,” not Ober’s core 22. Thus, according to PO, it would not have been obvious
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`to modify the frequency of the clock of Ober’s core 22. POR, 29. But PO ignores
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`the teachings of Nakazato related to CPU clock adjustment, and more importantly,
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`PO focuses on the wrong teaching of Ober. Id; See EX1028, ¶¶20-23.
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`The Petition focuses on a different teaching of Ober related to a different
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`register—register 62. Pet, 27. Ober explains that “register 62” includes a field
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`“SLPCLK,” that is used to program “the frequency of the system clock during a
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`sleep mode of operation.” Id. (citing EX1004, 11:31-33). Both experts agree that a
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`POSITA would have understood that the CPU core clock is necessarily adjusted
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`when the system clock is adjusted. EX1028, ¶20; EX1029, 90:9-16 (“If you divide
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`the system clock during run mode that would affect the frequency of the core and
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`the execution of instructions.”) This is because, as shown below, in Ober’s
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`(annotated) Figure 1, there is only one system clock that is the input clock for
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`every subsystem and peripheral of Ober, including the CPU core 22:
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`IPR2019-01526
`U.S. Patent No. 6,895,519
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`EX1008, FIG. 1.
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`Accordingly, dividing the system clock necessarily divides the input clock
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`for all of Ober subsystems, which in the case of core 22 would result in a divided
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`CPU clock frequency. EX1028, ¶21. This is precisely why the Petition explains
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`that it is register 62 that would be modified using the teachings of Nakazato to
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`adjust the CPU core clock: “there are at least six available bits in SFR register 62,
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`which would be sufficient for configuring the clock division during normal
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`operation mode.” Pet., 27-28. And the Board acknowledged this already in its
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`institution decision: “Petitioner points to an example in Ober that describes
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`dividing the system clock by 2, 4, or 128, and explains that the system can supply a
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`divided clock signal during ‘normal operating mode.’” ID, 18.
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`Therefore, although Ober describes that “a divided clock” may be provided
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`to “subsystem[s]” during “normal mode,” it’s irrelevant to Petitioner’s analysis
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`whether those “subsystems” are described as including Ober’s CPU core or not.
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`The Petition merely cites this portion of Ober, because if a divided clock can be
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`supplied to “subsystems” it suggests to POSITAs that such a divided clock can also
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`be supplied to Ober’s CPU core. Pet., 27. And AMD’s citations to register 62 and
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`Ober’s system clock merely explain one manner in which such a divided clock can
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`be supplied to Ober’s CPU. EX1028, ¶22.
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`But even assuming that dividing clocks is somehow limited to Ober’s
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`“subsystems 30-40,” PO’s theory is still incorrect, because it overlooks what the
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`Petition explains is Ober’s CPU. As shown below in annotated Figure 1 from the
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`Petition, AMD explains that Ober’s CPU includes not only core 22, but also FPIs
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`42-52:
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`U.S. Patent No. 6,895,519
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`Petition, 22-23. Importantly, PO doesn’t challenge AMD’s identification of Ober’s
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`CPU. And according to Ober, “each of the subsystems 30-40 include a FPI
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`peripheral interface 42-52” EX1004, 7:36-41 (emphasis added). Thus, even
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`assuming PO’s arguments that dividing the clock during “normal mode” is limited
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`to “subsystems 30-40,” since FPIs 42-52 are part of those subsystems, their clocks
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`are also divided during “normal mode.” And thus, by acknowledging that at least
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`“subsystems 30-40” can have their clocks adjusted during “normal mode,” PO is
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`effectively conceding that Ober’s CPU, as identified by AMD, is also having its
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`clock divided during “normal mode,” because FPIs 42-52 are part of the CPU
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`identified by AMD. When these adjustments occur, this would result in the FPIs,
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`which are part of the CPU, operating at a lower clock frequency at a time when the
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`core 22 is carrying out instructions (e.g., normal mode). EX1028, ¶23.
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`2. Ober’s CPU is capable of operating at reduced clock speeds.
`The Petition explains that the combination of Ober and Nakazato provides a
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`system that operates at different clock speeds during “ordinary operation mode.”
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`PO, however, once again improperly focuses on Ober alone instead of the
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`combination. Specifically, PO argues that Ober’s CPU is incapable of executing
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`instructions at different clock speeds during its “RUN mode,” which PO equates to
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`an “ordinary operation mode.” POR, 35. For this assertion, PO relies on a
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`disclosure from Ober that states that during its “RUN” state, a variable named
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`“Low Speed Clocks,” which PO contends is a reduced system clock speed, may be
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`set to “False.” Id. But the Board should reject PO’s argument because Ober never
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`suggests that “Low Speed Clocks” is equivalent to a reduced system clock.
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`Moreover, PO doesn’t account for the combination of Ober and Nakazato. And
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`even assuming “Low Speed Clocks” was somehow related to a reduced system
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`clock, the passage only bolsters the fact that Ober’s CPU can operate at different
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`clock speeds. See EX1028, 24-27.
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`First, as explained above, the Petition sets forth an obvious modification of
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`Ober that results in its CPU executing instructions at different frequencies as
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`taught in Nakazato. And there is no dispute that Nakazato teaches executing
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`instructions at different CPU frequencies. Thus, the Board should reject PO’s
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`arguments, because they do not address Nakazato’s teachings and the proposed
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`combination by AMD. See EX1028, ¶24.
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`Second, PO incorrectly assumes that if one adjusted Ober’s system clock
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`during RUN mode, “Low Speed Clocks” would change. Yet, nothing in Ober links
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`“Low Speed Clocks” to changes in the system clock, nor does PO cite any support
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`for its assumption. Moreover, AMD proposes modifying Ober’s register to support
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`the adjustment of CPU clock changes. So even if, as PO contends, the “Low Speed
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`Clocks” variable is changed based on some register value described in Ober,
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`nothing in the Petition, nor Ober, suggests that this would happen in the combined
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`system of Ober and Nakazato. That is, the Petition proposes using unused bits of a
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`register to effectuate the clock change. Nothing in Ober suggests the same “Low
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`Speed Clock” variable would be changed in response to these different bits, nor
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`does the Petition ever propose this. Thus, the Board should reject PO’s argument
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`for this reason too. See EX1028, ¶ 26.
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`Finally, even assuming “Low Speed Clock” did control the system clock
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`(which Ober doesn’t describe), PO’s arguments incorrectly focus on what Ober
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`explicitly discloses as opposed to what Ober suggests to a POSITA. In fact, the
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`passage cited by PO only further supports AMD’s position. Specifically, according
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`to PO the “Low Speed Clocks” variable controls the speed of the system clock.
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`U.S. Patent No. 6,895,519
`POR, 35. Based on this, PO then argues that although the “Low Speed Clock”
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`variable can control the speed of the CPU, it does not because Ober allegedly
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`“requires that the CPU’s clock be stopped while the system clock is low speed.” Id.
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`But PO’s support for this statement is simply that Ober never describes the CPU
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`operating while “Low Speed Clocks” is true . Id. Yet, even if Ober doesn’t
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`describe such a situation, PO overlooks that Ober describes “Low Speed Clocks”
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`as a “variable.” See EX1028, ¶25.
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`Dr. Albonesi explains that a POSITA would understand that variables are
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`intended to be changed. EX1028, ¶27. Thus, assuming PO’s interpretation is
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`correct, in describing “Low Speed Clock” as a variable, Ober also suggests to a
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`POSITA that system clock speed can be changed, including during “RUN” mode.
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`EX1028, ¶27. PO ignores this important detail. And both experts agree that if the
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`system clock is changed during “RUN” state, it would cause Ober’s CPU core 22
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`to execute instructions at a different clock frequency. EX1029, 90:9-16 (“If you
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`divide the system clock during run mode that would affect the frequency of the
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`core and the execution of instructions.”). Therefore, not only is PO’s analysis
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`improperly focused on attacking Ober alone instead of the combination of Ober
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`and Nakazato, but PO’s arguments fail to acknowledge that even under its own
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`interpretation of Ober, the passages it cites suggest to a POSITA that Ober’s CPU
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`is capable of executing instructions at different clock speeds.
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`B.
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`The Ober-Nakazato combination discloses “a first memory storing
`a clock control library for controlling clock frequency transitions
`between said ordinary operation modes.”
`For this element, PO rehashes the same arguments it made for “the plurality
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`of ordinary operation modes.” And PO’s arguments here fail for the same
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`reasons—PO simply ignores the teachings of Nakazato. In particular, PO argues
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`that Ober “does not suggest that the SFR 62 may be modified so that more than
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`one frequency is supplied to the CPU in RUN mode.” POR, 37. But PO again
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`ignores the combination with Nakazato. See EX1028, ¶¶28-36.
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`The Petition explicitly describes that “Ober does not explicitly describe how
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`[the clock is divided] during ‘normal mode.’” Pet., 17. And thus, a “POSITA
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`looking to implement the teachings of Ober would need to understand the
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`circumstances under which CPU speed would be reduced, while a computer is
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`normally operating, and how such a system would control the CPU speed.” Id.
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`(emphasis added). This is where Nakazato fits in, because “Nakazato discloses a
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`‘CPU speed control circuit 152’ that ‘controls the processing speed of the CPU 11,
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`and has a throttling controller for switching the CPU speed.’” Id.(citing EX1008,
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`5:44-49).
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`Accordingly, PO’s argument that Ober “does not suggest” such
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`modifications is not the relevant inquiry. Ober need not suggest such
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`modifications. See KSR, Int’l v. Teleflex. rejecting the teaching, suggestion, and
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`U.S. Patent No. 6,895,519
`motivation test) AMD need only show that it would have been obvious to a
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`POSITA, which as explained above, the Petition demonstrates in detail.
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`C. A POSITA would have been motivated to combine Ober and
`Nakazato and would have had a reasonable expectation of success
`The Petition explains that Ober discloses that the clocks to each of its
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`subsystems can be divided during “normal mode” by writing to a register. Pet., 16-
`
`17. As a result, and as the Petition explains, this would suggest to a POSITA to
`
`also divide Ober’s CPU core clock during normal mode by writing to a register
`
`too. Id. And as discussed above, this would have caused a POSITA to look to a
`
`reference, such as a Nakazato, which explicitly describes dividing a CPU clock by
`
`writing to a register. A POSITA would have been motivated to perform such a
`
`modification to further reduce Ober’s power consumption, because the CPU core is
`
`one of the largest power consumers in any computing system. EX1028, ¶17; Pet.,
`
`31. But the Petition goes one step further, explaining how a POSITA could
`
`combine the references by performing a simple modification to Ober’s registers to
`
`support such CPU frequency changes:
`
`[A] POSITA would have recognized that register 62 could
`be used to configure reduced CPU clock speed during
`normal mode by allowing software to write a value
`representing the amount of clock division into a field in
`register 62.
`
`Pet, 28.
`
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`U.S. Patent No. 6,895,519
`Despite these detailed explanations in the Petition, PO disputes that a
`
`POSITA would have been motivated to combine Ober and Nakazato or have had a
`
`reasonable expectation of success of doing so. Specifically, PO argues that (1)
`
`modifying register 62 would cause “unpredictable behavior;” (2) Ober’s power
`
`state machine “might” behave unpredictably; (3) dividing Ober’s system clock
`
`would cause Ober’s peripheral devices to behave “unpredictably;” and (4) Ober
`
`teaches away from Nakazato because Ober is “decentralized” and Nakazato is
`
`“centralized.” But the Board should reject all of these arguments, because they
`
`mischaracterize the positions in the Petition and ignore the ordinary creativity of a
`
`POSITA. See EX1028, ¶¶37-52.
`
`1. Modifying Ober’s register would not cause it to behave
`unpredictably.
`
`The Petition explains that one method to implement Ober’s CPU speed
`
`change is utilize additional unused bits in “register 62” for modifying the system
`
`clock. Pet., 27. PO, however, argues that modifying register 62 would cause
`
`unpredictable behavior. Specifically, “[r]eading or writing to undefined or unused
`
`bits in a register typically would be ignored or result in the chip behaving
`
`unpredictably.” POR., 44. The Board should reject this argument, because it
`
`ignores the explanation in the Petition and also makes no sense.
`
` The Petition never suggests writing to undefined bits. Rather, the Petition
`
`describes defining new bits in register 62 for use in dividing the CPU clock: “there
`
`
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`- 15 -
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`are at least six available bits in the SFR register 62, which would be sufficient for
`
`configuring the clock division during normal operation mode.” Pet, 27-28. A
`
`POSITA would have then made the appropriate changes to Ober to support these
`
`additional bits. PO simply ignores this. Instead, PO pretends as though a POSITA,
`
`after deciding to use the additional bits of register 62, would do so without making
`
`any other modifications to Ober to use those bits. That simply makes no sense. “A
`
`person of ordinary skill is also a person of ordinary creativity, not an automaton.”
`
`KSR, 550 U.S. at 421. Therefore, the Board should reject this argument.
`
`2.
`
`Combining Ober with Nakazato would not cause Ober’s
`“power management
`state machine”
`to
`behave
`unpredictably.
`
`As explained above, the Petition explains that one method to achieve Ober’s
`
`reduced CPU clock speed is by adjusting the system clock as defined in register 62.
`
`Pet, 27. PO equates adjusting the “system clock” to modifying the state variable
`
`“Low Speed Clocks.” POR, 47. PO then concludes “Ober’s microcontroller might
`
`behave unpredictably, and may even be locked unacceptably” when state variables,
`
`such as “Low Speed Clocks” are changed. POR, 47-48 (emphasis added). This,
`
`according to PO, means there is no reasonable expectation of success in combining
`
`Ober and Nakazato. Id. But the Board should reject PO’s argument, because it
`
`mischaracterizes the Petition and Ober and because the argument doesn’t even pass
`
`muster on its face.
`
`
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`- 16 -
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`IPR2019-01526
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`As an initial matter, the Petition never proposes modifying any state
`
`variables, even though state variables are meant to be changed. EX1028, ¶51.
`
`Changing a state variable would not cause the system to behave unpredictably,
`
`because they are meant to be changed. Id. But PO doesn’t even assert that Ober’s
`
`state machine would behave unpredictably. PO only states that it might or may
`
`behave unpredictably. That something might or may not work is not sufficient
`
`reasoning to rebut a reasonable expectation of success. PO’s assertions of
`
`hypothetical problems are vague and unsupported by any technical explanation of
`
`what specific problems PO believes might occur. But most importantly, PO
`
`ddoesn’t even allege that these hypothetical problems would be beyond the
`
`ordinary skill of a POSITA to solve. Accordingly, the Board should reject this
`
`argument too.
`
`3. Ober’s peripheral devices would not behave unpredictably in
`the combination of Ober and Nakazato
`
`The Petition explains that one method to achieve Ober’s reduced CPU clock
`
`speed is by adjusting Ober’s system clock. Pet., 27. PO argues that a POSITA
`
`would not have combined Ober and Nakazato, because adjusting the “system
`
`clock” “would change Ober’s principle of operation and modify Ober to supply
`
`low-speed clocks indiscriminately across the chip.” PO then contends this would
`
`allegedly “cause some of the peripherals…to fail,” because they are unexpectedly
`
`receiving lower speed clocks. POR, 52. But the Board should reject this argument,
`
`
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`because it ignores the ordinary creativity of a POSITA and more importantly, Ober
`
`already explicitly teaches how to do this.
`
`First, PO’s argument is incorrect because it assumes that a POSITA would
`
`combine Ober and Nakazato with reckless disregard to the operations of Ober’s
`
`peripherals. But this ignores the skill and ordinary creativity of a POSITA. “A
`
`person of ordinary skill is also a person of ordinary creativity, not an automaton.”
`
`KSR, 550 U.S. at 421. A POSITA would have understood how to combine Ober
`
`and Nakazato and to avoid any of the “peripheral” problems PO complains of.
`
`EX1028, ¶¶44-45.
`
`Second, and more importantly, PO also ignores that Ober already discloses
`
`that its subsystems (i.e. peripherals) are capable of operating at lower speed clocks:
`
`“a divide clock (DIVCLK) bit… may provide a divided clock signal to the
`
`subsystem during a normal mode.” EX1004 9:65-10:2. So contrary to PO’s
`
`assertion, Ober’s “peripherals” would not fail, because they are already capable of
`
`operating at lower clock frequencies. EX1028, ¶45. Thus, the Board should reject
`
`this argument too.
`
`4. Ober does not “teach away” from Nakazato
`The Petition explains that a POSITA would have been motivated to modify
`
`Ober with Nakazato’s CPU speed-changing functionality. Pet., 16-17. PO argues
`
`that a POSITA would not have combined Ober and Nakazato, because Ober
`
`
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`IPR2019-01526
`U.S. Patent No. 6,895,519
`allegedly disparages “centralized power management approach[es]” like Nakazato.
`
`POR, 54-55. But the Board should reject this argument, because PO is fixated on
`
`the words “decentralized” and “centralized” rather than the actual explanations in
`
`Ober and the Petition.
`
`As an initial matter, although Ober discusses both “centralized” and
`
`“decentralized” power management approaches, Ober is not strictly a decentralized
`
`power management scheme. Indeed, PO’s own expert confirmed this. EX1029,
`
`71:22-72:2 (“No it’s not solely decentralized.”). So PO’s argument fails at least
`
`because Ober itself is not decentralized.
`
`But more importantly, PO’s argument fails because nothing in the Petition
`
`proposes modifying any core functionality of Ober. Ober is decentralized in the
`
`sense that it’s “power management system” allows for the “microcontroller
`
`subsystems to be independently controlled.” EX1004, 2:45-48. This functionality
`
`would remain in the proposed combination with Ober and Nakazato. EX1028, ¶39.
`
`As noted above, the modi
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