Trials@uspto.gov
`571-272-7822
`
`Paper 13
`Date: March 13, 2020
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`
`v.
`
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`
`IPR2019-01526
`Patent 6,895,519 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
`
`POTHIER, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`571-272-7822
`
`Paper 13
`Date: March 13, 2020
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`
`v.
`
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`
`IPR2019-01526
`Patent 6,895,519 B2
`
`
`
`
`
`
`
`
`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
`
`POTHIER, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`IPR 2019-01526
`Patent 6,895,519 B2
`
`
`I.
`
`INTRODUCTION
`
`Advanced Micro Devices, Inc. (“Petitioner”)1 requests an inter partes
`
`review of all claims (claims 1–11) in U.S. Patent No. 6,895,519 B2 (Ex.
`
`1001, “the ’519 patent”). Paper 2 (“Petition” or “Pet.”), 16. Aquila
`
`Innovations Inc. (“Patent Owner”) filed a Preliminary Response. Paper 10
`
`(“Prelim. Resp.”). With authorization, Petitioner filed a Reply (Paper 11,
`
`“Reply”), and Patent Owner filed a Sur-Reply (Paper 12, “Sur-Reply”).
`
`Under 35 U.S.C. § 314, an inter partes review may not be instituted
`
`“unless . . . there is a reasonable likelihood that the petitioner would prevail
`
`with respect to at least 1 of the claims challenged in the petition.” Upon
`
`consideration of the Petition, Preliminary Response, Reply, and Sur-Reply,
`
`we determine that Petitioner has shown that there is a reasonable likelihood
`
`that it would prevail in showing the unpatentability of claims 1–11 of the
`
`’519 patent. We institute an inter partes review of all challenged claims of
`
`the ’519 patent.
`
`A. Related Proceedings
`
`The parties indicate the ’519 patent is at issue in a pending lawsuit,
`
`Aquila Innovations Inc. v. Advanced Micro Devices, Case No. 1:18-cv-
`
`00554-LY (W.D. Tex. filed July 2, 2018). Pet. 74; Paper 6, 2.
`
`B. The ’519 Patent
`
`The ’519 patent was filed on September 23, 2002, and claims priority
`
`to a Japanese application filed on February 25, 2002. Ex. 1001, codes (22)
`
`and (30). The ’519 patent relates to a system large scale integration (LSI).
`
`Id. at 1:7–10. As background, the ’519 describes a prior art microcontroller
`
`
`1 Petitioner identifies itself and ATI Technologies ULC as the real parties-in-
`interest. Pet. 4.
`
`2
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`IPR 2019-01526
`Patent 6,895,519 B2
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`power management that includes four clock operation modes: high-speed
`
`operation mode (operating at ½ of the oscillation frequency), low-speed
`
`operation mode (operating at 1/4, 1/8, 1/16, and 1/32 of the oscillation
`
`frequency respectively), wait mode, and halt mode. Id. at 1:63–2:6, 2:61–
`
`67, Fig. 10.
`
`The ’519 patent describes an “improved system LSI” that overcomes
`
`various problems in the prior art system LSIs. Id. at 3:24; id. at 3:21–34.
`
`The ’519 patent discloses “[a] system LSI dynamically and speedily controls
`
`clocks of various frequencies as used in a wide range of operation modes
`
`from high-speed to low-speed operation modes, enabling user selection of a
`
`system of power consumption type most suitable.” Id. at code (57); see also
`
`id. at 3:23–34.
`
`Figure 2 of the ’519 patent below shows an LSI:
`
`Figure 2 shows a system LSI using a CPU.
`
`
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`3
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`Patent 6,895,519 B2
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`Id., 5:60–61, Fig. 2. As shown above, LSI 550 includes CPU 510, ROM
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`551 for storing a clock control library and an application program, system
`
`control circuit 534, and clock generation circuit 558. Id. at 6:50–57, 7:9–12,
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`7:60–67, Figs. 2–4. According to the ’519 patent, the LSI’s system control
`
`circuit 534 and clock generation circuit 558 reduce consumed power without
`
`losing the core CPU’s versatility. Id. at 11:50–54, Figs. 1–5.
`
`The ’519 patent’s clock control library (e.g., 32 in Figure 6) manages
`
`power using an application program (e.g., 31 in Figure 6). Id. at 11:61–65,
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`Fig. 6. A main library (e.g., 33 in Figure 6) selects one of the libraries (e.g.,
`
`34 in Figure 6) corresponding with the application program’s state and
`
`permits transitions between clock operating modes. Id. at 12:2–5, 12:27–30,
`
`Figs. 6, 8(a). Below, Figure 5 illustrates an example of clock operation
`
`mode (i.e., eight operation modes STNn (n:integer of 0 through 7)) and the
`
`state transitions.
`
`Figure 5 shows clock operation modes and state transitions.
`
`
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`4
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`Id. at 5:66–67, 9:4–8, Fig. 5. Figure 5’s arrows show transitions among
`
`various states (modes). Id. at 11:18–22, Fig. 5.
`
`A “clock gear” concept permits transitions between the ordinary
`
`operation modes (e.g., STN0–STN4). Id. at 9:4–6, 11:33–39, Fig. 5. For
`
`example, the ’519 patent describes the state transition number becomes (5)
`
`in Figure 5, when switching the current clock mode from the low-speed
`
`operation mode (STN3) to the high-speed operation mode. Id. at 13:9–19,
`
`Fig. 5. Figure 5 further shows five “ordinary operation modes” (e.g., STN0–
`
`4) and three “special modes” (e.g., STN5–STN7). Id. at 9:46–47, Fig. 5.
`
`Figure 5’s ordinary operation modes include: (1) an initial operation mode
`
`(STN0, 25 MHz), (2) a highest-speed operation mode (STN1, 62.5 MHz),
`
`(3) a high-speed operation mode (STN2, 50 MHz), (4) a low-speed operation
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`mode (STN3, 31.25 MHz), and (5) a lowest-speed operation mode (STN4,
`
`32.768 MHz). Id. at 9:12–17, 9:38–41, 9:49–10:17, Fig. 5.
`
`C. Illustrative Claim
`
`Petitioner challenges all the claims of the ’519 patent. Of the
`
`contested claims, claim 1 is the only independent claim. Claims 2 through
`
`11 ultimately depend from claim 1. Independent claim 1, reproduced below,
`
`illustrates the claimed subject matter.
`
`1. A system LSI having a plurality of ordinary operation
`modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit, comprising:
`
`a first memory that stores a clock control library for
`controlling a clock frequency transition between said ordinary
`operation modes;
`
`a system control circuit which has a register, wherein
`said system control circuit carries out the clock frequency
`transition between said ordinary operation modes and said
`special modes in response to a change of a value in said
`
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`register, and also carries out the clock frequency transition
`among said ordinary operation modes in response to said clock
`control library;
`
`a clock generation circuit that receives a plurality of
`standard clocks, wherein said clock generation circuit generates
`a clock supplied to said central processing unit according to
`control by said system control circuit; and
`
`a second memory that stores an application program,
`wherein calling of said clock control library and changing of
`said register value are programmably controlled by said
`application program to enable user selectable clock frequency
`transitions,
`
`wherein said special modes comprise a first special mode
`in which clock supply to principal constituents of said central
`processing unit is halted, a second special mode in which clock
`supply to an entirety of said central processing unit is halted,
`and a third special mode in which supply of power to the
`entirety of said central processing unit is halted.
`
`Ex. 1001, 14:15–47.
`
`D. The Asserted Ground of Unpatentability
`
`Petitioner asserts that claims 1–11 would have been unpatentable
`
`under 35 U.S.C. § 103(a)2 based on the following grounds:
`
`Claims Challenged
`1, 7, 10, 11
`2–6
`
`35 U.S.C. §
`103(a)
`103(a)
`
`References
`Ober,3 Nakazato4
`Ober, Nakazato, Cooper,5
`
`
`2 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. Changes to § 103 apply to
`applications filed on or after March 16, 2013. Because the ’519 patent has
`an effective filing date before March 16, 2013, we refer to the pre-AIA
`version of § 103.
`3 US 6,665,802 B1, issued Dec. 16, 2003 and filed Feb. 29, 2000 (Ex. 1004).
`4 US 6,681,336 B1, issued Jan. 20, 2004 and filed June 16, 2000 (Ex. 1008).
`5 US 6,823,516 B1, issued Nov. 23, 2004 and filed Aug. 10, 1999 (Ex.
`1007).
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`6
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`Patent 6,895,519 B2
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`Claims Challenged
`
`35 U.S.C. §
`
`8, 9
`
`Pet. 3–4.
`
`103(a)
`
`References
`Windows ACPI6
`Ober, Nakazato, Doblar7
`
`E. Testimony
`
`Petitioner supports its challenges with a declaration of David H.
`
`Albonesi, Ph.D., Ex. 1003 (“Albonesi Declaration”), and a declaration of
`
`Christopher Butler, Ex. 1020 (“Butler Declaration”).
`
`II. DISCUSSION
`
`A. Principles of Law
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`
`differences between the claimed subject matter and the prior art are such that
`
`the subject matter, as a whole, would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of ordinary skill in the art; and (4) when in evidence, objective
`
`evidence of nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18
`
`(1966).
`
`“In an [inter partes review], the petitioner has the burden from the
`
`onset to show with particularity why the patent it challenges is
`
`
`6 Microsoft Corporation (1998), Microsoft Hardware White Paper, Draft
`ACPI Driver Interface Design Notes and Reference (Version 0.91).
`Redmond, WA (Ex. 1005).
`7 US 6,516,422 B1, issued Feb. 4, 2003 and filed May 27, 1999 (Ex. 1006).
`
`7
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`Patent 6,895,519 B2
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`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`
`petitions to identify “with particularity . . . the evidence that supports the
`
`grounds for the challenge to each claim”)). This burden of persuasion never
`
`shifts to Patent Owner. See Dynamic Drinkware, LLC v. Nat’l Graphics,
`
`Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (discussing the burden of proof in
`
`inter partes review).
`
`B. Level of Ordinary Skill in the Art
`
`Petitioner asserts
`
`[a] person of ordinary skill in the art . . . would have a B.S.
`degree in Electrical Engineering, Computer Engineering, or an
`equivalent field as well as at least 3 to 5 years of academic or
`industry experience in computer systems architecture or
`computer chip design, or comparable industry experience.
`
`Pet. 16. Patent Owner does not set forth an ordinary artisan’s skill level or
`
`dispute Petitioner’s proposed understanding. See generally Prelim. Resp.
`
`At this stage, we accept Petitioner’s explanation and assessment of the
`
`ordinary skill level as they are consistent with the ’519 patent and the
`
`asserted prior art. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir.
`
`2001) (prior art itself may reflect an appropriate level of skill).
`
`C. Claim Construction
`
`In this inter partes review, claims are construed using the same claim
`
`construction standard that would be used to construe the claims in a civil
`
`action under 35 U.S.C. § 282(b). See 37 C.F.R. § 42.100(b) (2019). The
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`claim construction standard includes construing claims in accordance with
`
`the ordinary and customary meaning of such claims as understood by one of
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`ordinary skill in the art and the prosecution history pertaining to the patent.
`
`See id.; Phillips v. AWH Corp., 415 F.3d 1303, 1312–14 (Fed. Cir. 2005).
`
`Petitioner proposes that we construe the term “system LSI” in the
`
`preamble of claim 1 to mean “a ‘single integrated chip, which has a CPU
`
`memory, and I/O capability.’” Pet. 14. Petitioner states that the ’519
`
`patent’s disclosure confirms the system LSI includes memory, a CPU, and
`
`I/O capabilities. Id. (citing Ex. 1001, 5:58–61, 12:34–37, Fig. 2). Relying
`
`on Dr. Albonesi’s testimony, Petitioner further states an ordinarily skilled
`
`artisan would have had the same understanding. Id. (citing Ex. 1003 ¶ 77).
`
`In response, Patent Owner asserts that we do not have to construe the
`
`term “system LSI” at this juncture (Prelim. Resp. 4), but urges us to construe
`
`the preamble as limiting (id. at 5–6). Patent Owner asserts Petitioner has not
`
`stated whether the preamble is limiting, but contends the preamble is
`
`limiting because (1) without the term “system LSI” in the preamble, “it is
`
`not clear that the structural limitations mentioned in claim 1 reside on a
`
`chip”; and (2) the preamble provides antecedent basis for the recited
`
`“ordinary operation modes,” “special modes,” and “central processing unit”
`
`in the claim 1’s body. Id. at 5–6 (citing Bicon, Inc. v. Straumann Co., 441
`
`F.3d 945, 952 (Fed. Cir. 2006)).
`
`For purposes of this Decision, we need not expressly construe “system
`
`LSI” beyond determining that this term limits the scope of the claims as
`
`requiring the elements of the claims reside on a chip. See, e.g., NTP, Inc. v.
`
`Research In Motion, Ltd., 418 F.3d 1282, 1305–06 (Fed. Cir. 2005) (noting
`
`that the preamble is limiting if it recites essential structure that is important
`
`to the invention or necessary to give meaning to the claim). Petitioner’s
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`offering a construction for this term without stating that the preamble is not
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`limiting implies Petitioner’s agreement with this position. We note that
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`Petitioner later implies the preamble may not be limiting. Pet. 25 (stating
`
`“to the extent the preamble is determined as limiting”). This statement,
`
`however, appears to be addressing the various recited “modes” in the claim’s
`
`preamble (id. at 24–25) and not the recited “system LSI” (id. at 19–23).
`
`We also agree with Patent Owner that the recitations “ordinary
`
`operation modes,” “special modes,” and “a central processing unit” in claim
`
`1’s preamble provide antecedent basis for recitations in claim 1’s body
`
`(Prelim. Resp. 6), such as “a clock frequency transition between said
`
`ordinary operation modes” (Ex. 1001, 14:21–22), “the clock frequency
`
`transition between said ordinary operation modes and said special modes”
`
`(id. at 14:24–26), and “a clock supplied to said central processing unit” (id.
`
`at 14:32–33). These limitations make claim 1’s preamble limiting because
`
`they are necessary to give meaning to claim 1’s body.
`
`At this stage, we determine that the term “system LSI” in the
`
`preamble includes a chip and that claim 1’s preamble is limiting. Although
`
`the proper construction of this term may be material to whether Petitioner
`
`ultimately succeeds in demonstrating unpatentability according to its
`
`grounds, our institution decision does not depend on construing the term
`
`“system LSI” further.
`
`Petitioner also provides constructions for “a clock control library for
`
`controlling a clock frequency transition between said ordinary operation
`
`modes” and “principal constituents of said central processing unit” in claim
`
`1. Pet. 14–15. Patent Owner states “it is not necessary to construe” these
`
`terms. Prelim. Resp. 4. For purposes of this Decision, we determine that we
`
`need not provide an express construction for these terms in the ’519 patent.
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`10
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`That is, “only those terms need be construed that are in controversy, and
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`only to the extent necessary to resolve the controversy.” Vivid Techs., Inc. v.
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`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999); see also Nidec
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`Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017
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`(Fed. Cir. 2017) (citing Vivid Techs. in the context of an inter partes
`
`review).
`
`D. Obviousness of Claims 1, 7, 10, and 11 Over Ober and Nakazato
`(Ground 1)
`
`1. Ober (Ex. 1004)
`
`Ober is a United States patent issued on December 16, 2003, and filed
`
`on February 29, 2000. Ex. 1004, codes (22), (45). According to Petitioner,
`
`Ober is prior art under 35 U.S.C. § 102(e). Pet. 12. Patent Owner does not
`
`dispute its prior-art status.
`
`Ober describes a power management system for a microcontroller or
`
`System on Chip (SoC) having different subsystems. Ex. 1004, code (57),
`
`3:45–47. Ober’s Figure 1 below shows a power management architecture
`
`for a microcontroller or SoC.
`
`
`
`Figure 1 showing a power management architecture for a SoC
`
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`11
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`Id. at 3:22–26, Fig. 1. Above, Figure 1 shows a microcontroller that
`
`includes CPU core 22, flexible peripheral interconnect (FPI) bus 24, power
`
`management subsystem 26, major subsystems 30–40, FPI peripheral
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`interface 42–52, and memory banks 54 and 56. Id. at 5:28–53, Fig. 1. CPU
`
`core 22 is coupled to a system bus (e.g., 24) “to enable the operating system
`
`or application program to read and write the [special function register
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`(“SFR”)] in the power management state machines as well as the SFRs in
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`each of the FPI peripheral interfaces for each of the subsystems.” Id. at
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`5:31–37, Fig. 1.
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`Ober’s power management subsystem 26, illustrated in Figure 2,
`
`includes a machine for controlling a central processing unit’s (CPU) power
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`mode. Id. at code (57), 3:28–30, 5:38–40, 17:1–5, Figs. 2, 6. Ober states the
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`power management subsystem may provide “four power modes or states:
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`RUN; IDLE; SLEEP; and DEEP SLEEP.” Id. at 4:16–19; id. at 7:65–67,
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`15:14–16:67, Fig. 6. Table 8 shows the system’s configuration during RUN,
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`IDLE, and SLEEP modes (id. at 12:41–13:42), and Table 9 summarizes the
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`power modes, including RUN, IDLE, SLEEP (distributed clock) and (no
`
`distributed clock), and DEEP SLEEP (id. at 13:45–15:10).
`
`Power management subsystem 26 includes power manager 28 with a
`
`power management state machine, programmable special function register
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`(SFR) 62, and clock subsystem 64 for generating a system clock signal. Id.
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`at 5:58–64, Fig. 2. Ober’s SFR register 62 allows the power management
`
`system to be configured for specific applications and is illustrated in Figure
`
`5. Id. at 10:10–13, Figs. 2, 5. The bits’ definitions for SFR register 62 are
`
`shown in Table 5 and include SlpClk (Sleep clock), which may be divided
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`by 2, 4, or 128 “during Sleep.” Id. at 10:13–11:12, Fig. 5. Each subsystem
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`12
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`30–40 also has a separate SFR, which allows the operating system (OS) to
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`control the subsystems during different power modes. Id. at 9:20–25, 9:49–
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`51, Fig. 1. The bits’ definition for registers 116 are shown in Table 4. Id. at
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`9:27–47, Fig. 4. “A sleep divide clock (SDCLK) bit and a divided clock
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`(DIVCLK) bit either disables or provides divided clock signal to the
`
`subsystem during a SLEEP mode and also may provide a divided clock
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`signal to the subsystem during a normal mode.” Id. at 9:65–10:2.
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`Ober’s clock subsystem 64 may be configured by SFR register 62. Id.
`
`at 9:4–7. Clock subsystem 64 generates system and management clock
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`signals. Id. at 8:52–55, Fig. 3. Main crystal 84 connects to system oscillator
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`104 to generate an oscillation frequency (e.g., 150 MHz). Id. at 8:58–61,
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`Fig. 3. Phase lock loop (PLL) 106 locks in the oscillation frequency, while
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`clock circuit 108 divides the oscillation frequency to provide the system
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`clock frequency (e.g., 75 MHz). Id. at 8:61–64, Fig. 3. The system clock
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`signal may be generated by main oscillator 84/PLL or shut down. Id. at 9:6–
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`8. Management clock 110 can be derived from three sources, including real
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`time clock (RTC) oscillator 114 connected to the 32 kHz crystal 86, system
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`clock oscillator 104, or system clock signal. Id. at 8:66–9:3.
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`2. Nakazato (Ex. 1008)
`
`Nakazato is a United States patent issued on January 20, 2004, and
`
`filed on June 16, 2000. Ex. 1004, codes (22), (45). According to Petitioner,
`
`Nakazato is prior art under 35 U.S.C. § 102(e). Pet. 12. Patent Owner does
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`not dispute its prior-art status.
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`Nakazato discloses a computer system shown below.
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`Nakazato’s Figure 1 showing a computer system.
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`
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`Ex. 1008, 3:5–7, Fig. 1. The above computer system includes CPU 11, main
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`memory 13, drive circuit 22, and CPU speed control circuit 152. The OS
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`and various programs are loaded in main memory 13. Id. at 4:11–20, Fig. 1.
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`
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`CPU speed control circuit 152 controls the CPU’s processing speed.
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`Id. at 5:44–52, Fig. 1. CPU’s processing speed can be controlled at different
`
`levels using a CPU throttling function and a GEYSERVILLE function. Id.
`
`at 4:20–24. For switching CPU speed, the throttling controller uses the CPU
`
`throttling function, and the frequency/voltage controller uses the
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`GEYSERVILLE function. Id. at 5:45–6:18. With either function, the CPU
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`speed can be switched by writing necessary data in the internal register of
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`CPU speed control circuit 152. Id. at 6:19–21.
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`
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`A power-saving driver/program, running on the OS, executes CPU
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`speed control circuit 152 and its variable setting of the CPU’s processing
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`speed. Id. at 7:2–6. The power-saving driver controls CPU speed control
`
`circuit 152 through BIOS or directly without BIOS. Id. at 7:13–15.
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`
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`The user designates the CPU speed level using the power-saving
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`driver. Id. at 4:25–26, 7:16–19. A dedicated program, such as a program-
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`saving utility, presents the user with a window, such as Figure 2 below.
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`Nakazato’s Figure 2 showing a CPU speed setting window.
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`Id. at 3:8–9, 7:19–24, Fig. 2. The selected CPU processing speed is
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`recorded in a predetermined area (e.g., a registry area) of HDD 161, and the
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`power-saving driver can refer to this area. Id. at 7:24–27, 9:34–39.
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`
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`Nakazato describes examples of the CPU processing speed changing.
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`For example, Nakazato states: (1) the CPU processing speed changes from
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`the highest speed to a low-speed when the user designates a low speed,
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`(2) the CPU processing speed is maintained as the highest speed when the
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`user designates a highest speed, and (3) the processing speed changes
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`depending on the presence/absence of the AC adapter when the user sets a
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`low speed for battery operation and a high speed for an operation by an
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`external AC power supply. Id. at 7:64–8:4.
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`3. Discussion
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`Petitioner contends claims 1, 7, 10, and 11 are unpatentable under
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`35 U.S.C. § 103(a) as obvious over the combination of Ober and Nakazato.
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`Pet. 16–51.
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`(a) Claim 1
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`(i) Preamble
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`15
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`IPR 2019-01526
`Patent 6,895,519 B2
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`Claim 1 recites “[a] system LSI having a plurality of ordinary
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`operation modes and a plurality of special modes in response to clock
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`frequencies supplied to a central processing unit.” Ex. 1001, 14:15–17.
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`Petitioner contends that Ober teaches or suggests this limitation. Pet. 19–25.
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`For the recitation “system LSI,” Petitioner states that Ober discloses a
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`“system LSI” as a microcontroller or System on Chip (SoC) that can be used
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`with different subsystems, including input/output ports 30 and memory
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`banks 54 and 56. Id. at 19–20 (citing Ex. 1003 ¶ 93; Ex. 1004, 3:45–51,
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`5:41–53) (reproducing Ex. 1004, Fig. 1). Petitioner states Ober’s SoC
`
`includes a “central processing unit” as the term is described in the ’519
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`patent, which includes a CPU that has a core CPU attached to external
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`devices. Id. at 20–21 (citing Ex. 1001, 6:17–49) (reproducing Ex. 1001, Fig.
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`1). Petitioner specifically identifies Ober’s CPU in annotated Figure 1 that
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`follows:
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`Annotated Ober’s Figure 1 identifying Ober’s CPU with a red outline
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`Id. at 22 (reproducing Ex. 1004, Fig.1 (annotated)). Petitioner contends
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`Ober’s CPU “has nearly identical components to” the ’519 patent’s CPU.
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`16
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`Patent 6,895,519 B2
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`Id. at 22; id. at 21–23 (citing Ex. 1001, 6:17–36, 6:44–46; Ex. 1003 ¶¶ 98–
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`99; Ex. 1004, 5:28–31, 5:38–57) (reproducing Ex. 1004, Fig. 1).
`
`Concerning the recitation in the preamble that the system LSI has “a
`
`plurality of ordinary operation modes and a plurality of special modes in
`
`response to clock frequencies supplied to a central processing unit,”
`
`Petitioner contends Ober teaches these features. Id. at 24–25. Petitioner
`
`asserts that Ober includes a power management subsystem that can be
`
`configured into various power modes that correspond to the recited
`
`“ordinary operation modes” and “special modes.” Id. Regarding the
`
`“plurality of ordinary operation modes,” Petitioner states claim 1 has two
`
`requirements: (1) the “‘clock frequency transition[s]’ occur between said
`
`ordinary operation modes,” and (2) “such clocks are ‘supplied to a central
`
`processing unit.’” Id. at 24 (italics omitted) (citing Ex. 1001, 14:20–22; Ex.
`
`1003 ¶ 102). Dr. Albonesi testifies “[t]o state it another way, the claimed
`
`ordinary operation modes operate at different frequencies.” Ex. 1003 ¶ 102.
`
`Petitioner contends Ober discloses these requirements. Pet. 24.
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`Specifically, Ober discloses a microcontroller architecture that
`
`includes a power management system with a configurable power
`
`management state machine to control the CPU’s power modes as well as
`
`various subsystems. Ex. 1004, 3:52–56. Petitioner contends Ober’s power
`
`management subsystem has one configurable state referred to as a “‘Divided
`
`Clock’ signal,” and this signal “enables Ober’s ‘clock subsystem’ to provide
`
`divided (i.e. lower frequency) clock signals to Ober’s CPU instead of the
`
`normal clock signals.” Pet. 24 (citing Ex. 1003 ¶ 102; Ex. 1004, 9:65–10:2);
`
`see id. at 7 (citing Ex. 1004, 9:65–10:2; Ex. 1003 ¶ 65). Petitioner further
`
`asserts that this “divided clock” concept in Ober causes Ober’s CPU to
`
`17
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`Patent 6,895,519 B2
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`execute various frequencies related to the division in the divided clock
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`signal. Id. at 24 (citing Ex. 1003 ¶ 103; Ex. 1004, 8:58–64, 15:60–63).
`
`Petitioner points to an example in Ober that describes dividing the system
`
`clock by 2, 4, or 128, and explains that the system can supply a divided
`
`clock signal during “normal operating mode.” Id. at 24–25 (citing Ex. 1004,
`
`9:65–10:2, 11:8–13).
`
`Patent Owner argues that Ober does not disclose the recited “plurality
`
`of ordinary operation modes” recited in claim 1. Prelim. Resp. 7, 10–18.
`
`Patent Owner states the ’519 patent discloses that the “ordinary operation
`
`modes,” which require “operation,” are achieved by varying the clock
`
`signal’s frequency similarly to shifting gears in a car. Id. at 11–14 (quoting
`
`Ex. 1001, 8:56–65, 11:34–38) (citing Ex. 1001, 4:12–18, 12:37–45, 13:54–
`
`60) (reproducing Ex. 1001, Fig. 5). Patent Owner also argues that Ober’s
`
`core CPU, unlike the CPU described and claimed in the ’519 patent,
`
`operates in only one mode (i.e., RUN mode), and asserts that Ober’s CPU is
`
`not operational in the other modes (i.e., IDLE and various SLEEP modes).
`
`Id. at 10 (citing Ex. 1004, 5:37–40, 17:15–27), 14 (citing Ex. 1001, 4:12–18,
`
`12:37–45, 13:54–60; Ex. 1004, Tables 8–9, 13:61, 15:24–27, 17:15–26).
`
`Patent Owner further asserts that Ober explicitly defines the RUN mode “to
`
`operate on a fixed clock frequency that cannot be selected or reduced.” Id.
`
`at 14 (citing Ex. 1004, 17:15–26).
`
`At this stage, we disagree with Patent Owner that Ober does not teach
`
`or suggest “a plurality of ordinary operation modes.” Ober discloses that
`
`power management techniques to control CPU power (e.g., different power
`
`modes) at the microcontroller level during normal operations were known.
`
`See id. at 2:17–20, cited in Pet. 27. Ober, thus, suggests ordinarily skilled
`
`18
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`Patent 6,895,519 B2
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`artisans would have recognized that system LSIs have a plurality of ordinary
`
`operation modes during normal operations to control CPU power. See id.
`
`Consistent with the record evidence, the ’519 patent further describes
`
`“conventional clock operation modes” (Ex. 1001, 1:63–65, 6:10–11, Fig. 10)
`
`of a ST7 core or a microcontroller (id. at 2:61–67) that include a high-speed
`
`operation mode and a low-speed operation mode. Id., cited in part in Pet. 3.
`
`Regarding whether “ordinary operation modes” should be construed
`
`to require varying a clock signal’s speed/frequency used by the CPU
`
`(Prelim. Resp. 11–14), we note that claim 1’s preamble does not include this
`
`limitation. Ex. 1001, 14:15–19. The above-noted passages in the ’519
`
`patent cited by Patent Owner also do not define the phrase “ordinary
`
`operation mode” or otherwise explain its customary meaning, such that its
`
`construction should be limited to that asserted by Patent Owner. However,
`
`when discussing the “clock control library for controlling a clock frequency
`
`transition between said ordinary operation modes” below, we further address
`
`Patent Owner’s assertion related to varying a clock signal’s frequency.
`
`Petitioner also contends Ober teaches the “plurality of special modes”
`
`recited in the preamble. Pet. 25. Petitioner asserts Ober discloses an “IDLE
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`mode” and a “SLEEP MODE (Clock Not Distributed)” where the power
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`optionally can be turned off to most or all subsystems. Id. (citing Ex. 1004,
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`15:14–16, 16:12–15, 16:19–24). Petitioner also indicates the ’519 patent
`
`admits “special operation modes” were known. Id. at 4. Patent Owner does
`
`not expressly address Ober’s teaching of the “plurality of special modes” but
`
`argues Ober fails to teach the “second special mode” recited later in claim 1.
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`Prelim. Resp. 7, 30–32. We address this argument below in our analysis of
`
`that limitation.
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`19
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`Based on the current record, we are persuaded Petitioner has
`
`demonstrated sufficiently that Ober teaches or suggests claim 1’s preamble.
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`(ii) “a first memory”
`
`Claim 1 recites “a first memory that stores a clock control library for
`
`controlling a clock frequency transition between said ordinary operation
`
`modes” (“limitation 1.1”).8 Ex. 1001, 14:20–22. Petitioner contends the
`
`combination of Ober and Nakazato teaches or suggests this claimed element.
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`Pet. 25–31.
`
`Petitioner asserts an ordinarily skilled artisan would have understood
`
`Ober discloses the “first memory” as memory banks 54 and 56 located on
`
`Ober’s SoC. Id. at 25–26 (citing Ex. 1004, 5:50–53; Ex. 1003 ¶ 109)
`
`(reproducing Fig. 1 (annotated)). Petitioner further states Ober discusses its
`
`SoC runs applications and OSs and that an ordinarily skilled artisan would
`
`have understood that the applications and OSs are stored in memory banks
`
`54 and 56 when executing. Id. at 26 (citing Ex. 1004, 4:29–32, 5:31–45,
`
`16:12–15; Ex. 1003 ¶ 109).
`
` Patent Owner asserts that Ober does not disclose limitation 1.1
`
`because Ober does not disclose the recited “plurality of ordinary operation
`
`modes” as the preamble recites. See Prelim. Resp. 18. As noted above,
`
`Patent Owner asserts the “ordinary operation modes” should be construed to
`
`require varying a clock signal’s speed/frequency used by the CPU. Prelim.
`
`Resp. 11–14. As also noted above, we did not address this argument in
`
`connection with the preamble because limitation 1.1, not the preamble,
`
`requires “controlling a clock frequency transition between said ordinary
`
`
`8 We use numbering similar to Petitioner’s for consistency. See Pet. 25–44.
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`20
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`Patent 6,895,519 B2
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`operation modes.” Ex. 1001, 14:20–22.9
`
`More specifically, regarding the “clock control library” feature,
`
`Petitioner explains that Ober discusses power management subsystem 26
`
`and describes how this system is controlled by a “software configurable
`
`register” known as SFR 62. Pet. 26 (citing Ex. 1004, 2:59–62). Petitioner
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`states Ober’s register includes fields for adjusting the system clock’s
`
`frequency using a “sleep divide clock (SDCLK) bit” and “a divide clock
`
`(DIVCLK) bit,” which “either disables or provides divided clock signals to
`
`the subsystem during a SLEEP mode and also may provide a divided clock
`
`signal to the subsystem during a normal mode.” Id. at 26–27 (quoting
`
`Ex. 1004, 9:65–10:2) (citing Ex.1003 ¶ 110); id. at 24. As previously
`
`indicated, Petitioner asserts that Ober’s “divided clock” concept causes
`
`Ober’s CPU to exe
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