Advanced Micro
`Devices, Inc.
`v.
`Aquila Innovations Inc.
`
`U.S. Patent No. 6,895,519
`IPR2019‐01526
`Aquila Innovation Inc.’s Demonstratives
`
`IPR2019‐01526
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`1
`
`AQUILA - Ex. 2024
`
`
`Devices, Inc.
`v.
`Aquila Innovations Inc.
`
`U.S. Patent No. 6,895,519
`IPR2019‐01526
`Aquila Innovation Inc.’s Demonstratives
`
`IPR2019‐01526
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`1
`
`AQUILA - Ex. 2024
`
`
`
`Grounds
`
`IPR2019‐01526
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`2
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`
`
`Ground 1 – Ober + Nakazato
`
`• What is Petitioner’s Combination?
`
`• Multiple Limitations Not Disclosed In Combination
`• “plurality of ordinary operation modes”
`• “clock frequency transitions between said ordinary operation
`modes”
`
`• Combination Not Obvious
`• Unpredictable to write to unused bits in register
`• Power Management State Machine unpredictable outside of
`defined states
`• Ober teaches away from Nakazato
`
`IPR2019‐01526
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`3
`
`
`
`Ground 1 – What Is Petitioner’s
`Combination?
`• Petition: Ober’s Hardware + Nakazato’s Power‐
`Saving Driver
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`IPR2019‐01526
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`4
`
`
`
`Ground 1 – What Is Petitioner’s
`Combination?
`• Petition: Ober’s Hardware + Nakazato’s Power‐
`Saving Driver
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`IPR2019‐01526
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`5
`
`
`
`Ground 1 – What Is Petitioner’s
`Combination?
`Petitioner’s Combination : Ober’s Hardware +
`Nakazato’s Power‐Saving Driver
`
`Petition at 18.
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`IPR2019‐01526
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`
`
`Petitioner Abandoned Its Theory
`
`Reply at 16.
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`IPR2019‐01526
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`7
`
`
`
`The Petition “Makes No Sense”
`
`Reply at 16.
`
`Petition at 18.
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`IPR2019‐01526
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`8
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`
`
`The Petition “Makes No Sense”
`
`Reply at 16.
`
`Petition at 31.
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`9
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`
`
`Petitioner Cannot Raise New
`Theories In Reply
`
`“[T]he expedited nature of IPRs bring with it an obligation
`for petitioners to make their case in their petition to
`institute.” Intelligent Bio-Systems, Inc. v. Illumina
`Cambridge, Ltd., 821 F.3d 1359, 1369 (Fed. Cir. 2016); see
`also Wasica Fin. GmbH v. Continental Automotive Sys., Inc.,
`853 F.3d 1272, 1287 (Fed. Cir. 2017) (“We also are
`unpersuaded by [petitioner]’s attempts to cure the petition’s
`deficiencies in its subsequent briefing to the Board and to
`us.”); Trial Practice Guide (Aug. 2018 Update) at 14; 37
`C.F.R. § 42.23(b)
`
`Surreply at 2‐3.
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`10
`
`
`
`Improper Reply Theory: Ober +
`Nakazato Discloses The Preamble
`Petitioner argued that Ober alone disclosed the
`preamble.
`
`Petition at 25.
`
`Ex. 1003 ¶ 107.
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`11
`
`
`
`Improper Reply Theory: Ober +
`Nakazato Discloses The Preamble
`
`Dr. Albonesi admits that he did not cite to Nakazato
`in his declaration when opining on the preamble.
`Ex. 2023 91:10‐106:8
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`IPR2019‐01526
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`12
`
`
`
`Ground 1 – Ober + Nakazato
`
`• What is Petitioner’s Combination?
`
`• Multiple Limitations Not Disclosed In Combination
`• “plurality of ordinary operation modes”
`• “clock frequency transitions between said ordinary operation
`modes”
`
`• Combination Not Obvious
`• Unpredictable to write to unused bits in register
`• Power Management State Machine unpredictable outside of
`defined states
`• Ober teaches away from Nakazato
`
`IPR2019‐01526
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`13
`
`
`
`Ober Does Not Teach Or Suggest “A
`Plurality Of Ordinary Operation
`Modes.”
`
`Preamble of Claim 1:
`
`Petition: Ober alone discloses the preamble. Petition
`at 19‐25.
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`14
`
`
`
`Ober Does Not Teach “A Plurality
`Of Ordinary Operation Modes.”
`• The Petition relies only on the “divided clock signal”
`for the claimed ordinary operation modes. Petition
`at 24:
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`15
`
`
`
`Ober Does Not Teach “A Plurality
`Of Ordinary Operation Modes.”
`• The “divided clock” signal does not “cause Ober’s
`CPU clock to execute at various frequencies.”
`• All of the cited passages teach that Ober’s system clock
`can be reduced in SLEEP mode. Ex. 2005 ¶ 78.
`• The CPU core is IDLE, i.e., stopped, during SLEEP. Ex.
`1004 at 15:46‐51.
`
`• Therefore, there is no execution at various frequencies.
`
`IPR2019‐01526
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`16
`
`
`
`Ober Does Not Teach “A Plurality
`Of Ordinary Operation Modes.”
`• The system clock only transitions frequencies
`during SLEEP mode.
`• The CPU is IDLE, i.e., stopped, during SLEEP mode.
`• Dr. Albonesi:
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`IPR2019‐01526
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`17
`
`Ex. 2012 at 33:15‐21.
`
`
`
`Ober Does Not Teach “A Plurality
`Of Ordinary Operation Modes.”
`
`Ex. 2012 at 33:22‐34:4.
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`IPR2019‐01526
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`18
`
`
`
`Ober Does Not Teach “A Plurality
`Of Ordinary Operation Modes.”
`
`Ex. 2012 at 35:2‐9.
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`IPR2019‐01526
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`19
`
`
`
`Ober RUNs at a single frequency.
`
`Ober’s Power Management State Machine defines RUN
`State to require “Low Speed Clocks = False”
`
`Ex. 1004 at 17:17‐26
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`IPR2019‐01526
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`20
`
`
`
`Power Management Disabled
`During RUN
`Ober’s Power Management Functions, i.e., low speed
`clocks, are turned off by default.
`
`IPR2019‐01526
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`21
`
`Ex. 1004 at Table 5.
`
`
`
`Power Management Disabled
`During RUN
`Ober’s Power Management Functions, i.e., low speed
`clocks, are turned off by default.
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`22
`
`Ex. 2005 at ¶ 55.
`
`
`
`Ober Does Not Teach “A Plurality
`Of Ordinary Operation Modes.”
`Ober’s Power Management Functions, i.e., low speed
`clocks, are turned off by default.
`
`Ex. 1004 at 11:15‐22.
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`IPR2019‐01526
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`23
`
`
`
`Power Management Disabled
`During RUN
`Ober’s Power Management Functions, i.e., low speed
`clocks, are turned off by default.
`
`Ex. 1004 at Table 5.
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`IPR2019‐01526
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`24
`
`
`
`Ober Does Not Suggest “A Plurality
`Of Ordinary Operation Modes.”
`
`“Ober’s teaching that that divided clocks may be
`supplied to a peripheral subsystem during a normal
`mode does not itself teach or suggest that Ober’s
`CPU may execute instructions using the low‐speed
`divided clock.” POR at 39.
`
`IPR2019‐01526
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`25
`
`
`
`Ober Does Not Suggest “A Plurality
`Of Ordinary Operation Modes.”
`CPU core 22 does not have an SFR 116 to divide its
`own local clocks.
`
`Adding an SFR 116 to the CPU core 22 would cause
`the microcontroller to freeze or act unpredictably.
`
`IPR2019‐01526
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`26
`
`
`
`“Supplying” A Clock Does Not
`Teach “Operation”
`“Ordinary operation modes” are in response to the
`supplied clock frequencies.
`
`Petition at 24.
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`IPR2019‐01526
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`27
`
`
`
`“Supplying” A Clock Does Not
`Teach “Operation”
`
`IPR2019‐01526
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`28
`
`Ex. 2005 at ¶ 42.
`
`
`
`Ground 1 – Ober + Nakazato
`
`• What is Petitioner’s Combination?
`
`• Multiple Limitations Not Disclosed In Combination
`• “plurality of ordinary operation modes”
`• “clock frequency transitions between said ordinary operation
`modes”
`
`• Combination Not Obvious
`• Unpredictable to write to unused bits in register
`• Power Management State Machine unpredictable outside of
`defined states
`• Ober teaches away from Nakazato
`
`IPR2019‐01526
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`29
`
`
`
`“clock control library for controlling
`clock frequency transitions”
`Petition at 31:
`“A POSITA could merely have combined Nakazato's
`power‐saving driver and utility with Ober's SoC to
`achieve a combined system that allowed for OS and
`application control of CPU clock frequency.”
`
`IPR2019‐01526
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`30
`
`
`
`Nakazato: Intel Driver
`
`Ex. 1013 – ACPI 2.0: Reads or writes to unused bits
`are either ignored or generate undefined results.
`
`IPR2019‐01526
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`31
`
`
`
`Ground 1 – Ober + Nakazato
`
`• What is Petitioner’s Combination?
`
`• Multiple Limitations Not Disclosed In Combination
`• “plurality of ordinary operation modes”
`• “clock frequency transitions between said ordinary operation
`modes”
`
`• Combination Not Obvious
`• Unpredictable to write to unused bits in register
`• Power Management State Machine unpredictable outside of
`defined states
`• Ober teaches away from Nakazato
`
`IPR2019‐01526
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`32
`
`
`
`Writing Unused Bits In A Register Is
`Unpredictable
`
`Dr. Albonesi
`
`Dr. Przybylski
`
`IPR2019‐01526
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`33
`
`
`
`Writing Unused Bits In A Register Is
`Unpredictable
`Ex. 1013 – ACPI: Reads or writes to unused bits are
`either ignored or generate undefined results.
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`IPR2019‐01526
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`34
`
`
`
`Writing Unused Bits In A Register Is
`Unpredictable
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`IPR2019‐01526
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`35
`
`
`
`Writing Unused Bits In A Register Is
`Unpredictable
`ARM 920T Manual, Ex. 2009 at 48:
`
`NXP Manual, Ex. 2006 at 144:
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`IPR2019‐01526
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`36
`
`
`
`Undefined, Unpredictable State
`Machine States
`
`Ober’s Power
`Management State
`Machine does not have a
`defined state in which
`RUN mode runs on “LOW
`SLEEP CLOCKS.”
`
`Ex. 2011 at 304.
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`37
`
`
`
`Undefined, Unpredictable State
`Machine States
`
`Using Nakazato’s driver to
`write to the unused bits in
`SFR 62 would put the FSM
`into an undefined and
`unpredictable state.
`
`Ex. 1004, Fig. 6.
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`IPR2019‐01526
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`38
`
`
`
`Reducing The System Clock During
`RUN Is Unpredictable
`
`IPR2019‐01526
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`39
`
`Ex. 2005 at ¶ 92
`
`
`
`Reducing The System Clock During
`RUN Is Unpredictable
`Ober’s architecture depends upon RUN and IDLE
`having the full‐speed clock.
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`40
`
`Ex. 2005 at ¶ 96.
`
`
`
`Ober’s Goal: Decentralized Power
`Management
`
`Ex. 1004 at 2:17‐26.
`
`Ex. 1004 at 2:45‐48.
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`IPR2019‐01526
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`41
`
`
`
`Ober’s Goal: Decentralized Power
`Management
`
`Ex. 2003 at 3‐4.
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`IPR2019‐01526
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`42
`
`
`
`Nakazato Is Centralized
`
`Ex. 2005 at ¶ 102.
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`IPR2019‐01526
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`43
`
`
`
`Ground 2 – Ober + Nakazato +
`“Windows ACPI”
`• Ex. 1005 – “Windows ACPI” – not shown to be
`printed publication or authenticated.
`
`• Butler affidavit does not show that the .zip files in
`the link contained Ex. 1005.
`
`• Dr. Albonesi’s reply testimony is untimely.
`
`IPR2019‐01526
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`44
`
`
`
`Ground 3: Ober + Nakazato +
`Doblar
`Petition: A POSITA would have been motivated to
`add the redundant PLL of Doblar to Ober as a
`failsafe.
`
`Ober:
`
`IPR2019‐01526
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`45
`
`
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