UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`AQUILA INNOVATIONS, INC., a
`Delaware Corporation,
`
`Plaintiff,
`
`v.
`ADVANCED MICRO DEVICES, INC.,
`a Delaware corporation
`Defendant.
`
`No. 1:18-cv-554-LY
`
`
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`
`AQUILA INNOVATIONS, INC.’S
`PRELIMINARY INFRINGEMENT CONTENTIONS
`Pursuant to the Court’s Scheduling Order, D.I.23, Plaintiff Aquila
`
`
`
`Innovations, Inc. (“Aquila”) submits the following preliminary infringement
`
`contentions for U.S. Patents 6,239,614 (“’614 Patent”) and 6,895,519 (“’519 Patent”).
`
`These preliminary infringement contentions were prepared without the benefit of
`
`the Court’s claim construction or the parties’ exchange of constructions. Discovery
`
`has been stayed, and AMD has not produced any information concerning the
`
`Accused Products. Thus, this chart is based on publicly available evidence, and
`
`based upon information and reasonable belief in light of such evidence. As such,
`
`Aquila reserves the right to amend or supplement its contentions to address any
`
`issues arising from the Court’s constructions or to account for new information that
`
`becomes available.
`
`
`
`AMD EX1012
`U.S. Patent No. 6,895,519
`
`0001
`
`
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`AQUILA INNOVATIONS, INC., a
`Delaware Corporation,
`
`Plaintiff,
`
`v.
`ADVANCED MICRO DEVICES, INC.,
`a Delaware corporation
`Defendant.
`
`No. 1:18-cv-554-LY
`
`
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`
`AQUILA INNOVATIONS, INC.’S
`PRELIMINARY INFRINGEMENT CONTENTIONS
`Pursuant to the Court’s Scheduling Order, D.I.23, Plaintiff Aquila
`
`
`
`Innovations, Inc. (“Aquila”) submits the following preliminary infringement
`
`contentions for U.S. Patents 6,239,614 (“’614 Patent”) and 6,895,519 (“’519 Patent”).
`
`These preliminary infringement contentions were prepared without the benefit of
`
`the Court’s claim construction or the parties’ exchange of constructions. Discovery
`
`has been stayed, and AMD has not produced any information concerning the
`
`Accused Products. Thus, this chart is based on publicly available evidence, and
`
`based upon information and reasonable belief in light of such evidence. As such,
`
`Aquila reserves the right to amend or supplement its contentions to address any
`
`issues arising from the Court’s constructions or to account for new information that
`
`becomes available.
`
`
`
`AMD EX1012
`U.S. Patent No. 6,895,519
`
`0001
`
`
`
`(a) Identification of asserted claims
`
`’614 Patent: Claims 1, 2
`
`’519 Patent: Claims 1, 2, 3, 5, 6, 7, 10
`
`(b) Identification of accused products
`’614 Patent Accused Products:
`
`
`
`
`
`Aquila contends that all AMD processor products containing power gate rings
`
`infringe each of the asserted claims of the ’614 Patent. This specifically includes but
`
`is not limited to processors with cores having microarchitectures belonging to the
`
`following families:
`
`o AMD 12h Llano Fusion APUs
`o AMD 15h Bulldozer APUs
`o AMD 15h Piledriver APUs
`o AMD 15h Excavator APUs
`AMD products belonging to each product family are identified in Exhibits C.1
`
`through C.4. The identification of specific products was prepared without the
`
`benefit of discovery from AMD and may not include OEM or custom processor
`
`products. Aquila reserves the right to amend or supplement its identification of
`
`accused products as AMD provides more information.
`
`’519 Patent Accused Products:
`
`Aquila contends that all AMD processor products capable of entering/exiting
`
`the CC1, PC1, and PC6 states infringe each of the asserted claims of the ’519 Patent.
`
`This specifically includes but is not limited to processors with cores having
`
`microarchitectures belonging to the following families:
`
`-2-
`
`0002
`
`
`
`o AMD Family 12h
`o AMD Family 14h
`o AMD Family 15h
`o AMD Family 16h
`o AMD Family 17h
`AMD products belonging to each product family are identified in Exhibits C.1
`
`through C.5. The identification of specific products was prepared without the
`
`benefit of discovery from AMD and may not include OEM or custom processor
`
`products. Aquila reserves the right to amend or supplement its identification of
`
`accused products as AMD provides more information.
`
`(c) Claim Charts
`
`Claim charts for each asserted claim corresponding to each representative
`
`accused product are contained in the exhibits below.
`
`
`
`
`
`
`
`’614 Patent: Exhibit A
`
`’519 Patent: Exhibit B
`
`(d) Doctrine of Equivalents
`
`Aquila contends that each limitation in each asserted claim is met literally.
`
`The Court has not construed the asserted claims, and AMD has not yet provided
`
`discovery on the accused products or provided non-infringement contentions. Aquila
`
`reserves the right to respond if AMD provides non-infringement contentions, which
`
`response may include doctrine of equivalents contentions.
`
`
`
`-3-
`
`0003
`
`
`
`(e) Identification of Priority Date
`
`
`
`’614 Patent: Each asserted claim of the ’144 Patent is entitled to a priority
`
`date as late as January 14, 1999.
`
`
`
`’519 Patent: Each asserted claim of the ’519 Patent is entitled to a priority
`
`date as late as February 25, 2002.
`
`
`
`Dated: February 13, 2019
`
`
`
`
`
`Respectfully submitted,
`
`
`
`
`
`
`/s/Jing H. Cherng
`Robert E. Freitas (admitted pro hac vice)
`Jing H. Cherng (admitted pro hac vice)
`FREITAS & WEINBERG LLP
`350 Marine Parkway, Suite 200
`Redwood Shores, CA 94065
`Telephone: (650) 593-6300
`rfreitas@fawlaw.com
`gcherng@fawlaw.com
`
`
`Henry B. Gonzalez III
`State Bar No. 00794952
`Jeffrie B. Lewis
`State Bar No. 24071785
`GONZALEZ, CHISCANO, ANGULO,
`& KASSON, PC
`9601 McAllister Freeway, Suite 401
`San Antonio, Texas 78216
`Tel: (210) 569-8500
`hbg@gcaklaw.com
`jlewis@gcaklaw.com
`
`Attorneys for Plaintiff
`Aquila Innovations, Inc.
`
`-4-
`
`0004
`
`
`
`I hereby certify that on this 13th day of February, 2019, a true and correct
`copy of the foregoing was forwarded to the following:
`Jennifer Librach Nall
`Kevin J. Meek
`Aashish Kapadia
`Puneet Kohli
`jennifer.nall@bakerbotts.com
`kevin.meek@bakerbotts.com
`aashish.kapadia@bakerbotts.com
`puneet.kohli@bakerbotts.com
`DLWiLAN_AMD_BakerBotts@BakerBotts.com
`BAKER BOTTS LLP
`
`
`
`
`
`
`
`
`
`
`CERTIFICATE OF SERVICE
`
`Jing H. Cherng
`Jing H. Cherng
`
`
`
`
`-5-
`
`0005
`
`
`
`Accused Product: AMD Family 12h Fusion Processors
`
`Exhibit A.1: Preliminary Infringement Contention Claim Chart for U.S. Patent 6.239.614
`
`These preliminary infringement contentions were prepared without the benefit of the Court’s claim construction or the parties’ exchangeof constructions.
`As of the date of these contentions, AMD has not produced any information concerning the Accused Products. Thus, this chart is based on publicly available
`evidence, and based upon information and reasonablebelief in light of such evidence. As such, Aquila reserves the right to amend or supplementits
`contentions to address any issues arising from the Court’s constructions or to account for new information that becomesavailable.
`
`A semiconductor
`integrated circuit device,
`
`To the extent the ortis a2 ere fs Accused Products are semiconductor integrated circuit devices.
`= —
`
`Suisse‘AMD’S “LLANO”FUSIONAPU, Hot Chips 23, 19th August 2011, page 6.
`
`Graphics SIMD
`Eee hY
`
`Thy 0) Fa]
`
`0 Controllers
`
`0006
`
`
`
`
`Limitation
`
`The Accused Products contain a plurality of first unit cells:
`
`a plurality of first unit
`cells each including a
`plurality of first MOS
`transistors, each of the
`first MOStransistors
`havinga first threshold
`
`voltage; Contention
`
`As is typical of multi-VT standard cell design methodologies and structures, the Llano Accused Products use a mix
`of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt (LC-Hvt) standard
`cells.
`
`Graphics SIMD
`Nery]
`
`Display
`
`VO Controllers
`
`Source:AMD’S “LLANO”FUSIONAPU, Hot Chips 23, 19th August 2011, page6.
`
`0007
`
`
`
`
`
`ubMN. :
`
`Ce
`yt i
`
`The Accused Productscontain a plurality of first MOS transistors, each of the first MOStransistors havingafirst
`threshold voltage:
`
`0008
`
`
`
`
`
`JOTWANI ef al: AN 186-64 CORE IN 32 am SOLCMOS
`
`Contention
`
`a
`
`&
`
`(a)
`
`Post Swapping
`HVvt } Vt Types
`
`0% 20% 40% 60% 60%
`(a)
`=#45nm @&32nm
`
`PostSwapping
`
`(b)
`
`100%
`
`100%
`
`[ iStatic
`
`plurality of second MOS
`
`CustomMacros SND 26%
`StdCelis SD 25%
`Flops SB 17%
`Clock 38%
`s:.
`Gater @ 4%
`Static SD 2°.
`yi
`
`(a) Core device width histogram by Vt type. (b) Using Vi swaps to
`Fig. 10,
`reshape critical path timing opportunistically,
`
`| V. (b) Relative power improvement
`(a) TDP power distribution at
`Fig. IL.
`With respect to 45 nm generation core (normalized for performance}.
`
`Dynamic
`
`0009
`
`
`
`Contention
`.
`7
`eS
`
`Graphics SIMD
`
`Display
`
`| fe. Controllers
`
`Limitation
`
`transistors, each of the
`second MOStransistors
`having a second threshold
`
`
`
`deesbreeedOF68pte+ Graton
`tteestte
`HELL
`
`Array
`
`
`
`0010
`
`
`
`rcesLvt
`
`B
`
`Lvt
`
`uei
`
` Limitation
`
`Contention
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standardcells.
`
`Lyt
`
`ecute compute-intensive code and will therefore be a high-performance device.
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`
`0011
`
`
`
`The Accused Products contain a plurality of second MOStransistors, each of the second MOStransistors having a
`second threshold voltage:
`
`
`
`
`
`Limitation
`
`Contention
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`=z
`am 2s.
`aa iy
`ga.
`gi
`O4%
`
`aG
`
`ap:
`0% a 40% 60% 80%
`
`(a
`
`CustomMacros
`
`StdCells
`Flops
`Clock
`Repeater
`Gater
`Dynamic
`Static
`
`5
`
`Post S
`Swecring
`vn} Peet
`Vt Types
`
`i
`
`Post Swapping
`
`PreSwapping
`100
`125
`150
`
`75
`
`#45nm #32nm
`
`100%
`
`100%
`
`68%
`
`fi
`
`84%
`
`i
`
`Timing Slack (ps)
`
`Static
`
`Dynamic
`
`0012
`
`
`
`
`
`Limitation
`
`comprisedofsaid first and
`second unit cells laid in
`
`array form; Contention
`VO Controllers
`
`Graphics SIMD
`PNgeht
`
`Display
`
`0013
`
`
`
`
`
`Contention
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standardcells.
`
`
`
`Lvt [svt
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`
`0014
`
`
`
`
`
`Limitation
`
`Contention
`
`a power switch disposed
`aroundsaid unitcell
`array and comprisedof a
`plurality of third MOS
`transistors, each of the
`third MOStransistors
`having the second
`threshold voltage; and
`
`=
`Poe rereWwererrere
`939559935599395555
`aOetetanictl
`
`Virtual voltage spreads uniformly
`Bumps nearhot spots can exceed max limits
`
`Footeves
`ls
`
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critical paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoff between High-Vt and Low-Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High-Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. ‘The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems,pp. 4-5.
`
`15 0) My Pn og Source: PRACTICAL POWER GATING AND DYNAMIC VOLTAGE/FREQUENCYSCALING by Stephen
`
`The Accused Products contain a power switch disposed aroundsaid unit cell array:
`LLANO CPU CORERING GATING
`WITH PACKAGE LAYER ASSIST
`cE
`eo er eee aeee
`ese es
`——
`©,sosane88
`
`”
`
`—susan
`
`a
`
`“ree
`
`vesfo
`
`0015
`
`
`
`Kosonocky, page 50.
`
`Contention
`
`Virtual eaecies uniformly
`
`Bumps near hot spots can exceed max limits
`
`The Accused Products contain a plurality of third MOStransistors:
`LLANO CPU CORE RING GATING
`WITH PACKAGE LAYER ASSIST
`
`
`
`CMOS,SooliespeaclngetCorefn32oemSO High Ryocancreatenoiseissues sl
`
`
`edt PRACT.TCALPOWER GATING AND DYNAMIC VOLTAGE/FREQUENCYSCALINGby Stephen
`
`Raw Jotwani, Sram Sundar:
`
`0016
`
`
`
`
`
`Limitation
`
`Contention
`
`Wedefined a low-power mode called core-level C6 (CC6) to
`allow core-level power gating [5] during periods of inactivity,
`The core is isolated fromthe supply during CC6 by a power-gate
`ring surrounding the CPU and L2 cachepair, allowing core level
`power down in a chip with multiple cores attached to a common
`power supply. The SOI process enables the gating of VSS (not
`
`VDD). constructing thdpower-gatewithregularVtaMOS}logic
`devices without the need for extra processing steps to reduce
`on-state resistance [6]. Fig. 12(a) describes the core operations
`controlled by the power management system for CC6 entry and
`exit sequences.
`Fig. 12(b) details the connections of the power-gate ring with
`respect to the core and the C4 bumps. In addition to two 16X
`M10 and MI! on-die metal layers, a low-impedance package
`layer connected to the die by C4 bumpsis dedicated for use as a
`virtual-groundlayer, eliminating the need for any ultra-thick sil-
`icon metallization layer [6]. The low-impedance package layer
`
`said unit cell array.
`
`VII. POWER GATING
`
`Source: An x86-64 Core in 32nm SOI CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 1,
`JANUARY 2011, page 6.
`
`0017
`
`
`
`
`
`Contention
`
`LLANO CPU CORE RING GATING
`WITH PACKAGE LAYER ASSIST
`ss
`
`aesssoess.
`eseeeeease
`seenaneen
`
`SeesawSseanse#
`
`Virtual voltage spreads uniformly
`Bumps near hot spots can exceed max limits
`
`:
`
`
`
`Source: PRACTICAL POWER GATING AND DYNAMIC VOLTAGE/FREQUENCYSCALING by Stephen
`Kosonocky, page 50.
`
`MO—iSy&&&& 11.tt
`worst
`ov
`:
`;
`222eeeereWeeroeren
`A
`A
`4
`= (a
`.
`
`Ryss
`
`VSS,
`5
`Ravi Jotwani, Snram Sundaram, Stephen Kosonocky,
`Trop
`Alex Schaeter, Victor F. Andrade, Amy Novak,
`"
`‘
`i
`Samuel Naffziger, “An x66-64 Core in 32 nm SO!
`High Ryss can create noise issues
`culos’Jac
`201
`tet ee Cay ant pe 1 ee © ey Conny tneere dame 1" 2D‘ Beet Cet
`
`Res = 1m Q =
`
`.
`
`0018
`
`
`
`
`
`Limitation
`
`Contention
`
`Two major knobs have emerged for controlling power
`
`1. Dynamic Voltage and Frequency Scaling
`— Optimize performance for the application while it’s
`running
`2. Power Gating
`— Gate powerduring idle periods
`
`Each present unique challengesfor
`implementation and optimization
`
`
`
`
`
`Kosonocky, page 8.
`
`
`
`
`
`aoPee catersondDera met)|SechenteewaeFreceeecyDcahegtewews Pacant he wos
`
`
`
`Source: PRACTICAL POWER GATING AND DYNAMIC VOLTAGE/FREQUENCYSCALINGby Stephen
`
`0019
`
`
`
`Accused Products: AMD Family 15h Bulldozer/Piledriver APU Processors
`
`Exhibit A.2: Preliminary Infringement Contention Claim Chart for U.S. Patent 6,239,614
`
`These preliminary infringement contentions were prepared without the benefit of the Court’s claim construction or the parties’ exchange of constructions.
`As of the date of these contentions, AMD hasnot produced any information concerning the Accused Products. Thus, this chart is based on publicly available
`evidence, and based upon information and reasonablebelief in light of such evidence. As such, Aquila reserves the right to amend or supplementits
`contentions to address any issues arising from the Court’s constructionsor to account for new information that becomesavailable.
`
`Limitation
`
`
`| A-semiconductor integrated circuit
`device, comprising:
`
`Contention
`=
`| To the extent the preamble is a limitation, the Accused Products are a semiconductor integrated device.
`
`
`
`Vy
`
`sma) a) |
`
`0020
`
`
`
`The Accused Productdiscloses a
`
`plurality of first unit cells.
`
`Contention
`
`Limitation
`
`a plurality offirst unit cells each
`including a plurality of first MOS
`transistors, each of the first MOS
`transistors having a first threshold
`
`THE DIE | Photograph
`rr Corr
`
`es
`
`0021
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Floorplan (315 mm7)
`
`
`
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS:Using the
`
`2M
`
`Etrae
`
`fest =(01cm
`aoe
`
`
`
`0022
`
`
`
`
`Limitation
`Contention
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standard cells.
`
`The Bulldozer module contains 84 unique custom macros and
`317,000 scannable flops. Module-level VSS power gating (C6)
`is used to reduce leakage power by approximately 95% when
`both cores are idle [4]. The 32 nm SOI process provides three
`transistor V7 types (low, regular, and high), with longer channel
`lengths used to achieve even finer-grained trade-offs between
`leakage and delay. V7’s used across the design consist mostly
`of regular (47%) and long-channelregular (46%), with less than
`1% low-V 7 used for the mostcritical paths.
`Source: McIntyre et al., Design Of The Two-Core x86-64 AMD “Bulldozer” Module In 32 nm SOI CMOS, IEEE Journal of Solid-
`State Circuits, Vol. 47, No. 1, January 2012, page 165.
`
`uteflwdfagfoudubefea
`
`
`0023
`
`
`
` Limitation
`
`Contention
`
`voltage.
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critical paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoff between High-Vt and Low-Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High-Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. ‘The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems,pp. 4-5.
`
`The Accused Products contain a plurality of first MOStransistors, each of the first MOStransistors havinga first threshold
`
`0024
`
`
`
`Limitation
`
`Contention
`
`THEDIE| Process Technology
`
`RattNecatLe
`
`* Low-k dielectric
`
`* 32-nm Silicon-On-insulator (SOl) Hi-K Metal Gate
`(HKMG)process from GlobalFoundries
`
`transistors.
`
`* Dual strain liners and eSiGe to improve
`performance.
`
`* Multiple VT (HVT, VT, LVT) and long-channel
`
`0025
`
`
`
` JOTWANI et al: AN 586-64 CORE IN 32 am SOIL CMOS
`
`MOStransistors, each of the
`
`§(
`
`a)
`
`RVt} LCRVt
`
`HVt }
`
`Post Swapping
`Vt Types
`
`@32nm
`
`Post Swapping
`
`PreSwapping
`
`100%
`
`tli
`
`Dynamic
`
`Static
`
`Timing Slack (ps)
`(b)
`
`(a) Core device width histogram by Vt type. (b) Using Vi swaps to
`Fig. 10.
`reshape critical path timing opportunistically
`
`(a) TDP power distribution at | V. (b) Relative power improvement
`Fig, 11.
`with respect to 45 amgeneration core (normalized for performance).
`
`0026
`
`
`
`Limitation
`
`second MOStransistors having a
`second threshold voltage;
`
`Contention
`
`THE DIE | Photograph
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS:Using the
`core code named “Bulldozer”, August 18, 2011, page 3.
`
`0027
`
`
`
`THE DIE | Floorplan (315 mm?)
`
`
`
`Ped eneat
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS:Using the |
`
`Limitation
`
`Contention
`
`
`
`0028
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Process Technology
`
`* 11-metal-layer-stack
`
`* Low-k dielectric
`
`* 32-nm Silicon-On-insulator (SOl) Hi-K Metal Gate
`(HKMG)process from GlobalFoundries
`
`transistors.
`
`* Dual strain liners and eSiGe to improve
`eatgitoe
`
`* Multiple VT (HVT, RVT, LVT) and long-channel
`
`0029
`
`
`
`
`Limitation
`Contention
`
`The Bulldozer module contains 84 unique custom macros and
`317,000 scannable flops. Module-level VSS powergating (C6)
`is used to reduce leakage power by approximately 95% when
`both cores are idle [4]. The 32 nm SOI process provides three
`transistor V7 types (low, regular, and high), with longer channel
`lengths used to achieve even finer-grained trade-offs between
`leakage and delay. V 7’s used across the design consist mostly
`of regular (47%) and long-channelregular (46%), with less than
`1% low-V 7 used for the mostcritical paths.
`Source: McIntyre et al., Design Of The Two-Core x86-64 AMD “Bulldozer” Module In 32 nm SOI CMOS, TEEE Journal of Solid-
`State Circuits, Vol. 47, No. 1, January 2012, page 165.
`
`
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hvt) standardcells.
`
`LutHTHee
`
`0030
`
`
`
` Limitation
`
`Contention
`
`a second threshold voltage:
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critical paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoff between High-Vt and Low-Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High-Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. ‘The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems,pp. 4-5.
`
`The Accused Products contain a plurality of second MOStransistors, each of the second MOStransistors having
`
`0031
`
`
`
`'
`ve 7}PostSwapping
`Post S
`RVt | LCRVt
`Vt Types
`
`#245nm &32nm
`
`n
`
`
`
`The Accused Products contain a unit cell array comprised ofsaid first and second unit cells laid in array form
`
`Post Swapping
`
`75
`
`Timing Slack (ps)
`(b)
`
`{00%
`
`;i
`
`Static
`
`100%
`
`Dynamic
`
`(b)
`
`(a) Core device width histogram by Vt type. (b) Using Vt swaps to
`Fig. 10.
`reshape critical path timing opportunistically,
`
`(a) TDP power distribution at 1 V. (b) Relative power improvement
`11.
`Fig.
`with respect to 45 nm generation core (normalized for performance).
`
`0032
`
`
`
`Limitation
`
`Contention
`
`THE DIE | Photograph
`
`CVSSSeeteed
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS:Using the
`core code named “Bulldozer”, August 18, 2011, page 3.
`
`0033
`
`
`
`
`
`Source: Scrbaket al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems,pp. 4-5.
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critical paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoff between High-Vt and Low-Vt devices by having medium power re-
`
`0034
`
`
`
`Limitation
`
`Contention
`
`a powerswitch disposed around
`said unit cell array and comprised
`of a plurality of third MOS
`transistors, each of the third MOS
`transistors having the second
`
`The Accused Products contain a powerswitch disposed aroundsaid unit cell array and comprised ofa pluraility of third MOS
`transistors.
`
`POWER MANAGEMENT| CoreC6State (CC6)
`
`threshold voltage; and
`
`if a core isn't active,
`*Core C6:
`remove power
`
`*Implementedin this physical
`design by a power gating ring
`that isolates the Core VSS for
`each Bulldozer module from the
`“Real” VSS
`
`»"CC6 entry: when both Bulldozer
`cores in the module areidle,
`flush caches and dump register
`state to CC6 save space, then
`gate Core VSS
`
`j
`
`Bulldozer
`Module
`
`hz Power Gating FETS
`
`0035
`
`
`
`Limitation
`
`Contention
`
`Source: Sean White, HIGH-PERFORMANCE POWER-EFFICIENTX86-64 SERVER AND DESKTOP PROCESSORS:Using the
`core code named “Bulldozer”, August 18, 2011, page 21.
`
`Each of the third MOStransistors of the Accused Products has the second threshold voltage:
`
`» 32-nm Silicon-On-insulator (SOl) Hi-K Metal Gate
`(HKMG)process from GlobalFoundries
`
`transistors.
`
`THE DIE | Process Technology
`
`MeCercatolee
`
`* Low-k dielectric
`
`* Dual strain liners and eSiGe to improve
`performance.
`
`* Multiple VT (HVT, RVT, LVT) and long-channel
`
`0036
`
`
`
`
`
`Limitation
`
`Contention
`
`core code named “Bulldozer”, August 18, 2011, page 6.
`
`Each of the third MOStransistors of the power gate ring has the second threshold voltage.
`VII. POWER GATING
`
`We defined a low-power mode called core-level C6 (CC6) to
`allow core-level power gating [5] during periods of inactivity.
`The coreis isolated from the supply during CC6 by a power-gate
`ring surrounding the CPU and L2 cachepair, allowing core level
`power down in a chip with multiple cores attached to a common
`power supply. The SOI process enables the gating of VSS (not
`
`VDD), constructing thdpower-gatewithregularVinMOSllogic
`devices without the need for extra processing steps to reduce
`on-state resistance [6]. Fig. 12(a) describes the core operations
`controlled by the power managementsystem for CC6 entry and
`exit sequences.
`Fig. 12(b) details the connections of the power-gate ring with
`respect to the core and the C4 bumps. In addition to two 16X
`M10 and M11! on-die metal layers, a low-impedance package
`layer connected to the die by C4 bumpsis dedicated for use as a
`virtual-ground layer, eliminating the need for anyultra-thicksil-
`icon metallization layer [6]. The low-impedance package layer
`
`alray.
`
`0037
`
`
`
`THE DIE| Floorplan (315 mm?)
`
`peek ES
`
`STLS ACoeee
`
`he A semiconductor integrated circuit
`+ The powergate ring is turned off during standby and turned on whenthe core exits C6state.
`core code named “Bulldozer”, August 18, 2011, page 5.
`Limitation Contention
`
`Bulldozer
`
`Fr
`
`
`
`0038
`
`
`
`Limitation
`
`device accordingto claim 1,
`wherein said powerswitch is turned
`off during standby and turned on
`
`
`
`1%low-V 7 used for the mostcritical paths.
`
`The Bulldozer module contains 84 unique custom macros and
`317,000 scannable flops. Module-level VSS power gating (C6)
`is used to reduce leakage power by approximately 95% when
`both cores are idle [4]. The 32 nm SOIprocess provides three
`transistor V7 types (low, regular, and high), with longer channel
`lengths used to achieve even finer-grained trade-offs between
`leakage and delay. V p's used across the design consist mostly
`of regular (47%) and long-channel regular (46%), with less than
`
`Contention
`
`Source: McIntyre et al., Design Of The Two-Core x86-64 AMD “Bulldozer” Module In 32 nm SOI CMOS, TEEE Journal of Solid-
`State Circuits, Vol. 47, No. 1, January 2012, page 165.
`
`
`
`0039
`
`
`
`Limitation
`
`Contention
`
`|
`
`- Bulldozer
`Module
`
`~~
`
`Power Gating FETs
`
`interrupts, etc.)
`
`*"CC6 entry: when both Bulldozer "3°"
`coresin the module areidle,
`flush caches and dump register
`state to CC6 save space, then
`gate Core VSS
`
`if acore isn’t active,
`*Core C6:
`remove power
`
`*Implementedin this physical
`design by a power gating ring
`that isolates the Core VSSfor
`each Bulldozer module from the
`“Real” VSS
`
`*"CC6 exit: ungate Core VSS,
`reload CC6 savedstate, resume
`execution (ex: service
`
`0040
`
`
`
`Accused Product: AMD APUscontaining Excavator cores (Representative Product: AMD Carrizo APU Processors)
`
`Exhibit A.3: Preliminary Infringement Contention Charts for U.S. Patent 6,239,614
`
`These preliminary infringement contentions were prepared without the benefit of the Court’s claim construction or the parties’ exchange of constructions.
`As of the date of these contentions, AMD has not produced any information concerning the Accused Products. Thus, this chart is based on publicly available
`evidence, and based upon information and reasonablebelief in light of such evidence. As such, Aquila reserves the right to amend or supplement its
`contentions to address any issuesarising from the Court’s constructions or to account for new information that becomesavailable.
`
`
`To the extent the preambleis a limitation, the Accused Products are semiconductorintegratedcircuits. circuit device, comprising:
`
`A semiconductor integrated
`
`Exhibit A.3
`
`0041
`
`-1-
`
`0041
`
`
`
`AMD 6' GENERATION
`A-SERIES PROCESSOR
`
`DDR/PHY.
`
`X86
`Welsfetta
`
`NET
`Wen
`
`Southbridge
`
`Northbridge
`
`welETEN
`
`Limitation Contention
`
`Source: Krishnan, Energy Efficient Graphics and Multimedia in 28nm Carrizo APU | Hot Chips27,p. 2.
`
`To the extent that the powergate ring implemented in this product operates similarly to the Bulldozer or Llano
`powergate rings, for example in terms of the threshold voltages of the MOStransistors in the various unit cells
`and the powerswitch, Aquila contends that the charts applicable to those products apply equally to this product,
`
`Exhibit A.3
`
`0042
`
`-2-
`
`0042
`
`
`
`Ieies andincorporates those chartsbyreference.
`
`The Accused Productsdisclose a plurality of first unit cells:
`
`voltage;
`
`
`Limitation
`Contention
`
`a plurality of first unit cells
`each including a plurality of
`first MOStransistors, each of
`the first MOStransistors
`havinga first threshold
`
`Exhibit A.3
`
`0043
`
`-3-
`
`0043
`
`
`
`
`Limitation
`
`Modern multi-VT standard cell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channel high Vt
`(LC-Hyvt) standardcells.
`
`[Lut] bt]
`Lvt
`{uve} t/t
`vt
`GeVYfiter}fillerfOVY U-VETLVfiller filler
`
`Source: Scrbaket al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems,pp. 4-5.
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critical paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoff between High-Vt and Low-Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High-Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. ‘The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`
`Exhibit A.3
`
`0044
`
`-4-
`
`0044
`
`
`
`
`
`DYNAMIC UVD POWER GATING PN|oP
`
`:
`“Kaveri” UVD busy and burning power the whole time
`
`
`Beinn 44 Dynamic inter frame power gating controlled by rtsEEEEEEEEUEUEEEEEEEEEE———————————__—___——___
`microcontroller firmware
`VJ
`)
`I
`i
`ad
`lad
`rom
`v
`
`- Pipeline idle detection enables header/footer
`power gating of the entire IP
`
`Dynamic power gating along with low power
`hardening of the video decoder enables CZ to
`negate the bigger video decoder needed for
`H.265offload
`
`ee Sela metaa ee Le) cee oe
`
`“Carrizo” UVD and power gates
`
`Limitation
`
`Contention
`
`The Accused Products disclose a plurality of first MOStransistors, each of the first MOS transistors having a
`first threshold voltage, e.g., RVt:
`
`teeoff ond PUTS DRAMinto low power made
`
`Source: ENERGY EFFICIENT GRAPHICS AND MULTIMEDIA IN 28NM CARRIZO APU, page 21 HOT CHIPS
`27 —- AUGUST2015
`
`Exhibit A.3
`
`0045
`
`-5-
`
`0045
`
`
`
`The Accused Products disclose a plurality of second unit cells:
`
`a plurality of second unit cells
`each including a plurality of
`second MOStransistors, each
`of the second MOStransistors
`having a second threshold
`voltage;
`
`
`Limitation
`Contention
`
`
`
`Modern multi-VT standardcell design methodologies and structures such as those used in the Llano Accused
`Products use a mix of low Vt (LVt), regular Vt (RVt), long channel regular Vt (LC-RVt) and long channelhigh Vt
`
`Exhibit A.3
`
`0046
`
`0046
`
`
`
`
`Limitation
`Contention
`
`(LC-Hyvt) standardcells.
`
`HeeEee
`
`Source: Scrbak et al., DVFS Space Exploration in Power Constrained Processing-in-Memory Systems, pp. 4-5.
`
`DVFS Characteristics Modern computer chips are designed using multiple
`types of transistors, i.e. a mixture of low-, medium-, and high-threshold transis-
`tors, to target different design tradeoffs, e.g. high-performance vs. low power.
`Low-threshold voltage (Low-Vt) devices are used in timing-critical paths,
`but have high leakage power. High-threshold voltage (High-Vt) devices have
`low leakage power but are slower, and are typically used in circuits that are
`off the timing-critical paths. Medium-threshold voltage (Mid-Vt) devices offer
`a tradeoff between High-Vt and Low-Vt devices by having medium power re-
`quirements and medium delay. In general, low power chips are designed using a
`larger percentage of High-Vt devices and high-performance chips with a larger
`percentage of Mid-Vt and Low-Vt devices. ‘The host processor is assumed to ex-
`ecute compute-intensive code and will therefore be a high-performance device.
`
`Exhibit A.3
`
`0047
`
`-7-
`
`0047
`
`
`
`Limitation
`
`Contention
`
`The Accused Products disclose a plurality of
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
