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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
`Petitioner
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`v.
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`AQUILA INNOVATIONS, INC.
`Patent Owner
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`
`
`Case IPR2019-01525
`Patent 6,239,614 B1
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`PETITION FOR INTER PARTES REVIEW
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`
`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II. MANDATORY NOTICES ............................................................................. 4
`
`A.
`
`B.
`
`C.
`
`Real parties-in-interest .......................................................................... 4
`
`Notice of related matters ....................................................................... 4
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`Lead and back-up counsel with service information ............................ 4
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`III. GROUNDS FOR STANDING ........................................................................ 5
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`IV.
`
`IDENTIFICATION OF CHALLENGE .......................................................... 5
`
`V.
`
`THE ’614 PATENT ......................................................................................... 7
`
`A.
`
`B.
`
`C.
`
`D.
`
`Technical Background ........................................................................... 7
`
`The Alleged Problem in the Prior Art ................................................. 11
`
`The Alleged Invention of the ’614 Patent ........................................... 11
`
`Summary of the Prosecution History .................................................. 14
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`VI. LEVEL OF ORDINARY SKILL IN THE ART ...........................................14
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`VII. CLAIM CONSTRUCTION ..........................................................................15
`
`VIII. OVERVIEW OF THE APPLIED REFERENCES .......................................25
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Overview of Urano....................................................................25
`
`Overview of Mutoh021 .............................................................26
`
`Overview of Mutoh ...................................................................29
`
`Overview of Douseki ................................................................31
`
`Overview of Ramus ..................................................................33
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`- i -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`IX. GROUNDS OF REJECTION .......................................................................34
`
`A. Ground 1: Claims 1-3 are obvious over Urano in view of
`Mutoh021 ............................................................................................ 34
`
`1.
`
`2.
`
`3.
`
`4.
`
`A POSA Would Have Been Motivated to Combine
`Urano and Mutoh021 ................................................................34
`
`Claim 1 is obvious over Urano in view of Mutoh021 ..............41
`
`Claim 2 is obvious over Urano in view of Mutoh021 ..............56
`
`Claim 3 is obvious over Urano in view of Mutoh021 ..............57
`
`B.
`
`Ground 2: Claims 1-3 are obvious over Mutoh in view of
`Mutoh021 ............................................................................................ 59
`
`1.
`
`2.
`
`3.
`
`4.
`
`A POSA Would Have Been Motivated to Combine
`Mutoh and Mutoh021 ...............................................................59
`
`Claim 1 is obvious over Mutoh in view of Mutoh021..............64
`
`Claim 2 is obvious over Mutoh in view of Mutoh021..............75
`
`Claim 3 is obvious over Mutoh in view of Mutoh021..............77
`
`C.
`
`Ground 3: Claims 4-5 are obvious over Douseki in view of
`Ramus .................................................................................................. 77
`
`1.
`
`2.
`
`3.
`
`A POSA Would Have Been Motivated to Combine
`Douseki and Ramus ..................................................................78
`
`Claim 4 is obvious over Douseki in view of Ramus ................80
`
`Claim 5 is obvious over Douseki in view of Ramus ................89
`
`X.
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`CONCLUSION ..............................................................................................92
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`- ii -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`
`EXHIBIT LIST
`
`Exhibit
`
`DESCRIPTION
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`U.S. Patent No. 6,239,614 to Morikawa (“’614 patent”)
`
`Prosecution History of U.S. Patent No. 6,239,614 (“’614
`Prosecution History”)
`
`Declaration of Dr. Holberg in Support of Petition for Inter Partes
`Review of U.S. Patent No. 6,239,614 (“Holberg Decl.”)
`
`Dr. Holberg’s Curriculum Vitae
`
`Mutoh et al., “1-V Power Supply High-Speed Digital Circuit
`Technology with Multithreshold-Voltage CMOS,” IEEE Journal
`of Solid-State Circuits, Vol. 30, No. 8, 847-854 (1995) (“Mutoh”)
`
`U.S. Patent No. 6,653,693 to Makino (“Makino”)
`
`Japanese Patent Publication No. H10125878 to Masami Urano
`(“Urano”)
`
`English translation of Urano
`
`Translation Certificate of Urano
`
`U.S. Patent No. 5,486,774 to Douseki et al. (“Douseki”)
`
`U.S. Patent No. 5,631,492 to Ramus et al. (“Ramus”)
`
`Japanese Patent Publication No. H0818021 to Shin’ichiro Mutoh
`et al. (“Mutoh021”)
`
`English translation of Mutoh021
`
`Translation Certificate of Mutoh021
`
`Declaration of Dr. Holberg in Support of District Court Case No.
`1:18-cv-00554-LY (“Holberg Dec. 2”)
`
`1016
`
`Saigo et al., “A 20 K-Gate CMOS Gate Array,” IEEE Journal of
`
`
`
`- iii -
`
`

`

`Exhibit
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`DESCRIPTION
`
`Solid State Circuits, Vol. SC-18, No. 5, 578-584 (1983)
`
`Sato et al., “A Subnanosecond 2000 Gate Array with ECL 10OK
`Compatibility,” Vol. ED-31, No. 2, 139-143 (1984)
`
`Massetti et al., “A CMOS-Based Mixed Analog-Logic Standard
`Cell Product Family,” IEEE 1988 Custom Integrated Circuits
`Conference, 24.1.1 (1988)
`Horowitz et al., “Chapter 2: Transitors,” The Art of Electronics, 2nd
`Edition, Cambridge University Press (1989)
`
`U.S. Patent No. 4,001,869 to Brown (“Brown”)
`
`U.S. Patent No. 4,499,387 to Konishi (“Konishi”)
`
`U.S. Patent No. 5,544,102 to Tobita et al. (“Tobita”)
`
`U.S. Patent No. 6,285,052 to Draper (“Draper”)
`
`U.S. Patent No. 6,292,015 to Ooishi et al. (“Ooishi”)
`
`Baker et al., “CMOS Circuit Design, Layout, and Simulation”
`Institute of Electrical and Electronics Engineers, Inc. (1998)
`
`Sato et al., “A Subnanosecond 2000 Gate Array with ECL 100K
`Compatibility,” IEEE Journal of Solid-State Circuits, Vol. SC-19,
`No. 1, 5-9 (1984)
`
`Smith et al., “A CMOS-Based Analog Standard Cell Product
`Family,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 2,
`370-379 (1989)
`
`U.S. Patent No. 6,340,825 to Shibata (“Shibata”)
`
`Scheduling Order, Aquila Innovations, Inc. v. Advanced Micro
`Devices, Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.), issued
`January 18, 2019
`
`1030
`
`Order Granting Unopposed Motion to Extend Claim Construction
`
`
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`- iv -
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`

`

`Exhibit
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`DESCRIPTION
`
`Deadlines, Aquila Innovations, Inc. v. Advanced Micro Devices,
`Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.), issued May 14,
`2019
`
`Webster’s Third New International Dictionary (2002)
`
`U.S. Patent No. 4,937,649 to Shiba et al. (“Shiba”)
`
`U.S. Patent No. 6,459,331 to Takeuchi et al. (“Takeuchi”)
`
`Weste, Neil H. E. et al., Principles of CMOS VLSI Design (2d ed.
`1993) (“Weste”)
`
`Laplante, P.A., Comprehensive Dictionary of Electrical
`Engineering (CRC Press 1999) (“Laplante”)
`
`Graf, R.F., Modern Dictionary of Electronics (7th ed. 1999)
`(“Graf”)
`
`Merriam-Webster’s Collegiate Dictionary (10th ed. 2001)
`
`Cabe, Adam and Shamik Das, “Performance Simulation and
`Analysis of a CMOS/Nano Hybrid Nanoprocessor System,”
`Nanotechnology, Vol. 20, No. 16, 22 (Apr. 2009) (“Cabe and
`Das”)
`
`U.S. Patent No. 5,781,062 to Mashiko et al. (“Mashiko”)
`
`U.S. Patent No. 5,933,384 to Terada et al. (“Terada”)
`
`U.S. Patent No. 6,034,563 to Mashiko (“Mashiko1996”)
`
`U.S. Patent No. 6,046,627 to Itoh et al. (“Itoh”)
`
`U.S. Patent No. 6,111,427 to Fujii et al. (“Fujii”)
`
`U.S. Patent No. 6,119,250 to Nishimura et al. (“Nishimura”)
`
`U.S. Patent No. 6,140,836 to Fujii et al. (“Fujii1998”)
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`
`
`- v -
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`

`

`Exhibit
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`DESCRIPTION
`
`1046
`
`U.S. Patent No. 6,211,725 to Kang (“Kang”)
`
`
`
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`- vi -
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`

`

`
`I.
`
`Introduction
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,728,144 B2
`
`Advanced Micro Devices, Inc. (“AMD”) petitions for inter partes review of
`
`claims 1-5 (“challenged claims”) of U.S. Patent No. 6,239,614 to Morikawa (the
`
`“’614 patent”) assigned to Aquila Innovations Inc. (“Aquila”).
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`The ’614 patent relates to a purported improvement to a layout of a well-
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`known integrated circuit—a multi-threshold complementary metal oxide
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`semiconductor (“MTCMOS”). The ’614 patent concedes that MTCMOS devices,
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`and many of the claimed features (e.g., MOS transistors of different threshold
`
`values, power switches, input/output circuits, power supply lines, and virtual
`
`power supply lines), were already known. EX1001, ’614 patent, 1:14-32.
`
`According to the ’614 patent, however, the prior art layout technique for
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`MTCMOS devices—a standard cell system—required long manufacturing times
`
`and could not implement high-speed logical operations. Id., 1:50-67.
`
`The ’614 patent purports to solve these problems by using a gate array
`
`layout (“unit cells”) instead of a standard cell system as well as decoupling
`
`capacitors. Id. But long before the ’614 patent’s claimed priority date of 1999,
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`these allegedly novel features were well-known. Urano, for example, recognized
`
`before 1999 that the same problem of long manufacturing times for MTCMOS
`
`devices using standard cell systems was solved by the use of a gate array of CMOS
`
`circuits to achieve low voltage, high-speed operation. EX1008, Urano, Abstract,
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`
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`- 1 -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`¶¶0006, 0007, 0027 (“[I]n the conventional MT-CMOS technology there is a
`
`problem in that the development lead time will be long, because it has come to be
`
`applied to cell-based or fully custom ICs, wherein transistors with threshold values
`
`that are freely different can be included.”), 0029 (“The present invention … and
`
`the object thereof is to provide a gate array that achieves low-voltage/high-speed
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`operation through the use of MT-CMOS circuits.”).
`
`Mutoh021 similarly teaches a MTCMOS device configured in a gate array
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`with CMOS circuits for low-voltage/high-speed operation composed of a transistor
`
`with a high threshold voltage and a transistor with a low threshold voltage.
`
`EX1013, Mutoh021, ¶0001. Ramus teaches the use of decoupling MOS capacitors,
`
`which were generally widely known and used. EX1011, Ramus, 4:34–5:27;
`
`EX1003, Holberg Decl., ¶¶47-55.
`
`A person of ordinary skill in the art (“POSA”) would have been motivated to
`
`combine the teachings of the prior art to obtain the claimed invention of the ’614
`
`patent. Each of the references discussed in further detail below are in the same
`
`field and describe common circuits (e.g., semiconductor IC devices). Moreover,
`
`Mutoh021’s layout and Ramus’ MOS capacitors were tools in a POSA’s toolbox,
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`used in known ways, for integrated circuit design. EX1003, ¶¶41-55.
`
`Further, a POSA would have understood the predictable benefits of
`
`Mutoh021’s layout to realize circuit design efficiencies, such as reducing wiring
`
`
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`- 2 -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`complexity, reducing resistance between components, decreasing response time of
`
`circuit components, and increased layout pattern density, and be motivated to
`
`combine Mutoh021 with the prior art to achieve low-voltage/high-speed operation.
`
`A POSA would have also understood the predictable benefits of Ramus’
`
`decoupling MOS capacitors to reduce noise and voltage drops in the power supply
`
`lines. A POSA would have therefore been motivated to combine the teachings of
`
`these references to obtain the claimed invention of the ’614 patent. EX1003,
`
`¶¶114-128, 163-171, 204-208.
`
`Accordingly, as explained below, the prior art renders obvious claims 1-5 of
`
`the ’614 patent.
`
`Further, this inter partes review should not be denied under § 314(a) or §
`
`325(d) for at least two reasons. First, this Petition is based on prior art which
`
`recognized the same problem and solution of the ’614 patent—Urano—and was
`
`known to the Patent Owner but never considered by the Examiner since it was
`
`disclosed to the USPTO only after the issue fee had been paid.
`
`Second, the pending district court litigation involving the ’614 patent is in
`
`the early stages and no trial date has been set. EX1029, 01-18-2019 Scheduling
`
`Order, 2; EX1030, 05-14-2019 Scheduling Order, 1-2. Indeed, all dates of the
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`litigation beyond August 2019 are stayed and the district court would likely
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`continue to stay the case upon institution of this proceeding to allow for effective
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`
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`- 3 -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`and efficient resolution of issues. EX1029, 2. Because the parties’ proposed claim
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`constructions have just been presented in litigation, the timing of this petition
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`allows the Board a full opportunity to consider the parties’ positions in relation to
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`the grounds presented in detail below.
`
`II. Mandatory Notices
`
`A. Real parties-in-interest
`
`Petitioner Advanced Micro Devices, Inc. and ATI Technologies ULC are the
`
`real parties-in-interest. ATI Technologies ULC is an indirect, wholly owned
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`subsidiary of Advanced Micro Devices, Inc..
`
`B. Notice of related matters
`
`Aquila asserted the ’614 patent in a district court litigation captioned as
`
`Aquila Innovations Inc. v. Advanced Micro Devices, Inc., Case No. 1:18-cv-00554-
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`LY (W.D. Tex.), filed July 2, 2018.
`
`C. Lead and back-up counsel with service information
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`Lead Counsel: Michael D. Specht (Reg. No. 54,463); 202.772.8756
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`Backup Counsel: Christopher R. O’Brien (Reg. No. 63,208); 202.772.8657
`
`Wenchong Shu (Reg. No. 73,999); 202.772.8656
`
`Michael B. Ray (Reg. No. 33,997); 202.772.8569
`
`Jonathan Tuminaro (Reg. No. 61,327); 202.772.8967
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`- 4 -
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`

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`Address:
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`
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
`
`1100 New York Avenue, N.W., Washington, DC 20005
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`(202) 371-2600 (phone) 202.371.2540 (fax)
`
`AMD consents to service via email at mspecht-
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`PTAB@sternekessler.com, COBrien-PTAB@sternekessler.com, wshu-
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`PTAB@sternekessler.com, mray-PTAB@sternekessler.com, jtuminar-
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`PTAB@sternekessler.com and PTAB@sternekessler.com.
`
`III. Grounds for Standing
`
`AMD certifies that the ’614 patent is eligible for inter partes review and that
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`AMD is not barred or estopped from requesting inter partes review of the ‘614
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`patent.
`
`IV.
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`Identification of Challenge
`
`AMD requests IPR on the grounds listed below. Per 37 C.F.R. § 42.6(c),
`
`copies of the references are filed with this petition. In support, this petition is
`
`accompanied by a Declaration of Douglas Holberg, Ph.D. (EX1003), along with
`
`his curriculum vitae (EX1004). Dr. Holberg’s Declaration explains what the prior
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`art would have conveyed to a POSA.
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`
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`- 5 -
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`

`

`Grounds Challenged Claims
`
`Type
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`References
`
`1
`
`2
`
`3
`
`1-3
`
`1-3
`
`4-5
`
`§103 Urano in view of Mutoh021
`
`§103 Mutoh in view of Mutoh021
`
`§103 Douseki in view of Ramus
`
`Urano, Exhibit 1007 (English translation and Certificate provided as
`
`Exhibits 1008 and 1009), was filed on November 21, 1996 and published on May
`
`5, 1998, before the priority date of the ’614 patent. Thus, Urano is prior art under
`
`at least 35 U.S.C. § 102(a).
`
`Mutoh021, Exhibit 1012 (English translation and Certificate provided as
`
`Exhibits 1013 and 1014), was filed on July 4, 1994 and published on January 19,
`
`1996, more than a year before the priority date of the ’614 patent. Thus, Mutoh21
`
`is prior art under at least 35 U.S.C. § 102(b).
`
`Mutoh, Exhibit 1005, was published in the IEEE Journal of Solid-State
`
`Circuits, Vol. 30 in August 1995, more than a year before the priority date of the
`
`’614 patent. IEEE is a well-known publisher and a POSA would have been able to
`
`locate it exercising reasonable diligence. EX1003, 35. Thus, Mutoh is prior art
`
`under at least 35 U.S.C. §102(b).
`
`
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`- 6 -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`Douseki, Exhibit 1010, was filed on November 2, 1994 and issued on
`
`January 23, 1996, more than a year before the priority date of the ’614 patent.
`
`Thus, Douseki is prior art under at least 35 U.S.C. § 102(b).
`
`Ramus, Exhibit 1011, was filed on April 15, 1996 and issued on May 20,
`
`1997, more than a year before the priority date of the ’614 patent. Thus, Ramus is
`
`prior art under at least 35 U.S.C. § 102(b).
`
`V. The ’614 Patent
`
`A. Technical Background
`
`The ’614 patent relates to a layout for a semiconductor integrated circuit
`
`device including multi-threshold voltage MOS transistors (“MTCMOS”), which is
`
`capable of operating at a lower power supply voltage when active and reduced
`
`leakage current during standby. EX1001, Abstract, 1:7-12. The ’614 patent also
`
`relates to the use of MOS decoupling capacitors to reduce voltage variations and
`
`time delays in MTCMOS devices. Id., Abstract, 4:59-6:9.
`
`As the patent admits, however, MTCMOS devices capable of operating at a
`
`lower power supply voltage when active with reduced leakage current during
`
`standby were well-known in the art. Id., 1:14-32. The ’614 patent explains the
`
`basic components of conventional MTCMOS devices, including: “at least one
`
`logic circuit electrically connected between a virtual power supply line and a
`
`virtual power supply line and comprised of MOS transistors each having a low
`
`
`
`- 7 -
`
`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`threshold voltage and standby power control MOS transistors each having a high
`
`threshold voltage, which are electrically connected between a power supply line
`
`and the virtual power supply line and between a ground line and a virtual ground
`
`line to reduce the leakage current of each MOS transistor during standby.” Id.,
`
`1:33-42.
`
`Similarly, Figure 40 of Urano illustrates an exemplary prior art MTCMOS
`
`gate-array device, including: logic circuit 9 connected to a virtual power supply
`
`line VDDV and a virtual ground line GNDV, the logic circuit 9 having low-
`
`threshold MOS transistors (M11-M14) and high-threshold MOS transistors (M15-
`
`M16) to reduce leakage current during standby. EX1008, ¶¶0010-0013.
`
`
`
`EX1008, Fig. 40.
`
`
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`- 8 -
`
`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`Additional exemplary prior art MTCMOS devices are taught by Mutoh021
`
`(EX1012), and Makino (EX1006). EX1003, ¶37.
`
`Furthermore, various layout designs for semiconductor IC circuit devices,
`
`including gate arrays and standard cell systems, were well-known before 1999.
`
`See, e.g., EX1016, Saigo, Fig. 10 (showing a chip configuration of a gate array
`
`layout); EX1017, Sato, Fig. 4 (showing a gate array chip); EX1027, Smith, Fig. 2
`
`(showing an analog standard cell (ASC) chip layout); EX1018, Massetti, Fig. 2
`
`(showing an analog standard cell (ASC) chip layout). EX1003, ¶¶41-46.
`
`Gate arrays and standard cell systems were also well-known layouts
`
`specifically for MTCMOS devices prior to 1999. The ’614 patent acknowledges
`
`that standard cell systems were a prior art layout technique for manufacturing
`
`MTCMOS devices. EX1001, 1:51-58. Gate array layouts were also widely known.
`
`For example, Urano and Mutoh021 each teach a gate array-type IC compatible
`
`with CMOS circuits for low-voltage/high-speed operation composed of a high
`
`threshold voltage transistor and a low threshold voltage transistor. EX1008,
`
`¶0062; EX1013, ¶0001. EX1003, ¶42.
`
`Further, using decoupling capacitors (also referred to as “bypass capacitors”)
`
`in integrated circuits to mitigate power and ground routing resistance and
`
`inductance was well-known in the art by 1999. Their use was even taught by
`
`textbooks published in the 1980s. See, e.g., EX1019, Horowitz, 554 (“Power-
`
`
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`- 9 -
`
`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`supply current spikes generated by the active pullup output circuitry generally
`
`require liberal use of power-supply bypassing, ideally one 0.1µF capacitor per
`
`chip.”). EX1003, ¶¶47-52.
`
`Using MOS capacitance and/or the PN-junction capacitance within
`
`MOSFETs as capacitors, and specifically decoupling capacitors across the supply
`
`of integrated circuits was also well-known in the art by 1999. Ramus, for example,
`
`teaches an integrated circuit having MOS capacitors across power supply lines.
`
`See EX1011, Abstract, 4:34-5:27. See also, e.g., EX1020, Brown (titled “Mos-
`
`capacitor for integrated circuits”); EX1021, Konishi, Abstract (“A MOS type
`
`semiconductor integrated circuit comprising a C-MOS inverter including P- and N-
`
`channel MOS transistors connected in series between VDD and VSS power supply
`
`terminals …”); EX1022, Tobita, 8:31-33 (“A capacitor of a MOS structure shown
`
`in FIG. 30 (A) is used because the thickness of a dielectric film (capacitor
`
`insulating film) can be reduced.”); EX1023, Draper, 1:9-20, 1:21-25; and EX1024,
`
`Ooishi, 41:59-63. EX1003, ¶¶53-54.
`
`As described in detail below, it was well-known to combine these prior art
`
`concepts into different configurations depending on the need of a particular
`
`application and design considerations.
`
`
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`
`B.
`
`The Alleged Problem in the Prior Art
`
`The ’614 patent asserts that the conventional layout for MTCMOS devices
`
`required long manufacture times and could not implement high-speed logical
`
`operations. EX1001, 1:50-67. The ’614 patent specifically states that conventional
`
`MTCMOS devices adopted a standard cell system layout design, resulting in long
`
`periods of time for manufacturing. And in some cases where current is not
`
`sufficiently high during active mode due to the high threshold voltage of the switch,
`
`“a high-speed logical operation cannot be implemented.” EX1003, ¶56.
`
`C. The Alleged Invention of the ’614 Patent
`
`The purported invention of the ’614 patent is a semiconductor integrated
`
`circuit device—a MTCMOS—having: (1) low-threshold MOS transistors, (2)
`
`high-threshold MOS transistors, (3) a power switch composed of MOS transistors,
`
`(4) input/output circuits, and (5) bypass/decoupling capacitors. EX1001, 2:9-26,
`
`3:7-22. EX1003, ¶57.
`
`To overcome the alleged problem of the prior art, the ’614 patent
`
`implements a “layout of a semiconductor integrated circuit device by a gate array
`
`system” instead of a standard cell system, thus allegedly “shortening a
`
`manufacturing period thereof as compared with the conventional standard cell
`
`system.” EX1001, 2:3-7. Figure 1 of the ’614 patent illustrates the allegedly novel
`
`layout of the MTCMOS comprised of units cells with low-threshold MOS
`
`
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`transistors (red), high-threshold MOS transistors (blue), and a power switch of
`
`MOS transistors (green). Id., 3:7-22.
`
`Array of
`Unit cells
`cells with
`with low-
`low-
`threshold
`threshold
`MOSFETs
`MOSFETs
`Unit cells
`Array of cells
`with high-
`with high-
`threshold
`threshold
`MOSFETs
`MOSFETs
`
`Power switch
`with high-
`threshold
`MOSFETs
`
`EX1001, Fig. 1 (annotated).
`
`
`
`EX1003, ¶58.
`
`Figure 3 shown below illustrates the allegedly novel MTCMOS, including:
`
`(1) unit cells having low threshold voltage MOS transistors to form logic cells 20
`
`connecting between two virtual power supply lines 13 and 14, (2) unit cells having
`
`high threshold voltage MOS transistors to form the DFF (D flip flop) cell
`
`connecting between the two power supply lines 11 and 12, and (3) high threshold
`
`PMOS and NMOS transistors 15, 16, 17, 18 to form the power switch. EX1001,
`
`3:7-45.
`
`
`
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`

`

`Unit cells with high
`threshold MOS
`
`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`Unit cells with low
`threshold MOS
`
`Power
`switch with
`high
`threshold
`MOS
`
`Capacitors
`
`EX1001, Fig. 3 (annotated).
`
`
`
`As shown above in Figure 3, the MTCMOS also includes bypass/decoupling
`
`capacitors 21 and 22 formed between power supply lines and virtual power supply
`
`lines. Thus, according to the ’614 patent, the MTCMOS is allegedly “capable of
`
`restraining variations in the values of voltages applied to a virtual power supply
`
`line and a virtual ground line and reducing a delay time when switching is done
`
`between logic circuits provided within an MTCMOS.” EX1001, 2:6-13. EX1003,
`
`¶60.
`
`But these techniques and components, and the benefits thereof, were known
`
`well before the ’614 patent. EX1003, ¶¶33-55.
`
`
`
`- 13 -
`
`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`
`D.
`
`Summary of the Prosecution History
`
`The ’614 patent was filed on April 1, 1999, and claims priority to a Japanese
`
`application, filed on January 14, 1999. EX1001, Foreign Application Priority
`
`Data.
`
`During prosecution of the ’614 patent, one non-final office action was
`
`issued. The office action contained a § 102 rejection of original claims 4-6 over
`
`Mutoh, a § 103 rejection for original claim 7 over Mutoh, and an objection to
`
`original claims 1-3 and 8. EX1002, ’614 Prosecution History, 80. In response, the
`
`Applicant canceled claims 4-7 and added new claims, which became issued claims
`
`4-7. Claim 1 was amended to overcome the objection. Id., 88-95. A Notice of
`
`Allowance was accordingly issued. Id., 101-105.
`
`The Applicant attempted to withdraw the application from issuance after
`
`paying the issue fee in order to have another reference considered—the Urano
`
`reference. Id., 116. The Applicant’s petition was denied because the petition was
`
`filed too late and the patent issued before a decision could be reached. Id., 122.
`
`Accordingly, the IDS filed by the Applicant with the Urano reference was merely
`
`placed in the file. Urano was thus never considered by the Examiner.
`
`VI. Level of Ordinary Skill in the Art
`
`A person of ordinary skill in the art (“POSA”) at the time of the claimed
`
`invention would have a B.S. degree in Electrical Engineering or an equivalent
`
`
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`- 14 -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`field, as well as at least 3-5 years of academic or industry experience in
`
`semiconductor integrated circuit field, or comparable industry experience.
`
`EX1003, ¶26.
`
`VII. Claim Construction
`
`In an inter partes review, claims are “construed using the same claim
`
`construction standard that would be used to construe the claim in a civil action
`
`under 35 U.S.C. 282(b).” 37 C.F.R. § 42.100(b). If trial is instituted, all claim
`
`terms must be given their ordinary and customary meaning as understood by a
`
`POSA at the time of the alleged invention in light of the specification and the
`
`prosecution history pertaining to the patent. Id.; Phillips v. AWH Corp., 415 F.3d
`
`1303, 1312-1313 (Fed. Cir. 2015) (en banc); see also 83 Fed. Reg. 51,340.
`
`The pending district court litigation is in the early stages with the parties
`
`having just exchanged expert reports regarding claim construction of the following
`
`terms:
`
`(1)
`
`“unit cells” (claims 1 and 4);
`
`(2) “a unit cell array comprised of said first and second unit cells laid in
`
`array form” (claim 1);
`
`(3)
`
`“a power switch” (claims 1, 2, and 3);
`
`(4)
`
`“a power switch disposed around said unit cell array and comprised of
`
`a plurality of third MOS transistors” (claim 1);
`
`
`
`- 15 -
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`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`“a plurality of input/output circuits disposed around said unit cell
`
`(5)
`
`array” (claim 1); and
`
`(6)
`
`“parts of said power switch disposed within said unit cell array”
`
`(claim 3).
`
`All other terms should receive their plain and ordinary meaning. EX1003,
`
`¶68.
`
`The claim constructions presented here are the same as those that the
`
`Petitioner has presented in the co-pending district court action. To the extent that
`
`the Patent Owner argues (or should the Board adopt) that the claim constructions
`
`identified by the Patent Owner in the co-pending district court action should apply
`
`here, the identified references discussed in detail below disclose these limitations
`
`even under those alternative claim constructions. EX1003, ¶69; EX1015, Sec. VI.
`
`“unit cells”
`
`(1)
`The term “unit cells” should be construed as “semiconductor integrated
`
`circuits implemented by a gate array system, cannot be a conventional standard
`
`cell.” EX1003, ¶¶72-83; EX1015, ¶34-44.
`
`Independent claims 1 and 4 each recite “unit cells.” However, the term “unit
`
`cells” is not a commonly used term in the art of semiconductor integrated circuit
`
`design and the ’614 patent does not provide a definition for the term “unit cells.”
`
`EX1003, ¶72; EX1015, ¶34.
`
`
`
`- 16 -
`
`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`MOS transistors are the building blocks of all CMOS integrated circuits.
`
`And the ’614 patent distinguishes conventional standard cell MTCMOS from the
`
`claimed invention that uses “unit cell” MTCMOS. EX1003, ¶74; EX1015, ¶35.
`
`Specifically, the Background of the ’614 patent explains that conventional
`
`MTCMOS circuits implemented a standard cell system “in which layout design is
`
`performed in units of a latch circuit such as a flip-flop circuit comprised of an
`
`inverter circuit, a master circuit and a slave circuit, and a logic circuit.” EX1001,
`
`1:51-55. The Background further notes that since the standard cell system is
`
`implemented by each circuit unit (e.g., a standard cell is employed for each of the
`
`inverter circuit, master circuit, slave circuit, and logic circuit), “the period required
`
`to manufacture the MTCMOS becomes long.” Id., 1:55-58. EX1003, ¶74;
`
`EX1015, ¶35.
`
`The “present invention” of the ’614 patent’s MTCMOS circuit is thus
`
`instead implemented “by a gate array system, thereby shortening a manufacturing
`
`period thereof as compared with the conventional standard cell system.” EX1001,
`
`2:3-7. The ’614 patent explains that “for achieving the” objective of a MTCMOS
`
`gate array system, “unit cells each including PMOS transistors and NMOS
`
`transistors” are used in an array format instead of standard cells. Id., 2:14-26.
`
`Figure 3 illustrates “one example of the unit cells shown in FIG. 1 according to a
`
`configuration of a semiconductor integrated circuit device of the present invention”
`
`
`
`- 17 -
`
`

`

`Petition for Inter Partes Review of
`U.S. Patent No. 6,239,614
`implemented by a gate array system having a shortened manufacturing period as
`
`compared with conventional standard cell systems. Id., 3:8-11, 3:51-54 (“Since the
`
`layout of the MTCMOS 10 can be implemented in accordance with a gate array
`
`system in the present embodiment, a manufacturing period can be shortened as
`
`compared with the conventional standard cell system.”). EX1003, ¶74; EX1015,
`
`¶35.
`
`Therefore, the ’614 patent explains that the claimed invention is
`
`implemented by a gate array system in order to reduce manufacturing time and, as
`
`a POSA would understand, that gate arrays and standard cells are two distinct ways
`
`of designing and fabricating semiconductor circuits. A POSA reading the
`
`specification would understand that “unit cells” as recited in claims 1 and 4 are
`
`semiconductor integrated circuits implemented by a gate array system, and that
`
`they cannot be a conventional standard cell. EX1003, ¶¶74-78; EX1015, ¶35-39.
`
`In the pending litigation, the Patent Owner has proposed a construction of
`
`“logic elements of which a unit cell array is comprised” for the term “unit cells.”
`
`However, this construction fails to provide clarity to the term,