[19]
`United States Patent
`6,140,836
`[11] Patent Number:
`[45] Date of Patent: Oct. 31, 2000
`FuJ 11 et al.
`
`
`
`US006140836A
`
`[54] SELF-TIMED PIPELINED DATAPATH
`SYSTEM AND ASYNCHRONOUS SIGNAL
`CONTROL CIRCUIT
`
`[75]
`
`Inventors: Koji Fujii; Takakuni Douseki, both of
`Tokyo, Japan
`
`[73] Assignee: Nippon Telegraph And Telephone
`Corporation, Tokyo, Japan
`
`[21] Appl. No.: 09/033,850
`
`[22]
`
`Filed:
`
`Mar. 3, 1998
`
`[30]
`
`Foreign Application Priority Data
`
`Mar. 3, 1997
`
`[JP]
`
`Japan .................................... 9—061696
`
`Int. Cl.7 ..................................................... H03K 17/23
`[51]
`[52] US. Cl.
`.............................. 326/35; 326/93; 326/121;
`326/112
`[58] Field of Search .................................. 326/46, 35, 36,
`326/93, 96, 112, 119, 120, 121
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.............................. 326/93
`7/1995 Yetter et a1.
`5,434,520
`1/1996 Douseki et a1.
`.
`5,486,774
`5,583,457 12/1996 Horiguchi et a1.
`...................... 326/121
`1/1997 Douseki ............... 326/119
`5,594,371
`
`............................... 327/333
`5,929,687
`7/1999 Yamauchi
`
`OTHER PUBLICATIONS
`
`“A Fully Asynchronous Digital Signal Processor Using
`Self—Timed Circuits” by Gordon M. Jacobs and Robert W.
`Brodersen, IEEE Journal of Solid—State Circuits, vol. 25,
`No. pp. 1526—1537, Dec. 6, 1990.
`
`A Comparison of CMOS Implementations of an Asynchro-
`nous Circuits Primitive: the C—Element by: Maitham Shams,
`Jo C. Ebergen, Mohamed I. Elmasry, University of Water-
`loo, Waterloo, Ontario, Canada, ISLPED 1996 Monterey
`CA, pp. 1—4.
`“A Study on Multi—threshold—voltage COMS Circuit With
`Asynchronous system”, Fujii et al. Proceedings of the 1997
`IEICE General Conference Mar. 24—27, 1997, Kansai Uni-
`versity, Suita.
`
`Primary Examiner—Michael Tokar
`Assistant Examiner—Don Phu Le
`
`Attorney, Agent, or Firm—Norman N. Kunitz; Venable
`
`[57]
`
`ABSTRACT
`
`A self-timed pipelined datapath system reduces its power
`dissipation by accurately controlling the active and inactive
`states of the multi-threshold CMOS (MT-CMOS) circuit
`used as its combinational circuit. The MT—CMOS circuit
`
`comprises a logic circuit of low-threshold and a power
`control circuit formed of high-threshold transistors for con-
`trolling the power feeding to the logic circuit. The self-timed
`pipelined datapath system comprises: a pipelined datapath
`circuit including a plurality of data processing stages, each
`having a combinational circuit for processing input data and
`a register connected to the input side of the combinational
`circuit; and an asynchronous signal control circuit
`that
`controls data transmission to and from each of the registers
`in the pipelined datapath circuit in response to a request
`signal. The state change of an active state to an inactive state
`of the combinational circuit is performed in consideration of
`the signal propagation time therein, whereby the issue of the
`request signal with respect to the combinational circuit at the
`preceding stage is delayed from the time the request signal
`with respect to the current combinational circuit is issued.
`
`11 Claims, 13 Drawing Sheets
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ASYNCHRONOUS
`[SEW _——_]
`SIGNAL CONTROL
`CIRCUIT................
`
`1
`
`0001
`
`AMD EX1045
`
`US. Patent No. 6,239,614
`
`
`
`i COMEINA-
`TIONAL
`CIRCUIT
`(MT-CMOS
`j CIRCUIT)
`
`i
`
`3
`
`noun.
`CIRCUIT
`3
`(MT-CMOS
`: CIRCUIT)
`
`
`
`AMD EX1045
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 1 0f 13
`
`6,140,836
`
`
`
`................................
`
`IN
`
`COMBINA-
`COMBINA-
`
`
`TIONAL
`TIONAL
`
`
`
`CIRCUIT
`CIRCUIT
`
`
`
`(MT-CMOS
`(MT-CMOS
`
`
`
`CIRCUIT)
`CIRCUIT)
`
`
`
`
`....................................
`
`
`
`ASYNCHRONOUS
`SIGNAL CONTROL
`CIRCUIT ________________ -
`
`II
`:
`.
`
`FIG.1
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 2 0f 13
`
`6,140,836
`
`SET
`
`ZV'
`
`/¢é
`
` s\ s~~‘‘
`
`8T1
`
`“02
`
`EN2
`
`ST2
`
`REQB
`
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`
`SIGNAL
`
`“008551353 ?7
`
`7
`
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`’9"
`
`‘
`SIGNAL
`pnocnssmc 2
`
` EN3
`
`——> TIME
`LAPSE
`
`FIG.2
`
`0003
`
`0003
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 3 0f 13
`
`6,140,836
`
`.................................................................
`
`...............
`
`...................
`
`...................
`
`
`
`................
`
`
`
`................
`
`
`
`
`COMBINA-
`i
`i
`TIONAL
`a
`5
`
`
`CIRCUIT
`'REGIS-'
`
`5
`(MT-CMOS
`TER
`CIRCUIT)
`3
`g
`
`COMBINA-
`TIouRL
`CIRCUIT
`(MT-cues
`CIRCUIT)
`snp*
`
`o
`
`E
`
`
`
`g
`RSYNCHRONOUS
`SIGNAL CONTROL;
`CIRCUIT ................ -
`
`FIG.3
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 4 0f 13
`
`6,140,836
`
`................
`
`5 COMBINA-
`:
`
`s
`TIONAL
`E
`
`IN
`-, CIRCUIT
`'
`5
`;
`(MT-C240?
`
`:
`: CIRCUIT
`t
`:
`E
`5
`SLP*
`I:
`
`
`1
`
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`§
`
`5
`;
`
`'REGIs-;
`
`TER
`g
`
`:
`:
`;
`
`................
`
`COMBINA-
`TIONAL
`CIRCUIT
`(MT-CMOS
`CIRCUIT)
`
`
`
`
`
`
`
`
`
`
`ASYNCHRONOUS
`S IGNAL CONTROL
`
`.
`
`.-.vr
`
`FIG.4
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 5 0f 13
`
`6,140,836
`
`321'
`
`7/
`
`REQi
`
`7
`
`%
`
`7 \
`
`l V
`
`SIGNAL
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`PROCF§§E¥EE gfi
`.7
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`SIGNAL
`
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`
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`
`7
`
`m1
`
`3-1-1
`
`R202
`
`mu
`
`s'r2
`
`REQ3
`
`Exz IW
`
`LAPSE
`
`FIG.5
`
`0006
`
`0006
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 6 0f 13
`
`6,140,836
`
`I
`
`i cousnm-
`5
`TIONAL
`REGIS- - CIRCUIT
`TER
`(MT-CMOS
`CIRCUIT)
`
`:
`;
`'
`g
`3
`
`
`
` E
`
`ASYNCHRONOUS
`SIGNAL CONTROL 5
`3
`_: ...................................................................................... 9.1.3.99?! ________________‘
`
`FIG.6
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 7 0f 13
`
`6,140,836
`
`SET 7
`
`%
`
`.........‘
`SIGNAL\
`PR°C§§§§¥§ E.
`
`........
`
`ENl
`
`REQZ
`
`EN2
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`sn
`
`EN3
`
`7/
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`1
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`‘
`
`‘3‘
`3‘
`SIGNAL
`PR0CE§§I§§HE finSE§§sxne 2
`
`0008
`
`0008
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 8 0f 13
`
`6,140,836
`
`
`
`0009
`
`0009
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 9 0f 13
`
`6,140,836
`
`
`
`FIG.9A
`
`PRIOR ART
`
`
`
`FIG. 93
`
`PRIOR ART
`
`0010
`
`0010
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 10 0f 13
`
`6,140,836
`
`E]
`
`D D E
`
`]
`
`Cl
`
`E!
`
`DDDUDDDDDIDDD
`
`El
`
`E]
`
`D E
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`]
`
`E]
`
`D E
`
`] D
`
`PRIOR ART
`
`0011
`
`0011
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 11 0f 13
`
`6,140,836
`
`SLP*
`
`COMBINATIONAL
`CIRCUIT
`(DYNAMIC
`CIRCUIT)
`SLP"
`
`ASYNCHRONOUS
`SIGNAL CONTROL
`CIRCUIT
`
`COMBINATIONAL
`CIRCUIT
`(DYNAMIC
`CIRCUIT)
`
`REGISTER
`
`FIG. 10
`(PRIOR ART)
`
`0012
`
`0012
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 12 0f 13
`
`6,140,836
`
`11
`
`}YA2
`
`FIG.11A
`
`
`
`0013
`
`0013
`
`

`

`US. Patent
`
`Oct. 31, 2000
`
`Sheet 13 0f 13
`
`6,140,836
`
`OUT
`REGG
`
`
`
`
`
`COMBINATIONAL
`COMBINATIONAL
`CIRCUIT
`CIRCUIT
`
`
`
`
`
`REGISTER
`
`REGISTER
` REGISTER
`(STATIC
`(STATIC
`
`
`
`
`CIRCUIT)
`CIRCUIT)
`
`
`
`SLP*
`SLP*
`
`
`
`
`12"
`
`
`
`ASYNCHRONOUS
`SIGNAL CONTROL
`CIRCUIT
`
`FIG. 12
`(PRIOR ART)
`
`0014
`
`0014
`
`

`

`1
`SELF-TIMED PIPELINED DATAPATH
`SYSTEM AND ASYNCHRONOUS SIGNAL
`CONTROL CIRCUIT
`
`6,140,836
`
`2
`
`the high-
`SLP* is “1” (meaning a high level voltage),
`threshold MOS transistors in the circuit 2H and in the circuit
`2L are on, the virtual power rail VDDV and the power rail
`VDD are thereby electrically connected, and the virtual
`ground rail GNDV and the ground rail GND are also
`connected respectively, so that the logic circuit 1 is supplied
`with power and thereby activated. Conversely, when the
`sleep signal SLP is “1”, and the inverted sleep signal SLP*
`is “0”, the high-threshold MOS transistors in the circuit 2H
`and the circuit 2L are both off, so that the logic circuit 1
`cannot be supplied with electric power, and is put in an
`inactive state (hereinafter it may referred to just as “sleeping
`state”).
`FIG. 9B shows an example of the MT—CMOS circuit,
`which is equivalent to the MT—CMOS circuit of FIG. 9A but
`without the circuit 2L, and FIG. 9C shows an example of the
`MT—CMOS circuit, which is equivalent to the MT—CMOS
`circuit of FIG. 9A but without the circuit 2H. In the former
`
`MT—CMOS circuit, the logic circuit 1 is controlled to be
`activated or set to the sleeping state only by the sleep signal
`SLP, whereas in the latter, the logic circuit 1 is controlled
`only by the inverted sleep signal SLP*.
`On an IC chip as shown in FIG. 9D, the MT—CMOS circuit
`of FIG. 9A is preinstalled in the respective blocks 3 through
`6, wherein a circuit block for controlling the power supply
`7 generates and sends SLP and/or SLP* signals to each of
`these blocks 3 through 6 independently. Thus, the activated
`state and sleeping state of each of the blocks 3 through 6 are
`controlled independently.
`Note that the power source control block 7 may generate
`only one of the SLP and SLP* signals, and the other signal
`may be generated within each of the blocks 3 through 6 by
`way of an inverter. MT—CMOS circuits respectively shown
`in FIGS. 9B and 9C may be used for the blocks 3 through
`6. Further,
`the SLP and SLP* signals may be supplied
`externally.
`In each block 3 through 6, when the logic circuit 1 is in
`the sleeping state, the high-threshold MOS transistors in the
`respective circuit 2H and the circuit 2L are off, the leakage
`current can be reduced to the level of the high-threshold
`CMOS circuit, and a reduction of power dissipation is
`thereby enabled. Further, since the logic circuit 1 is config-
`ured by low-threshold MOS transistors only, it performs a
`high-speed logic operation in its active state even at low
`supply voltages. In fact, the MT—CMOS circuit features its
`high-speed operation and its low-level leakage current at
`low supply voltages. In a conventional CMOS circuit, the
`leakage current is increased if, for the purpose of acceler-
`ating the operating speed thereof, the threshold voltage of
`the MOS transistors is lowered in compliance with the
`reduction of the supply voltage, whereas this does not
`happen to the MT—CMOS circuit.
`As mentioned heretofore, it is ensured that the MT—CMOS
`circuit is effective for reducing the static power dissipation
`in connection with the low supply voltage. However, basi-
`cally it is not a circuit for controlling the conductive and/or
`non-conductive states of the high-threshold MOS transistors
`therein in accordance with the data flowing order. For this
`reason, even if it is applied to a pipelined datapath circuit, as
`long as the high-threshold MOS transistors are on, there still
`occurs a leakage current even when there is not much data
`flowing therein, and the static power dissipation is thereby
`increased.
`
`SUMMARY OF THE INVENTION
`
`The present invention has been achieved to solve the
`above-described problem and an object of the present inven-
`
`This application is based on Patent Application No.
`61,696/1997 filed Mar. 3, 1997 in Japan,
`the content of
`which is incorporated hereinto by reference.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`
`The present invention relates to a technique in which a
`multi-threshold CMOS circuit (hereinafter referred to just as
`a “MT-CMOS circuit”) is applied to a self-timed pipelined
`datapath system, wherein the MT—CMOS circuit comprises
`a logic circuit portion formed by a low-threshold CMOS
`circuit and a power source control circuit composed of
`high-threshold MOS transistors for supplying electric power
`to the logic circuit portion, and more particularly to a
`technique in which the high-threshold MOS transistors
`composing the power source control circuit
`in the
`MT—CMOS circuit are accurately controlled to be on and off
`along the data flowing order in response to asynchronous
`signals, thereby to reduce the power dissipation as a whole.
`2. Description of the Prior Art
`Recently, in view of a magnification of the information to
`be transmitted and received by portable communication
`apparatuses,
`the LSIs installed on them dissipate more
`power. To address this problem, various techniques for
`lowering power dissipation have been researched and devel-
`oped.
`Conventionally, an improvement of operating speed of a
`circuit at a low supply voltage region has been made by a
`low-threshold CMOS circuit, and a reduction of leakage
`current in its inactive state has been progressed by high-
`threshold MOS transistors, whereby a MT—CMOS circuit as
`a static CMOS circuit capable of realizing both the high-
`speed operation and low power dissipation has been pro-
`posed (S. Mutoh, T. Douseki, T. Aoki, and J. Yamada,
`“1V—high-speed digital circuit
`technology with 0.5E m
`multi-threshold CMOS”, in Proc. IEEE 1993 International
`ASIC Conf., pp. 186—189,1993. Or, US. Pat. No. 5,486,
`774.)
`FIG. 9A shows a configuration of a MT—CMOS circuit. In
`the figure, reference numeral 1 denotes a logic circuit
`portion (hereinafter it may be referred to just as “logic
`circuit”) formed by a low-threshold CMOS circuit, to which
`electric power is supplied from a virtual power rail VDDV
`and a virtual ground rail GNDV. As shown in FIG. 9A, the
`logic circuit 1 includes a NAND gate composed of low-
`threshold pMOS transistors MP1, MP2,
`low-threshold
`nMOS transistors MN1 and MN2, and an inverter composed
`of a low-threshold pMOS transistor MP3 and a low-
`threshold nMOS transistor MN3. 2H denotes a circuit for
`
`controlling the voltage at the virtual power rail, which is
`composed of high-threshold pMOS transistors MP4 and
`MP5, whose sources are connected to the power rail VDD,
`whose drains are connected to the virtual power rail VDDV,
`and whose gates are connected to a sleep signal SLP,
`respectively. Further, 2L denotes a circuit for controlling the
`voltage at the virtual ground rail, which is composed of
`high-threshold nMOS transistors MN4 and MN5, whose
`sources are connected to the ground rail GND, whose drains
`are connected to the virtual ground rail GNDV, and whose
`gates are connected to an inverted sleep signal SLP*
`(inverted SLP signal), respectively.
`In the MT—CMOS circuit, when the sleep signal SLP is
`“0”, (meaning a low level voltage), and its inverted signal
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
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`35
`
`40
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`45
`
`50
`
`55
`
`60
`
`65
`
`0015
`
`0015
`
`

`

`6,140,836
`
`3
`tion is to provide a system which controls to make operable
`only the circuit which is actually in an active state, and
`reduce the power dissipation in the circuit where no data is
`being processed when the MT—CMOS circuit is applied to a
`pipelined datapath circuit.
`In order to solve the problems aforementioned, a self-
`timed pipelined datapath system according to the first
`embodiment of the present invention is constructed such that
`it comprises:
`a pipelined datapath circuit including a plurality of data
`processing stages, each having a combinational circuit for
`processing input data, and a register connected to the input
`side of the combinational circuit; and an asynchronous
`signal control circuit that controls data transmission to and
`from each of the registers in the pipelined datapath circuit in
`response to a request signal; wherein the combinational
`circuit in each of the plurality of data processing stages is
`composed of a multi-threshold CMOS circuit, with the
`multi-threshold CMOS circuit further comprising, a logic
`circuit portion configured by a low-threshold CMOS circuit,
`and a power control circuit portion, which is configured by
`a plurality of high-threshold MOS transistors and controls
`power feeding with respect to the logic circuit portion; and
`wherein the asynchronous signal control circuit comprises a
`signal generating means for controlling active and inactive
`states of each of the combinational circuits in response to a
`request signal.
`A self-timed pipelined datapath system according to the
`second embodiment of the present invention is constructed
`such that it comprises: a pipelined datapath circuit including
`a plurality of data processing stages, each having a combi-
`national circuit for processing input data, and a register
`connected to the input side of the combinational circuit; and
`an asynchronous signal control circuit that controls data
`transmission to and from each of the registers in the pipe-
`lined datapath circuit
`in response to a request signal;
`wherein the combinational circuit in each of the plurality of
`data processing stages is composed of a multi-threshold
`CMOS circuit, with the multi-threshold CMOS circuit fur-
`ther comprising, a logic circuit portion configured by a
`low-threshold CMOS circuit, and a power control circuit
`portion, which is configured by a plurality of high-threshold
`MOS transistors and controls power feeding with respect to
`the logic circuit portion; and wherein the asynchronous
`signal control circuit comprises: a plurality of monitoring
`circuits, each of which delays for a predetermined period of
`time a data write enable signal generated, in response to a
`request signal, to be applied to the register preceding the
`current combinational circuit, and issues another request
`signal with respect to the register succeeding the current
`combinational circuit, and also finishes the request signal
`based on the issue of the another request signal; and a
`plurality of signal generating means each for generating an
`activation signal for controlling the current combinational
`circuit to put in an active or inactive state in response to a
`request signal, but irrespective of an issue of the write enable
`signal with respect to the register preceding the current
`combinational circuit.
`
`A self-timed pipelined datapath system according to the
`third embodiment of the present
`invention based on a
`two-phase handshaking protocol is constructed such that it
`comprises: a pipelined datapath circuit including a plurality
`of data processing stages, each having, a combinational
`circuit for processing input data, and a register connected to
`the input side of the combinational circuit, with the register
`being composed of a double edge-triggered D flip-flop, and
`an asynchronous signal control circuit that controls data
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`transmission to and from each of the registers in said
`pipelined datapath circuit in response to a request signal;
`wherein the combinational circuit in each of said plurality of
`data processing stages is composed of a multi-threshold
`CMOS circuit, with the multi-threshold CMOS circuit fur-
`ther comprising a logic circuit portion configured by a
`low-threshold CMOS circuit, and a power control circuit
`portion, which is configured by a plurality of high-threshold
`MOS transistors and controls power feeding with respect to
`the logic circuit portion; and wherein the asynchronous
`signal control circuit comprises: a plurality of delay circuits,
`each of which delays for a predetermined period of time a
`state change of a data write enable signal generated,
`in
`response to a request signal, to be applied to the register
`preceding the current combinational circuit, and generates a
`state change of another request signal with respect to the
`register succeeding the current combinational circuit; and a
`plurality of signal generating means each for issuing an
`activation signal for controlling the current combinational
`circuit, to put in an active or inactive state, in accordance
`with the state change of the data write enable signal gener-
`ated in response to the request signal with respect to the
`register preceding the current combinational circuit, and
`finishes said activation signal in response to the state change
`of the data write enable signal generated in response to the
`request signal with respect to the register succeeding the
`current combinational circuit.
`
`As is explained above, since the active and inactive states
`of the combinational circuits are controlled in accordance
`
`with the data flowing order, even in a case that data to be
`processed are sent intermittently, the static leakage current
`caused by low-threshold MOS transistors in the active state
`thereof is reduced, and thereby the power dissipation can be
`reduced. Further, since only the circuits to be operated are
`activated, even though a mapping of the active and inactive
`states in the entire circuit is not planned beforehand at its
`designing state, effective power dissipation can be per-
`formed.
`
`The above and other object, effects, features and advan-
`tages of the present invention will become more apparent
`from the following description of embodiments thereof
`taken in conjunction with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a circuit diagram showing a self-timed pipelined
`datapath system according to a first embodiment of the
`present invention.
`FIG. 2 is a timing chart for the operation of an asynchro-
`nous signal control circuit of FIG. 1.
`FIG. 3 is a circuit diagram showing a modification of the
`self-timed pipelined datapath system of the first embodi-
`ment.
`
`FIG. 4 is a circuit diagram showing a self-timed pipelined
`datapath system according to a second embodiment of the
`present invention.
`FIG. 5 is timing chart for the operation of the asynchro-
`nous signal control circuit of FIG. 4.
`FIG. 6 is a circuit diagram showing a self-timed pipelined
`datapath system according to a third embodiment of the
`present invention.
`FIG. 7 is a timing chart for the operation of the asyn-
`chronous signal control circuit of FIG. 6.
`FIG. 8 is a circuit diagram showing a double edge-
`triggered flip-flop.
`FIGS. 9A through 9C are circuit diagrams respectively
`showing the MT—CMOS circuit, and FIG. 9D is an explana-
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`tory view of a case in which the MT-CMOS circuit
`preinstalled in an IC.
`FIG. 10 is a circuit diagram showing a self-timed pipe-
`lined datapath system using a dynamic logic circuit therein
`as a combinational circuit.
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`FIG. 11A is a symbolic diagram of the C-element, FIG.
`11B is a circuit diagram of the C-element, and FIG. 11C is
`an explanatory view of a truth table of the C-element; and
`FIG. 12 is a circuit diagram showing a self-timed pipe-
`lined datapath system based on the two-phase handshaking
`protocol using s static circuit as the combinational circuit.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`[First Embodiment]
`FIG. 1 is a circuit diagram showing a configuration of a
`self-timed pipelined datapath system according to the first
`embodiment of the present invention. Reference numerals
`11A and 12A denote combinational circuits both adopting
`the MT-CMOS circuit shown in FIG. 9A, and numeral 13A
`denotes an asynchronous signal control circuit for control-
`ling the data transmission in the combinational circuits 11A
`and 12A. Here, a datapath circuit for activating a two-stage
`pipeline operation is shown as an example. However, the
`number of stages to be pipelined is not limited to only two.
`In the asynchronous signal control circuit 13A, reference
`characters REQi, REQ2 and REQ3 denote request signals
`respectively for pipeline control operation, EN1 through
`EN3 denote data write enable signals to be applied to
`registers REG1 through REG3 respectively, and ST1 and
`ST2 denote activation signals respectively for controlling
`the active and/or inactive (sleeping) states of the combina-
`tional circuits 11A and 12A. Here, the signals ST1 and ST2
`are inputted to the combinational circuits 11A and 12A
`respectively as an inverted sleep signal SLP*. The sleep
`signal SLP is generated by inverting the signal SLP* within
`the combinational circuits 11A and 12A.
`
`Registers REG1 through REG3 are formed by a series of
`D flip-flops for storing the data inputted to and/or outputted
`from the combinational circuits 11A and 12A respectively.
`Reference numeral 131 denotes a monitoring circuit for
`monitoring the operation of the first-stage combinational
`circuit 11A, which is composed of a delay circuit DL1, a
`NAND circuit NAND1 and an inverter INV1. By this
`monitoring circuit, the second request signal REQ2 is issued
`with respect to the second-stage combinational circuit 12A
`after the time to be delayed at the delay circuit DL1 has
`lapsed from the moment that the write enable signal EN1
`was issued, in other words, the “0” state thereof was changed
`to the “1” state. Note that the wording “issue” means a state
`change of any signal from “0” to “1” throughout the speci-
`fication. The time to be delayed at the delay circuit DL1 is
`predetermined in such a manner as to be longer than the
`propagation delay time within the combinational circuit
`11A. The request signal REQ2 finishes in accordance with
`the completion of the activation signal ST1 (namely that the
`“1” state of the ST1 signal is changed to the “0” state). Note
`that the wording “finish” or “completion” means a state
`change of any signal from “1” to “0” throughout the speci-
`fication.
`
`Reference numeral 132 denotes a monitoring circuit for
`monitoring the operation of second-stage combinational
`circuit 12A, which is composed of a delay circuit DL2, a
`NAND circuit NAND2 and an inverter INV2, and performs
`a function just like the first monitoring circuit 131.
`Reference characters NOR1 through NOR5 denote NOR
`gates, and C1 through C5 denote C-elements, each config-
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`ured as shown in FIG. 11B. Namely, C-elements are respec-
`tively composed of pMOS transistors MP11 through MP16,
`and nMOS transistors MN11 through MN16. Considering
`the C-element, as shown in the truth table of FIG. 11C, when
`the two input data A1 and A2 are coincided to be “0”, then
`“0” is outputted as the data Y, while “1” is outputted when
`coincided to be “1”. If they do not coincide,
`then the
`previous data is maintained to be outputted.
`It is to be noted that the C-element is disclosed in the
`
`following documents; G. M. Jacob et al. “A Fully Asyn-
`chronous Digital Signal Processor Using Self-Timed Cir-
`cuits” IEEE Journal on Solid State Circuits, vol. 25, No. 6,
`December 1990, pp. 1526—1537; and M. Shames et al. “A
`Comparison of CMOS Implementations of an Asynchronous
`Circuits Primitive: the C-element” International Symposium
`on Low Power Electron Devices Monterey Calif. 1996, pp.
`93—96.
`
`Here, in order to facilitate the understanding of the present
`embodiment, a conventionally disclosed self-timed pipe-
`lined datapath system is explained, taking up the case shown
`in FIG. 10 in which dynamic combinational circuits 11‘ and
`12' are adopted. In the same figure, reference numeral 13' is
`an asynchronous signal control circuit. The members same
`as those in FIG. 1 have the same numbers.
`
`In the dynamic combinational circuit 11‘ (and also to the
`combinational circuit 12'), MP21 through MP23 are pMOS
`transistors for a precharging operation, MN21 through
`MN23 are nMOS transistors for a discharging operation,
`INV31 and INV32 are inverters, and reference numerals 14
`through 16 are pull-down networks each composed of
`nMOS transistors. The dynamic combinational circuit 11‘ is
`formed by a DOMINO logic circuit, and includes a moni-
`toring circuit 17 for monitoring the completion of the
`combinational circuit 11‘ itself. Since the transistors MP21
`
`through MP23 are on when the activation signal ST1 is “0”,
`and the dynamic circuit is put in a precharging state, so that
`the request signal REQ2 outputted from this monitoring
`circuit 17 is turned to “0”.
`
`On the other hand, when the activation signal ST1
`becomes “1”, and the transistors MN21 through MN23 are
`on to start logic operation (sampling operation), the request
`signal REQ2 is turned to “1” after a predetermined time
`lapse. The timing for converting the request signal REQ2
`into “1” is determined in such a manner that the logic circuit
`16 in the monitoring circuit 17 raises a signal to flag the
`completion of logic operation in the combinational circuit
`11‘.
`
`In this manner, the request signal REQ2 with respect to
`the succeeding combinational circuit 12' is issued after a
`predetermined time lapse corresponding to the propagation
`delay time of the current combinational circuit 11‘ from the
`issue of the activation signal ST1, and finishes in accordance
`with the completion of the activation signal ST1.
`In the first embodiment of the present invention, a moni-
`toring circuit 131 is provided as shown in FIG. 1, so as to
`readily generate the request signal REQ2 that satisfies the
`above condition. In the same manner, the monitoring circuit
`132 is provided for generating the request signal REQ3.
`The operation of this embodiment
`is now explained
`referring to FIG. 2.
`First, a SET signal is issued to put the asynchronous signal
`control circuit 13A in an active state. Then, in a state that all
`the data to be inputted to the register REG1 are ready, a
`request signal REQ1 is issued from outside. As the result, a
`write enable signal EN1 to be applied to the first-stage
`register (hereinafter it may be referred to just as “first
`register”) REG1, and an activation signal ST1 with respect
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`to the first-stage combinational circuit (hereinafter it may
`referred to just as “first combinational circuit”) 11A are
`issued one after the other. Further, when the activation signal
`ST1 is issued, the first combinational circuit 11A is put in an
`active state (meaning that the signal SLP is set to “0”, and
`the signal SLP* is set
`to “1”, and a logic processing
`operation is performed to the data received from the first
`register REG1.
`Next, when a period of time which is longer than the
`propagation delay time in the first combinational circuit 11A
`has passed after the moment that the activation signal ST1
`was issued, the monitoring circuit 131 issues a request signal
`REQ2 with respect to the second combinational circuit 12A.
`In accordance with the issue of the request signal REQ2,
`a write enable signal EN2 to be applied to the second-stage
`register (hereinafter it may be referred to just as “second
`register”) REG2, and an activation signal ST2 to be applied
`to the second-stage combinational circuit (hereinafter
`referred to just as “second combinational circuit”) 12A are
`issued one after the other. Thereafter, due to the fact that the
`write enable signal EN2 has been issued, the data processed
`in the first combinational circuit 11A is stored in the second
`
`register REG2, and the activation signal ST1 to be applied
`to the first combinational circuit 11A finishes, and thereafter
`the second request signal REQ2 with respect to the second
`combinational circuit 12A also finishes. Due to the comple-
`tion of the request signal REQ2, the write enable signal EN2
`is also completed.
`Here, due to the completion of the activation signal ST1,
`the signal SLP to the first combinational circuit 11A is set to
`“1”, and the signal SLP* is set to “0”, so that the combi-
`national circuit 11A is put in an inactive state. On the other
`hand, because of the issue of the activation signal ST2, the
`signal SLP to the second combinational circuit 12A is set to
`“0”, and the signal SLP* is set to “1”, so that the combi-
`national circuit 12A is put in an active state, so as to process
`the data outputted from the second register REG2. In other
`words, an active state is shifted from the first combinational
`circuit 11A to the second combinational circuit 12A.
`
`Next, when a period of time which is longer than the
`propagation delay time in the second combinational circuit
`12A has passed after the moment that the activation signal
`ST2 was issued, the monitoring circuit 132 issues a request
`signal REQ3 with respect
`to the third-stage register
`(hereinafter it may referred to just as “third register”) REG3.
`In accordance with the issue of the request signal REQ3, a
`write enable signal EN3 to be applied to the third-stage
`register REG3 (hereinafter it may be referred to just as “third
`register) is issued, and the data processed in the second
`combinational circuit 12A is stored in the third register
`REG3. Further, due to the issue of the write enable signal
`EN3, the activation signal ST2 to be applied to the second
`combinational circuit 12A finishes, so that the second com-
`binational circuit 12A is put in an inactive state, and there-
`after the request signal REQ3 with respect
`to the third
`register REG3 also finishes. Due to the completion of the
`request signal REQ3, the write enable signal EN3 is also
`completed.
`In this way, in accordance with the completion of the
`request signal REQ3, a series of pipelining operation is
`completed. Note that after the completion of the request
`signal REQi from outside, the asynchronous signal control
`circuit is put in a waiting state for another request signal.
`As explained heretofore, the combinational circuits 11A
`and 12A are activated only when the respective registers
`thereof receive data and the data are need to be processed.
`Otherwise, they are put in an inactive state. In the inactive
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`state, a static leakage current is suppressed by the circuits for
`controlling power supply 2H and 2L, which are composed of
`high-threshold MOS transistors in the MT-CMOS circuits of
`the respective combinational circuits 11A and 12A. For this
`reason, power dissipation in the pipelined circuit for pro-
`cessing intermittently received data is greatly reduced.
`FIG. 3 shows a modified embodiment of the above-
`
`explained configuration. The pipelined datapath circuit of
`this type adopts an asynchronous signal control circuit 13B
`(same as the asynchronous signal control circuit 13' in FIG.
`10), wherein monitoring circuits (not shown) equivalent to
`the circuits 131 and 132 disclosed