6,119,250
`[11] Patent Number:
`[19]
`United States Patent
`
`Nishimura et al.
`[45] Date of Patent:
`Sep. 12, 2000
`
`US006119250A
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`
`[75]
`
`Inventors: Kazuko Nishimura, Kyoto; Hironori
`Akamatsu, Osaka; Akira Matsuzawa,
`KYOtO; Mitsuyasu Ohta, Osaka, all Of
`Japan
`
`_
`_
`_
`.
`[73] Ass1gnee: Matsushlta Electrlc Industrlal C0.,
`Ltd" Osaka, Japan
`
`I21] APP1~ N03 09/083,389
`22
`F1 d.
`Rd
`22 1998
`-
`.
`1 e
`’
`ay
`Related US. Application Data
`
`[
`
`]
`
`[63] Continuation of application No. 08/888,920, Jul. 7, 1997,
`Pat. No. 5,978,948.
`.
`.
`.
`.
`.
`Forelgn Appllcatlon Pr10r1ty Data
`[30]
`
`8—175304
`May 7, 1996
`[JP]
`Japan .....
`May 23, 1997
`[JP]
`Japan .................................... 9—133369
`n.
`.
`.....................................................
`[51]
`I t (:17
`G11C 29/00
`[52] us. Cl.
`............................................. 714/718; 365/201
`[58] Fleld 0f Search """""""714/736733 771337;?5/722é’
`’
`’
`’
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.................... 365/189.1
`6/1997 Furutanu et al.
`5,636,163
`FOREIGN PATENT DOCUMENTS
`
`$132;
`2392:2432
`—
`2/1992
`04055778
`6/1994
`06160487
`06334010 12/1994
`
`japan‘
`apan .
`Japan .
`Japan .
`Japan .
`
`07038417
`7—38417
`
`2/1995
`2/1995
`
`Japan .
`Japan .
`
`OTHER PUBLICATIONS
`Y. Matsuya, et al., “1V, 10MHZ High—Speed Digital Circuit
`Technology With Multi—Threshold CMOS”, Technical
`ReportofIEICE,ICH)93—107,pp.23—27,1993—10
`C.Q. Tong, et al., “IDDQ Testing in Low Power Supply
`CMOS Circuits”, Proc. of IEEE 1996 Custom Integrated
`Circuits Conference, pp. 467—470, 1996.
`T. Kuroda, “A High—Speed Low Power 0.3 pm CMOS Gate
`’
`Array With Variable Threshold Voltage (VT) Scheme” Proc.
`of IEEE 1996 Custom Integrated Circuits Conference, pp.
`53—56> 1996'
`T. Kuroda, et al., A 0.9V 150 HMZ 10mW 4mm2 2—D
`discrete COSine Transform Core Processor With Vari-
`able—Threshold—voltage Scheme, Proc. of 1996 IEEE Inter-
`national Sold—State Circuits Conference, pp. 166—167,
`1 996.
`
`Primary Examiner—Hoa T. Nguyen
`Attorney, Agent, or Firm—McDermott, Will & Emery
`[57]
`ABSTRACT
`A test-target circuit is constructed of circuit blocks each
`comprising low-Vth MOS transistors including address
`buffers and a timing generator. A test enable signal for
`indication of a test, an operation selection signal for indi-
`cation of an operation, and a block selection signal used to
`select a desired circuit block are provided. A high-Vth
`NMOS and a high-Vth PMOS transistor are provided in
`order to provide to a test circuit one of detected currents of
`the circuit blocks that was selected by placing a block
`selection signal and the test enable signal in the state of
`HIGH'
`
`11 Claims, 19 Drawing Sheets
`
`VREF
`
`TE
`
`/0P
`
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`REGISTER
`CIRCUIT
`
`TEST
`CIRCUIT
`
`:TEST-TARGET:
`CIRCUIT
`
`I
`'
`
`SCAN
`REGISTER
`
`
`13n ““““““
`F
`
`161 ————————————
`<—————
`
`250
`
`240
`
`GND 220A
`
`210
`
`0001
`
`AMD EX1044
`
`US. Patent No. 6,239,614
`
`AMD EX1044
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 1 0f 19
`
`6,119,250
`
`Fig. 1
`
`PRIOR ART
`
`—1 EA —| 6‘ HVth-Tr
`
`p CHANNEL
`
`n CHANNEL
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Sep.12,2000
`
`SheetZ 0f19
`
`6,119,250
`
`emme
`
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`

`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 3 0f 19
`
`6,119,250
`
`Fig. 3
`
`16
`
`13(TESTER)
`
`STORAGE
`
`DEVICE
`
`DISPLAY
`
`DEVICE
`
`”TIME
`
`TER
`
`JUDGING
`
`17
`
` 18
`CIRCUITI“
`
`
`
`
`SEMICONDUCTOR
`
`INTEGRATED CIRCUIT
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 4 0f 19
`
`6,119,250
`
`Fig. 4
`
`START
`
`STII
`
`ST12
`
`PLACE TEST SIGNAL
`
`IN ON STATE
`
`MEASURE ELECTRIC
`
`CURRENT
`
`NO
`
`ST13
`
`///,r”
`
`YES
`
`JUDGEMENT 0F
`
`JUDGEMENT 0F
`
`REJECTION
`
`ACCEPTANCE
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet 5 0f 19
`
`6,119,250
`
`
`
`FHDQMHQ0H604
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`

`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 6 0f 19
`
`6,119,250
`
`Fig.6
`
`START
`
`ST21
`
`ST22
`
`
`
`PLACE TEST SIGNAL SIGNIFYING
`
`
`
`TEST-TARGET LOGIC BLOCK
`
`
`
`SUBSET IN ON STATE
`
`MEASURE TARGET LOGIC BLOCK
`
`SUBSETS ELECTRIC CURRENT
`
`NO
`
`ST23
`
`YES
`
`JUDGEMENT OF
`
`JUDGEMENT OF
`
`REJECTION
`
`ACCEPTANCE
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet7 0f19
`
`6,119,250
`
`Aomhzoomacs—mee-
`
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`

`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet 8 0f 19
`
`6,119,250
`
` H
`
`0009
`
`0009
`
`

`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 9 0f 19
`
`6,119,250
`
`Fig. 9
`
`STATE CONTROL
`
`SIGNAL (MODE)
`
`
`NORMAL CONTROL
`SIGNAL
`
`
`42
`
`STATE CONTROL
`
`UNIT
`
`HVth-Tr
`CONTEOL SIGNALAT
`(
`1
`ON)
`
`OO1O
`
`0010
`
`

`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet 10 0f 19
`
`6,119,250
`
`Fig.10
`
`START
`
`
`
`CREATE NETLIST AS PARTIAL CIRCUIT
`
`
`DESCRIPTION FOR TEST-TARGET LOGIC
`
`CIRCUIT GROUP
`
`GENERATE TEST SEQUENCE FOR
`
`CREATED NETLIST
`
`ST31
`
`ST32
`
`ST33
`
`ADD TO GENERATED TEST
`
`
`
`
`
`SEQUENCE TO CONTROL STATE
`
`
`CONTROL UNIT
`
`END
`
`OO11
`
`0011
`
`

`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 11 0f 19
`
`6,119,250
`
`Fig.11
`
`7O
`
`
`
`INPUT SEQUENCE
`
`
`VALUE STORAGE
`
`
`
`EXPECTED
`
`DEVICE
`
`STORAGE DEVICE
`
`
`
`
` JUDGING
`
`DISPLAY UNIT
`
`CIRCUIT
`
`SEQUENCE INPUT
`
`DEVICE
`
`
`
`
`SEMICONDUCTOR
`
`INTEGRATED
`
`CIRCUIT
`
`0012
`
`0012
`
`

`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet 12 0f 19
`
`6,119,250
`
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`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 13 0f 19
`
`6,119,250
`
`Fig. 13
`
`’ 60
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`

`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet 14 0f 19
`
`6,119,250
`
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`
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`US. Patent
`
`Sep. 12, 2000
`
`Sheetls 0f19
`
`6,119,250
`
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`

`US. Patent
`
`Sep. 12,2000
`
`Sheet 16 0f 19
`
`6,119,250
`
`Fig.16
`
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`
`FIRST
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`

`US. Patent
`
`Sep. 12, 2000
`
`Sheet 17 0f 19
`
`6,119,250
`
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`US. Patent
`
`Sep.12,2000
`
`Sheet 19 0f 19
`
`6,119,250
`
`Fig.19
`
` SPARE
`
`MEMORY
`BLOCK(MY)
`
`SW3Y
`
`THPBY
`
`- GND
`
`0020
`
`0020
`
`
`

`

`6,119,250
`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`
`This application is a continuation of Ser. No. 08,888,920
`filed Jul. 7, 1997 now US. Pat. No. 5,978,948.
`BACKGROUND OF THE INVENTION
`
`The invention relates to semiconductor integrated circuits
`that have a circuit for use in self-testing and self-fault-
`restoring.
`There have been strong demands for low-power semicon-
`ductor integrated circuits for achieving reductions in the
`dimensions of semiconductor devices for improving the
`level of integration of semiconductor devices. The reduction
`of power supply voltage is an effective way of implementing
`semiconductor integrated circuits with low power consump-
`tion. The problem is that reductions in power supply voltage
`result in slow transistors. Asolution to this problem has been
`proposed. An MT—CMOS integrated circuit, as one of semi-
`conductor integrated circuits formed by CMOS integrated
`circuits, has been known in the art.
`In the MT—CMOS
`integrated circuit,
`two types of MOS transistors are
`employed, namely MOS transistors having a low threshold
`voltage (Vth), called low-threshold MOS transistors and
`MOS transistors having a high Vth, called high-threshold
`MOS transistors.
`
`An MT—CMOS integrated circuit is reported in TECHNI-
`CAL REPORT OF IEICE, ICD93—107 (1993—10) of THE
`INSTITUTE OF ELECTRONICS, INFORMATION AND
`COMMUNICATION ENGINEERS, which is described
`with reference to FIG. 1.
`
`FIG. 1 is a circuit diagram which outlines a part of an
`MT—CMOS integrated circuit. Referring to FIG. 13, logic
`gate 99, in which many low-threshold transistors (LVth-
`Tr’s) are placed, is connected between power supply termi-
`nal 100 at which the operation voltage (VDD) is provided
`and grounding terminal 101 at which the grounding potential
`(VGN) is provided. Connected between power supply ter-
`minal 100 and logic gate 99 is a p-channel, high-threshold
`transistor (pHVth-Tr 91). Further, connected between logic
`gate 99 and grounding terminal 101 is an n-channel, high-
`threshold transistor (nHVth-Tr 92). Transistors 93—96, con-
`tained in logic gate 99, are low-threshold transistors, there-
`fore having the ability to operate at high speed and perform
`arithmetic operations at high speed, but on the other hand, a
`large leakage current will flow therein. This may lead to an
`increase in power consumption. To cope with this problem,
`HVth-Tr 91 is placed between logic gate 99 and terminal
`100 and HVth-Tr 92 is placed between logic gate 99 and
`terminal 101.
`
`The operation of the MT—CMOS integrated circuit of FIG.
`1 is described. The electric potential of node 97 between
`logic gate 99 and pHVth-Tr 91 is the virtual power supply
`potential (VDDV), while the electric potential of node 98
`between logic gate 99 and nHVth-Tr 92 is the virtual
`grounding potential (VGNV). Electric charges are applied to
`node 97 that acts as a virtual power supply terminal and to
`node 98 that acts as a virtual grounding terminal by having
`HVth-Tr 91 and HVth-Tr 92 placed in the ON state during
`the operation period of logic gate 99, whereby logic gate 99
`formed of LVth-Tr’s 93—96 starts operating at high speed.
`On the other hand, the supply of voltage from terminal 100
`to logic gate 99 is cut off by having HVth-Tr 91 placed in the
`OFF state during the standby period, and HVth-Tr 92 turns
`off thereby suppressing leakage current from logic gate 99 to
`terminal 101 during the standby period. As a result, leakage
`from terminal 100 to terminal 101 can be held considerably
`low.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`In a CMOS integrated circuit constructed of a PMOS
`circuit and an NMOS circuit, only one of them is placed in
`the ON state when the CMOS integrated circuit
`is in
`operation, and therefore the dissipation of power is low.
`When faults and/or defects, such as bridging between wires,
`occur in CMOS integrated circuits, power consumption is
`increased on the order of a few digits. This is utilized in
`methods, such as standby current testing and IDDQ testing,
`for detecting faults by observing increases in the value of
`electric current at the time of testing LSIs formed of CMOS
`integrated circuits.
`As previously mentioned, with the reduction in LSI
`supply voltage with a view to reducing power consumption
`as low as possible, the reduction of Vth for MOS transistors
`disposed in CMOS integrated circuits has been strongly
`demanded in order to secure a satisfactory operating speed.
`However, for the case of MOS transistors low in Vth, there
`occurs an increase in leakage current in the standby state. To
`cope with such a problem, two techniques have been devel-
`oped for the reduction of power consumption during the
`standby period. One technique employs a configuration for
`CMOS integrated circuits for increasing the Vth of respec-
`tive MOS transistors in the standby state by substrate
`voltage control, i.e., a so-called variable threshold-voltage
`CMOS integrated circuits (VT-CMOSs) configuration. On
`the other hand, the other technique employs the foregoing
`MT—CMOS integrated circuit configuration for CMOS inte-
`grated circuits, in other words a CMOS integrated circuit
`configuration is provided in which a circuit of low-Vth MOS
`transistors is placed in the OFF state during the standby
`period using high-Vth MOS transistors. The MT—CMOS
`integrated circuit configuration has the advantage over the
`VT—CMOS integrated circuit configuration in that it can
`achieve faster switching from operation mode to standby
`mode.
`
`The above-described MT—CMOS integrated circuit con-
`figuration however has the problem that
`the amount of
`leakage current occurring in standby mode increases due to
`each of low-Vth MOS transistors forming a CMOS inte-
`grated circuit. The proportion of an incremental amount of
`abnormal current accompanied with abnormal conditions
`(faults and/or defects) is therefore reduced, which makes it
`difficult to detect faults at test time. Testing including IDDQ
`testing is difficult to carry out.
`
`SUMMARY OF THE INVENTION
`
`Bearing in mind the above-described problems with the
`prior art techniques, the invention was made. Accordingly,
`an object of the invention is to provide a novel semicon-
`ductor integrated circuit containing therein MOS circuits
`constructed of low-Vth transistors, the semiconductor inte-
`grated circuit being capable of detecting an increase in the
`amount of electric current caused by an abnormal condition
`taking place in a MOS circuit.
`Arrangements are made in order to achieve the object of
`the invention, in which a circuit of low-Vth MOS transistors
`that is tested is divided into a plurality of circuit blocks and
`high-Vth MOS transistors for turning off the circuit blocks
`during the normal standby mode of operation are utilized
`also at the time of testing for leakage current. In other words,
`it is arranged for each circuit block that a circuit current in
`each circuit block is directed to a test circuit through a
`high-Vth MOS transistor.
`In accordance with the invention, a circuit block that is
`tested is selected using a high-Vth MOS transistor disposed
`for switching off power at standby time, and a supply current
`
`0021
`
`0021
`
`

`

`6,119,250
`
`4
`FIG. 16 is a circuit diagram showing the details of a
`test-target circuit, i.e., a candidate for testing, and a circuit
`block switch part shown in FIG. 15.
`FIG. 17 is a circuit diagram showing the details of a test
`circuit shown in FIG. 15.
`
`5
`
`FIG. 18 is a circuit diagram of a circuit where a reference
`current value is determined based on measured values.
`
`10
`
`FIG. 19 is a circuit diagram partially showing a circuit
`formed as a result of addition of a spare block switch circuit
`to the FIG. 16 circuit.
`
`3
`in a circuit of low-Vth MOS transistors is detected for each
`selected circuit block, and the detected supply current is
`compared with a reference value to determine whether it is
`acceptable or not. As a result of such arrangement,
`the
`number of circuit blocks that are tested at one time during
`the test mode of operation is limited, whereupon testing
`including IDDQ testing can be implemented by detecting an
`increase in the supply current due to faults and/or defects in
`low-Vth MOS transistors.
`
`In accordance with the invention, a circuit block is tested
`to determine presence or absence of a fault
`therein by
`leakage current testing, and if the circuit block is faulty, then
`such a faulty circuit block is replaced by a previously-
`prepared spare circuit block.
`As a result of such arrangement of replacing a faulty
`circuit block with a spare circuit block, it becomes possible
`to correct existing faults. This provides improvements in the
`yield of semiconductor integrated circuits. Additionally,
`since leakage current is judged per circuit block, this makes
`it possible to easily specify a circuit block in which a leakage
`current in excess of the reference value flows. Accordingly,
`this invention provides a semiconductor integrated circuit
`capable of circuit block evaluation, fault analysis, and other
`similar operations.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is an electric circuit diagram of a typical
`MT—CMOS integrated circuit in accordance with the prior art
`technique.
`FIG. 2 is an electric circuit diagram of an MT-CMOS
`integrated circuit belonging to the first embodiment of the
`invention.
`
`FIG. 3 outlines in block form a test device belonging to
`the first to sixth embodiments of the invention.
`
`FIG. 4 is a flow chart showing a test procedure belonging
`to the first embodiment of the invention.
`
`FIG. 5 is an electric circuit diagram of an MT-CMOS
`semiconductor integrated circuit belonging to the second
`embodiment of the invention.
`
`FIG. 6 is a flow chart showing a test procedure belonging
`to the second embodiment.
`
`FIG. 7 is an electric circuit diagram of an MT-CMOS
`integrated circuit belonging to the third embodiment of the
`invention.
`
`FIG. 8 shows in block form logic circuits in the
`MT—CMOS integrated circuit belonging to the third embodi-
`ment of the invention.
`FIG. 9 shows in block form a state control unit of the
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`PREFERRED EMBODIMENTS OF THE
`INVENTION
`
`EXAMPLE 1
`
`A first embodiment of this invention is described. FIG. 2
`
`is an electric circuit diagram of an MT-CMOS integrated
`circuit system of the first embodiment.
`Semiconductor integrated circuit 8, shown in FIG. 2, has
`logic blocks 7a—7x formed of MT-CMOS integrated circuits.
`Logic blocks 7a—7x have logic circuits 5a—5x, respectively.
`Each logic circuit 5a—5x is formed of many low-threshold
`transistors (LVth-Tr’s) and is connected between power
`supply terminal 10 at which VDD is provided and grounding
`terminal 11 at which VGN is provided. Connected between
`each of logic circuits 5a—5x and terminal 10 are p-channel,
`high-threshold transistors (pHVth-Tr’s) la—lx. On the other
`hand, connected between each of logic circuits 5a—5x and
`terminal 11 are n-channel, high-threshold transistors
`(nHVth-Tr’s) 2a—2x. The electric potential of first nodes
`3a—3x between pHVth-Tr’s la—lx and logic circuits 5a—5x
`is VDDV (the virtual power supply potential). On the other
`hand, the electric potential of second nodes 4a—4x between
`nHVth-Tr’s 2a—2x and logic circuits 5a—5x is VGNV (the
`virtual grounding potential). Semiconductor integrated cir-
`cuit 8 is provided with state control unit 6. State control unit
`6 has test control unit 6a. In response to a test signal (Sdt)
`for testing components other than logic circuits 5a—5x, i.e.,
`each HVth-Tr and wires, test control unit 6a disconnects
`logic circuits 5a—5x from terminals 10 and 11 and, as a
`result, logic circuits 5a—5x each enter the standby state. State
`control unit 6 further has normal control unit 6b. In response
`to a normal control signal applied from inside semiconduc-
`tor integrated circuit 8, normal control unit 6b controls the
`operation of the low-threshold transistors of the logic
`blocks.
`In the present embodiment, power supply and
`grounding terminals 10 and 11 common to logic blocks
`7a—7x are provided and, during the test period, test control
`unit 6a of state control unit 6 controls all of pHVth-Tr’s
`la—lx and nHVth-Tr’s 2a—2x in logic blocks 7a—7x to go
`into the OFF state at the same time. According to the normal
`control signal, each HVth-Tr is controlled, by normal control
`unit 6b, to turn on during the operation period of logic blocks
`7a—7x or to turn off during the standby period.
`A technique of testing semiconductor integrated circuit 8
`having the above-described organization is now described
`with reference to FIGS. 3 and 4.
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`FIG. 3 outlines in block form the organization of tester 13
`for testing semiconductor integrated circuits for use in the
`first to sixth embodiments. As shown in the figure, tester 13
`has probes 14a and 14b which are brought into contact with
`both ends of a part of semiconductor integrated circuit 8,
`ammeter 15 that is connected to probes 14a and 14b, storage
`device 16 which stores a predetermined set value, judgement
`circuit 17 which determines whether a target of testing is
`acceptable or unacceptable, and display device 18 which
`
`MT—CMOS integrated circuit belonging to the third embodi-
`ment of the invention.
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`FIG. 10 is a flow chart showing a test procedure belonging
`to the third embodiment of the invention.
`
`FIG. 11 outlines in block form a test device belonging to
`the third embodiment of the invention.
`FIG. 12 shows in block form a state control unit in an
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`MT-CMOS integrated circuit belonging to the fourth
`embodiment of the invention.
`FIG. 13 shows in block form a state control unit in an
`
`MT—CMOS integrated circuit belonging to the fifth embodi-
`ment of the invention.
`
`FIG. 14 is an electric circuit diagram of an MT-CMOS
`integrated circuit belonging to the sixth embodiment of the
`invention.
`
`FIG. 15 shows in block form a semiconductor integrated
`circuit belonging to the seventh embodiment of the inven-
`tion.
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`indicative of a judgement result from
`receives a signal
`judgement circuit 17 and displays the result. At the time of
`testing semiconductor integrated circuit 8, probes 14a and
`14b are brought into contact with a location defined between
`terminals 10 and 11, to detect, for example, an HVth-Tr
`failure.
`
`FIG. 4 is a flow chart showing a test procedure of the
`present embodiment. In step ST11, when the test signal Sdt
`goes into the ON state, pHVth-Tr’s la—lx and nHVth Tr’s
`2a—2x of logic blocks 7a—7x are controlled by test control
`unit 6a to turn off. If pHVth-Tr’s la—lx and nHVth Tr’s
`2a—2x enter the OFF state in normal manner, this have logic
`circuits 5a—5x placed in the standby state, in other words
`logic circuits 5a—5x are disconnected from power supply and
`grounding terminals 10 and 11.
`In step ST12, an electric current flowing in a path is
`measured. Such measurement may be carried out at the side
`of power supply terminal 10 or at the side of grounding
`terminal 11.
`
`In step ST13, a check is made to determine whether Idt
`(the detected value of a leakage current when signal Sdt is
`in the OFF state) is below Is (the predetermined set value).
`If Idt is less than Is, this means “accepted”. If Idt is equal to
`or greater than Is, this means “rejected”. The set value, Is, is
`given by:
`
`15:1+K1
`
`where I
`
`is the electric current
`
`that flows under normal
`
`conditions and K1 is the constant allowing for characteristic
`variations occurring in the fabrication. The set value, Is, is
`stored in storage device 16.
`In accordance with the present embodiment, it is possible
`to determine whether a logic block in the MT—CMOS
`integrated circuit makes a transition to the standby state
`during the test period,
`in other words it
`is possible to
`effectively detect a faulty product
`that fails to operate
`normally due to the malfunction of high-threshold transis-
`tors or due to the short-circuiting of wires of the MT—CMOS
`integrated circuit. Wire short-circuit that is detected by the
`present
`test
`is wire short-circuit occurring outside logic
`circuits 7a—7x, such as a short-circuit occurring between
`source terminals of pHVth- and nHVth-Tr’s connected to the
`same logic circuit (for example, pHVth-Tr 1a and nHVth-Tr
`2a connected to logic circuit 7a), and a short-circuit occur-
`ring between the source and drain of an HVth-Tr when the
`HVth-Tr’s are provided at one side only.
`In this way,
`faulty products are screened and only
`MT—CMOS integrated circuits free from defects are selected
`and shipped from the factory. The present embodiment has
`been described in terms of an MT—CMOS integrated circuit
`including a plurality of logic blocks formed of MT—CMOS
`integrated circuits. The invention may be embodied in an
`MT—CMOS integrated circuit including only one logic block
`formed of MT—CMOS integrated circuits.
`In accordance with the present embodiment, state control
`unit 6 is placed outside logic blocks 7a—7x. State control unit
`6 may be placed in each logic block 7a—7x.
`In accordance with the present embodiment, it is designed
`such that the test signal Sdt is applied directly from outside
`semiconductor integrated circuit 8 to test control unit 6a of
`state control unit 6. The test signal Sdt may be generated
`within each logic block 7a—7x, and the same effects can be
`obtained. Further,
`in accordance with the present
`embodiment, the normal control signal is generated within
`semiconductor integrated circuit 8. The normal control sig-
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`nal may be applied from outside semiconductor integrated
`circuit 8, that is, from outside the semiconductor chip.
`
`EXAMPLE 2
`
`A second embodiment of the invention is now described
`
`by reference to FIGS. 5 and 6. FIG. 5 is an electric circuit
`diagram which outlines an organization of MT—CMOS inte-
`grated circuit 21 according to the present embodiment. FIG.
`6 is a flow chart showing a test procedure for semiconductor
`integrated circuit 21.
`MT—CMOS integrated circuit 21 shown in FIG. 5 has
`logic blocks 7a—7x formed of MT—CMOS integrated circuits,
`and state control unit 22. State control unit 22 is described.
`
`Having received test signals Sdtl—Sdti, state control unit 22
`controls pHVth- and nHVth-Tr’s, which are contained in
`one or more logic blocks (hereinafter called a subset of logic
`blocks) of logic blocks 7a—7x subjected to testing, to turn
`off. State control unit 22 has decoder 22a which receives the
`
`test signals Sdtl—Sdti, decoder 22b which receives the nor-
`mal control signals, and selector 22c which selects between
`the output from decoder 22a and the output from decoder
`22b. According to a combination of Sdtl—Stdi, decoder 22a
`provides a signal that has pHVth- and nHVth-Tr’s within a
`test-target logic block subset of logic blocks 7a—7x placed in
`the OFF state. Selector 22C selects, based on a mode switch
`signal
`indicative of test mode or normal control mode,
`between the test signal and the normal control signal.
`Selector 22C then provides a selection.
`Logic blocks 7a—7x are provided with their respective
`power supply and grounding terminals 10a—10x and
`Ila—11x. It is to be noted that each logic block of the present
`embodiment
`is identical
`in internal organization with a
`corresponding one of the first embodiment.
`The test apparatus of the present embodiment is basically
`identical in organization with that of the first embodiment
`shown in FIG. 3. The value of electric current is detected by
`bringing probes 14a and 14b of FIG. 3 into contact with, for
`example, external pins. The set value, Is, is given by:
`
`15=I+Kk
`
`where Kk is the constant allowing for characteristic varia-
`tions occurring in the fabrication. The electric potential of
`grounding terminals Ila—11x is assumed to be zero.
`A test procedure is described with reference to the FIG. 6
`flow chart.
`
`In step ST21, a combination of test signals that signifies
`a test-target logic block subset, is fed to decoder 22a of state
`control unit 22. Suppose that logic block 7a is designated in
`the present embodiment. If either pHVth-TR 1a or nHVth-
`Tr 2a operates normally, the target logic block subset 7a is
`disconnected from power supply terminal 10a or grounding
`terminal 11a to enter the standby state.
`Next, in step ST22, Idta, which is the electric current
`value of logic block subset 7a, is measured at locations on
`the side of power supply terminal 10a or on the side of
`grounding terminal 11a.
`Step ST23 determines whether the detected current value
`Idta less than the set value Is. If Idta is determined to be less
`
`than Is, this means “accepted”. On the other hand, if Idta is
`determined to be equal to or greater than Is, this means
`“rejected”.
`for
`logic block subset,
`that a different
`In the event
`is designated to be a
`example,
`logic block subset 7x,
`test-target logic block subset,
`the current value of logic
`block subset 7x is measured to determine whether pHVth-Tr
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`1x or nHVth-Tr 2x of logic block subset 7x operates
`normally, in other words whether the detected current value
`Idtx is less than the set value Is is determined. If Idtx is
`determined to be less than Is, this means “accepted”. On the
`other hand, if Idtx is determined to be equal to or greater
`than Is, this means “rejected”.
`Like the first embodiment, it is possible for the present
`embodiment to determine whether an MT—CMOS integrated
`circuit is acceptable or not. Particularly, the present embodi-
`ment provides the advantage that, even when logic block
`subsets have different power supply voltages,
`it
`is still
`possible to determine, without fail, whether test-target logic
`block subsets are acceptable or unacceptable.
`In the present embodiment, each of logic blocks 7a—7x
`formed of MT—CMOS integrated circuits is provided with
`power supply terminal 10 and grounding terminal 11.
`However, power supply terminals 10 and grounding termi-
`nals 11 may be arranged to one logic block subset, for
`example,
`logic block subset 7a. Alternatively, a power
`supply and grounding terminals common between a plurality
`of logic blocks that belong in the same logic block subset
`may be provided, which achieves the same effects as the
`present embodiment.
`In accordance with the present embodiment, state control
`unit 22 is arranged outside logic blocks 7a—7x. State control
`unit 22 may be formed within each logic block.
`Further, in the present embodiment, it is arranged such
`that the test signals Sdtl—Sdti are fed to decoder 22a of state
`control unit 22 from outside semiconductor integrated cir-
`cuit 8; however, these signals may be generated within logic
`blocks 7a—7x of semiconductor integrated circuit 8.
`Furthermore, in the present embodiment, the normal control
`signal
`is applied from outside semiconductor integrated
`circuit 8; however, the normal control signal may be gen-
`erated outside semiconductor integrated circuit 8, that is,
`inside the semiconductor chip.
`EXAMPLE 3
`A third embodiment of the invention relates to a method
`
`for generating a test sequence for a semiconductor integrated
`circuit. FIG. 7 is an electric circuit diagram showing an
`organization of MT—CMOS integrated circuit 41 in accor-
`dance with the present embodiment.
`Semiconductor
`integrated circuit 41 of the present
`embodiment has basically the same organization as semi-
`conductor integrated circuit 8 of the first embodiment shown
`in FIG. 2. In the present embodiment, state control unit 42
`is provided. State control unit 42 includes test control unit
`42a. When the state control signal MODE is at “1” during
`the logic circuit test period, test control unit 42a controls the
`entirety of a logic circuit group 43, which is formed of logic
`circuits 5a—5x of logic blocks 7a—7x which is a target of
`testing,
`to connect with terminals 10 and 11 (the power
`supply terminal and the grounding terminals). In the present
`embodiment, when the state control signal MODE is at “1”,
`this means that logic circuit group 43 is in the ON state. Like
`each of the foregoing embodiments, normal control unit 42b
`is arranged in state control unit 42 for controlling the normal
`operation of logic circuit group 43 according to the normal
`control signal.
`FIG. 8 is a circuit diagram in block form showing an
`example of the organization of logic circuit group 43.
`Connected between input pins A—D and an output pin OUT
`are circuit elements including a flip-flop DFF, two AND
`circuits, an OR circuit, and an inverter INV. FIG. 8 shows
`identification names for the circuit elements, names for the
`input pins, a name for the output pin, and names for wire
`nets.
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`FIG. 9 is a block circuit diagram showing an organization
`of state control unit 42. State control unit 42 is formed of an
`
`OR circuit which receives the normal control signal and the
`state control signal (MODE) and generates the OR of these
`input signals. Each HVth-Tr is controlled to go into the ON
`state when state control unit 42 provides the HVth-Tr control
`signal at “1”. In other words, the function of test control unit
`42a and the function of normal control unit 42b (see FIG. 7)
`are incorporated into the OR circuit.
`The functions of test control unit 6a and normal control
`
`unit 6b (see FIG. 2) may be implemented by an organization
`shown in FIG. 9, that is, by a single OR circuit.
`
`A method of generating a test sequence for the above-
`described semiconductor integrated circuit is illustrated with
`reference to a flow chart shown in FIG. 10.
`
`In step ST31, a netlist, shown in TABLE 1, is created to
`be circuit descriptions for logic circuit group 43, a tar