USOO6111427A
`
`[19]
`United States Patent
`6,111,427
`[11] Patent Number:
`[45] Date of Patent: Aug. 29, 2000
`FUJ 11 et al.
`
`
`
`[54] LOGIC CIRCUIT HAVING DIFFERENT
`THRESHOLD VOLTAGE TRANSISTORS AND
`ITS FABRICATION METHOD
`
`[75]
`
`Inventors: Koji Fujii, Zama; Takakuni Douseki,
`Atsugi, both of Japan
`
`[73] Assignee: Nippon Telegraph and Telephone
`Corporation, Toyko, Japan
`
`[21] Appl. No.: 08/861,319
`
`[22]
`
`Filed:
`
`May 21, 1997
`
`[30]
`
`Foreign Application Priority Data
`
`May 22, 1996
`Aug. 13, 1996
`
`[JP]
`[JP]
`
`Japan .................................... 8—150268
`Japan .................................... 8—231306
`
`Int. Cl.7 ..................................................... H03K 17/16
`[51]
`[52] US. Cl.
`................................ 326/34; 326/83; 326/121
`[58] Field of Search ........................... 326/17, 31, 34—36,
`326/53, 54, 55, 83, 86, 112, 119, 121
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,107,548
`8/1978 Sakaba et al.
`.......................... 326/119
`4,441,039
`4/1984 Schuster ..................... 326/86
`
`4,473,762
`...... 327/262
`9/1984 Iwahashi et al.
`..
`
`4,563,599
`...... 326/120
`1/1986 Donoghue et al.
`4,714,840 12/1987 Proebsting .........
`326/34
`
`.......................... 326/81
`5,486,774
`1/1996 Douseki et al.
`.................................. 326/119
`5,594,371
`1/1997 Douseki
`
`5,610,533
`3/1997 Arimoto et al.
`326/33
`5,821,769
`10/1998 Douseki
`.................................... 326/34
`
`FOREIGN PATENT DOCUMENTS
`
`0690510 A1
`4—263468
`08287686
`
`1/1996 European Pat. Off.
`9/1992
`Japan .
`11/1996
`Japan .
`OTHER PUBLICATIONS
`
`.
`
`ISSCC96/Session 5/Technology Directions: High Speed,
`Low Power/Paper TP 5. TP:5.4 A 0.5V Simox—MTCMOS
`Circuit With 200ps Logic Gate; Takakuni Douseki, et al.,
`1996 IEEE International Solid—State Circuits Conference;
`pp. 84—85, 66—67, and 364—365.
`
`Primary Examiner—Jon Santamauro
`Assistant Examiner—Don Phu Le
`
`Attorney, Agent, or Firm—Venable; Robert J. Frank; Jeffrey
`W. Gluck
`
`[57]
`
`ABSTRACT
`
`A logic circuit having a first logic gate and the remaining
`logic gate or gates. The first logic gate is interposed in a
`signal path determining an operating speed, and includes at
`least one first MOS transistor which has a threshold voltage
`lower than a predetermined voltage and operates at a high
`speed. The remaining logic gate or gates include at least one
`of a second MOS transistor and a third MOS transistor as a
`
`transistor having a margin for operating speed. The second
`MOS transistor has a middle threshold voltage equal to or
`greater than the predetermined voltage, and the third MOS
`transistor has a high threshold voltage equal to or greater
`than the predetermined voltage. The power consumption of
`the entire logic circuit at the time of operation is reduced,
`While maintaining the maximum operating speed.
`
`17 Claims, 24 Drawing Sheets
`
`C1:CMOS LOGIC CIRCUIT
`\’\
`
`L1
`
`L2
`
`L3
`
`L4
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`OUT
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`LOGIC
`CIRCUIT
`
`L9
`L8
`L7
`L6
`L5
`
`PATH THAT DETERMINES OPERATING SPEED
`
`INl
`
`INZ
`
`1N3
`
`IN4
`
`IN5
`
`0001
`
`AMD EX1043
`
`US. Patent No. 6,239,614
`
`AMD EX1043
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 1 0f 24
`
`6,111,427
`
`HZH
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`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 2 0f 24
`
`6,111,427
`
`L1 : LOGIC CIRCUIT
`
`/
`
`VDD
`
`11
`
`[J
`
`W2
`
`GND
`
`FIG.2
`
`0003
`
`0003
`
`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 3 0f 24
`
`6,111,427
`
`L2 , L3 : LOGIC CIRCUIT
`
`VDD
`
`/
`
`2 1
`
`(J
`|__
`
`24 :VIRTUAL VDD
`
`FIG.3
`
`.
`
`22
`
`L4 ”V L9 : LOGIC CIRCUIT
`
`/
`
`VDD
`
`4 1
`
`F/
`l.— 44 :VIRTUAL VDD
`
`FIGo4
`
`-
`
`42
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 4 0f 24
`
`6,111,427
`
`LOW
`THRESHOLD
`VOLTAGE
`MOS
`
`MIDDLE
`THRESHOLD
`VOLTAGE
`MOS
`
`HIGH
`THRESHOLD
`VOLTAGE
`MOS
`
`TRANSISTOR TRANSISTOR TRANSISTOR
`
`FIG.5
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 5 0f 24
`
`6,111,427
`
` 101-2
`
`101-3
`
`102-2
`
`
`
`102-3
`
`103-2
`
`103-3
`
`
`
`101—2 101-3
`
`102—2 102-3
`
`103-2 103-3
`
`FIG.6B
`
`0006
`
`0006
`
`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 6 0f 24
`
`6,111,427
`
`LOW
`THRESHOLD
`IMPLANTATION
`
`111
`LOW
`THRESHOLD
`
`IMPLANTATION
`
`WI--IWWI--Im
`
`
`112
`
`MIDDLE
`THRESHOLD
`IMPLANTATION
`
`MIDDLE
`THRESHOLD
`IMPLANTATION
`
`
`
`WI--IWI--IW
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 7 0f 24
`
`6,111,427
`
`111
`
`112
`
`FIG.8A
`
`FIG.8B
`
`0008
`
`0008
`
`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet8 0f24
`
`6,111,427
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`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 9 0f 24
`
`6,111,427
`
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`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet10 0f24
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`6,111,427
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`

`US. Patent
`
`Aug. 29, 2000
`
`Sheetll 0f24
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`6,111,427
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`US. Patent
`
`Aug. 29, 2000
`
`Sheet12 0f24
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`6,111,427
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`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 13 0f 24
`
`6,111,427
`
`MIDDLE-Vth
`
`1012
`
`1013
`
`IMPURITY CONCENTRATION
`IN THE CHANNEL REGION (cm-2)
`
`FIG.10
`
`0014
`
`0014
`
`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet14 0f24
`
`6,111,427
`
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`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 15 0f 24
`
`6,111,427
`
`C2 : LOGIC CIRCUIT
`
`\ B1
`
`B3
`
`IN1
`
`IN2
`IN3
`
`CK
`
`CIRCUIT
`
`BLOCK I
`
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`BLOCK
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`FIG.12
`
`0016
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`
`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 16 0f 24
`
`6,111,427
`
`Bl , BZ : CIRCUIT BLOCK
`
`VDD
`
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`
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`|-———
`
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`
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`
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`R
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`
`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 17 0f 24
`
`6,111,427
`
`B1 : CIRCUIT BLOCK
`
`54 :VIRTUAL VDD
`
`52a
`
`VDD
`
`/
`
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`
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`
`53a
`
`GND
`
`FIG.15
`
`0018
`
`0018
`
`

`

`US. Patent
`
`Aug. 29,2000
`
`Sheet 18 0f 24
`
`6,111,427
`
`(ps)
`
`DELAYTIME
`
`NUMBER OF FAN-OUTS
`
`-4&—:HIGH
`THRESHOLD
`VOLTAGE MOS
`TRANSISTOR
`
`-€3—:MIDDLE
`THRESHOLD
`VOLTAGE MOS
`TRANSISTOR
`
`-%}—:LOW
`THRESHOLD
`VOLTAGE MOS
`TRANSISTOR
`
`FIG.16
`
`0019
`
`0019
`
`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 19 0f 24
`
`6,111,427
`
`nn>JEDBMH.>
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`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet20 0f24
`
`6,111,427
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`

`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 21 0f 24
`
`6,111,427
`
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`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 22 0f 24
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`6,111,427
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`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 23 0f 24
`
`6,111,427
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`

`US. Patent
`
`Aug. 29, 2000
`
`Sheet 24 0f 24
`
`6,111,427
`
`C1_1:CMOS LOGIC CIRCUIT
`
`/
`
`VDD
`
`8 1
`
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`'— 84 :VIRTUAL VDD
`
`82
`
`FIG.22
`
`PRIOR ART
`
`0025
`
`0025
`
`

`

`6,111,427
`
`1
`LOGIC CIRCUIT HAVING DIFFERENT
`THRESHOLD VOLTAGE TRANSISTORS AND
`ITS FABRICATION METHOD
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a logic circuit and its
`fabrication method, and more particularly to a circuit struc-
`ture for implementing a low power consumption CMOS
`logic circuit.
`2. Description of Related Art
`A CMOS circuit structure is widely employed in fields
`such as mobile telecommunication systems that consist of
`low power consumption LSIs with a supply voltage of one
`volts or less.
`
`FIG. 22 is a circuit diagram showing a conventional
`CMOS logic circuit. In FIG. 22, a CMOS logic circuit C11
`is composed of a high threshold voltage pMOS transistor 81,
`a low threshold voltage pMOS transistor 82, and a low
`threshold voltage NMOS transistor 83. In other words, the
`CMOS logic circuit C11 is composed of MOS transistors
`with the high threshold voltage and low threshold voltage.
`The conventional CMOS logic circuit C11 has a high
`operating speed because it uses low threshold voltage MOS
`transistors 82 and 83. In addition, smaller leakage current
`flows through the low threshold voltage MOS transistors 82
`and 83 in a sleeping mode than in an operating mode, since
`the pMOS transistor 81 is kept OFF. This can reduce power
`consumed by the low threshold voltage MOS transistors 82
`and 83 in the sleep mode.
`In the CMOS logic circuit C11, however, a leakage
`current flows through the MOS transistors 82 and 83, since
`the pMOS transistor 81 is turned on in the operation mode,
`and the leakage current causes power loss. Thus, the con-
`ventional CMOS logic circuit C11 has a problem in that it
`cannot prevent a power loss in an operation mode.
`SUMMARY OF THE INVENTION
`
`invention to
`therefore, an object of the present
`is,
`It
`provide a logic circuit capable of reducing the power con-
`sumption in the operation mode, while maintaining a high
`operating speed like the conventional circuit.
`It is another object of the present invention to provide a
`fabrication method for the logic circuit without increasing
`the process steps.
`In a first aspect of the present invention, there is provided
`a logic circuit comprising:
`a first logic gate having at least one first MOS transistor
`and interposed in a signal path determining an operat-
`ing speed, the first MOS transistor having a threshold
`voltage lower than a predetermined voltage and oper-
`ating at a high speed; and
`one or plural remaining logic gates other than the first
`logic gate having at least one of a second MOS tran-
`sistor and a third MOS transistor as a transistor having
`a margin for operating speed, the second MOS transis-
`tor having a medium threshold voltage equal to or
`greater than the predetermined voltage, and the third
`MOS transistor having a high threshold voltage equal
`to or greater than the predetermined voltage.
`The logic circuit may further comprise a fourth MOS
`transistor having a high threshold voltage interposed
`between a main power supply line and a terminal of at least
`one of the first and second MOS transistors on the side of a
`
`high potential power supply line.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`At least one first MOS transistor in the first logic gate may
`include a fifth MOS transistor constituting a transfer gate
`interposed in the signal path, and a sixth MOS transistor for
`controlling the fifth MOS transistor, and the one or plural
`remaining logic gates may include a second logic gate for
`determining an output of the fifth MOS transistor, and a third
`logic gate for controlling the sixth MOS transistor.
`The sixth MOS transistor may have its drain terminal
`connected to a gate terminal of the fifth MOS transistor, its
`source terminal connected to an output terminal of the third
`logic gate, and its gate terminal connected to one of the high
`potential power supply line and the main power supply line,
`or the ground.
`The first, second and third MOS transistors may have a
`$01 structure, and at least one of the low threshold voltage
`first MOS transistor and the medium threshold voltage
`second MOS transistor may be a fully depleted MOS
`transistor.
`
`The MOS transistors may have a $01 structure, at least
`one of the low threshold voltage first MOS transistor and the
`medium threshold voltage second MOS transistor may be a
`fully depleted MOS transistor, and the high threshold volt-
`age third MOS transistor may be a fully depleted MOS
`transistor.
`
`The fifth MOS transistor may be a first first-conductivity-
`type-channel MOS enhancement transistor having a source
`connected to a signal input terminal of the transfer gate, and
`a drain connected to a signal output terminal of the transfer
`gate,
`the sixth MOS transistor may be a second first-
`conductivity-type-channel MOS enhancement
`transistor
`having a source connected to an output terminal of the third
`logic gate, a drain connected to a gate of the first first-
`conductivity-type-channel MOS enhancement
`transistor,
`and a gate connected to the high potential power supply or
`the ground, and a body of the first first-conductivity-type-
`channel MOS enhancement transistor and a body of the
`second first-conductivity-type-channel MOS enhancement
`transistor may both be made floating.
`The first first-conductivity-type-channel MOS enhance-
`ment
`transistor and the second first-conductivity-type-
`channel MOS enhancement
`transistor may have a $01
`structure.
`
`The first first-conductivity-type-channel MOS enhance-
`ment
`transistor and the second first-conductivity-type-
`channel MOS enhancement transistor may be of the fully
`depleted type.
`One or plural remaining logic gates may include a full
`adder for performing addition by receiving first and second
`input signals and a carry signal,
`the carry signal being
`supplied to the transfer gate, the third logic gate may control
`to determine whether or not the carry signal is output from
`the transfer gate in response to the first and second input
`signals, and the second logic gate may generate as an output
`of the transfer gate an output predetermined in accordance
`with the first and second input signals when the carry signal
`is not output from the transfer gate in response to the first
`and second input signals.
`At least one first MOS transistor having a lower threshold
`voltage may include first and second first-conductivity-type-
`channel enhancement MOS transistors,
`the first
`first-
`conductivity-type-channel enhancement MOS transistor
`having a source connected to a signal input terminal, and a
`drain connected to a signal output terminal; and the second
`first-conductivity-type-channel enhancement MOS transis-
`tor having a source connected to a control terminal, a drain
`connected to a gate of the first first-conductivity-type-
`channel enhancement MOS transistor, and a gate connected
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`to a high potential power supply or the ground, the first and
`second first-conductivity-type-channel enhancement MOS
`transistors, whose bodies are made floating, may constitute
`a switching circuit as a transfer gate.
`there is
`invention,
`In a second aspect of the present
`provided a fabrication method for fabricating a logic circuit
`including a first logic gate having at least one first MOS
`transistor and interposed in a signal path determining an
`operating speed, the first MOS transistor having a threshold
`voltage lower than a predetermined voltage and operating at
`a high speed; and
`one or plural remaining logic gates other than the first
`logic circuit having at least one of a second MOS transistor
`and a third MOS transistor as a transistor having a margin for
`operating speed,
`the second MOS transistor having a
`medium threshold voltage equal
`to or greater than the
`predetermined voltage, and the third MOS transistor having
`a high threshold voltage equal to or greater than the prede-
`termined voltage,
`the fabrication method comprising the steps of:
`(A) forming MOS device regions for forming MOS
`transistors having low, medium and high threshold
`voltages, the MOS device regions being isolated from
`each other;
`(B) implanting impurity for a low threshold into the MOS
`device regions for forming the MOS transistors having
`the low and high threshold voltages; and
`(C) implanting impurity for a medium threshold into the
`MOS device regions for forming the MOS transistors
`having the medium and high threshold voltages.
`The step (A) may form in the MOS device regions first
`and second conductivity type MOS device regions; and the
`steps (B) and (C) may be carried out in the first conductivity
`type MOS device regions; and subsequently the steps (B)
`and (C) may be carried out in the second conductivity type
`MOS device regions.
`In a third aspect of the present invention, there is provided
`a fabrication method for fabricating a logic circuit including
`a first logic gate having at least one first MOS transistor and
`interposed in a signal path determining an operating speed,
`the first MOS transistor having a threshold voltage lower
`than a predetermined voltage and operating at a high speed;
`one or plural remaining logic gates other than the first
`logic circuit having at least one of a second MOS
`transistor and a third MOS transistor as a transistor
`
`having a margin for operating speed, the second MOS
`transistor having a medium threshold voltage equal to
`or greater than the predetermined voltage, and the third
`MOS transistor having a high threshold voltage equal
`to or greater than the predetermined voltage; and
`a fourth MOS transistor having a high threshold voltage
`interposed between a main power supply line and a
`terminal of at least one of the first and second MOS
`
`transistors on the side of a high potential power supply
`line;
`the fabrication method comprising the steps of:
`(A) forming MOS device regions for forming MOS
`transistors having low, medium and high threshold
`voltages, the MOS device regions being isolated from
`each other;
`(B) implanting impurity for a low threshold into the MOS
`device regions for forming the MOS transistors having
`the low and high threshold voltages; and
`(C) implanting impurity for a medium threshold into the
`MOS device regions for forming the MOS transistors
`having the middle and high threshold voltages.
`
`4
`The above and other objects, effects, features and advan-
`tages of the present invention will become more apparent
`from the following description of the embodiments thereof
`taken in conjunction with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram showing a first embodiment of
`a logic circuit in accordance with the present invention;
`FIG. 2 is a circuit diagram showing a specific embodiment
`of a logic gate in the logic circuit L1 in FIG. 1;
`FIG. 3 is a circuit diagram showing a specific embodiment
`of a logic gate in the logic circuits L2 and L3 in FIG. 1;
`FIG. 4 is a circuit diagram showing a specific embodiment
`of a logic gate in the logic circuits L4—L9 in FIG. 1;
`FIG. 5 is an explanatory diagram illustrating symbols of
`nMOS and pMOS transistors, each having low, medium and
`high threshold voltages respectively;
`FIGS. 6A and 6B are plan and cross-sectional views,
`respectively, showing MOS transistors with low, medium
`and high threshold voltages used in the logic circuit in
`accordance with the present invention;
`FIGS. 7A and 7B are cross-sectional views showing a
`fabrication process of the MOS transistors shown in FIGS.
`6A and 6B in accordance with the present invention;
`FIGS. 8A and 8B are plan views showing the masks for
`low and medium ion implantation used in the fabrication
`process shown in FIGS. 7A and 7B;
`FIGS. 9A—9J are cross-sectional views illustrating a spe-
`cific embodiment of the process steps shown in FIGS. 7A
`and 7B;
`FIG. 10 is a characteristic diagram illustrating relation-
`ships between the impurity concentration in a channel region
`and a threshold voltage;
`FIG. 11 is a block diagram showing a second embodiment
`of a logic circuit in accordance with the present invention;
`FIG. 12 is a block diagram showing a third embodiment
`of a logic circuit in accordance with the present invention;
`FIG. 13 is a circuit diagram showing a specific embodi-
`ment of a logic gate in the circuit blocks B1 and B2 in FIG.
`12;
`FIG. 14 is a circuit diagram showing a specific embodi-
`ment of a logic gate in the circuit block B3 in FIG. 12;
`FIG. 15 is a circuit diagram showing a modification of the
`logic gate in the circuit block B1 in FIG. 12;
`FIG. 16 is a characteristic diagram comparatively illus-
`trating relationships between the number of fan-outs and
`delay times of a two-input NAND gate composed of three
`types of MOS transistors with low, medium and high thresh-
`old voltages;
`FIG. 17 is a circuit diagram showing a full adder as a
`fourth embodiment of a logic circuit in accordance with the
`present invention;
`FIGS. 18A and 18B are diagrams plotting voltages at
`various terminals based on circuit simulation when using
`high threshold voltage transistors as the MOS transistors of
`the switching circuit SW;
`FIGS. 19A and 19B are diagrams plotting voltage at
`various terminals based on circuit simulation when using
`low threshold voltage transistors as the MOS transistors of
`the switching circuit SW;
`FIG. 20 is a block diagram showing a 4-bit adder com-
`posed of the full adders as shown in FIG. 17;
`FIG. 21 is a circuit diagram showing a full adder as a fifth
`embodiment of a logic circuit in accordance with the present
`invention; and
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`5
`FIG. 22 is a circuit diagram showing an example of a
`conventional CMOS circuit.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`The present invention will now be described with refer-
`ence to the accompanying drawings.
`Embodiment 1
`
`FIG. 1 is a block diagram showing a first embodiment of
`a logic circuit C1 in accordance with the present invention.
`In FIG. 1, a CMOS logic circuit C1 is a combinational
`logic circuit composed of logic circuits L1—L9. The logic
`circuits L4—L9 are each composed of logic gates using low
`threshold voltage MOS transistors, and the operating speed
`of the CMOS logic circuit C1 is determined by the logic
`circuits L4—L9.
`
`FIG. 2 is a circuit diagram showing a logic gate in the
`logic circuit L1 in the CMOS logic circuit C1, which is
`composed of high threshold voltage MOS transistors 11 and
`12.
`
`FIG. 3 shows a specific embodiment of a logic gate in the
`logic circuits L2 and L3 in the CMOS logic circuit C1.
`The logic gate in the logic circuit L2 includes a series
`connection of a medium threshold voltage pMOS transistor
`22 and a medium threshold voltage nMOS transistor 23. The
`power supply VDD is connected to a virtual high potential
`power supply line (Virtual VDD) 24 through a high threshold
`voltage pMOS transistor 21. The other terminal of the
`medium threshold voltage nMOS transistor 23 is connected
`to the ground potential GND. The logic circuit I3 in the
`CMOS logic circuit C1 is also composed in the same fashion
`as the logic circuit L2.
`FIG. 4 shows a specific embodiment of a logic gate in the
`logic circuits L4—L9 in the CMOS logic circuit C1.
`The logic gate of the logic circuit L4 includes a series
`connection of a low threshold voltage pMOS transistor 42
`and a low threshold voltage nMOS transistor 43. The power
`supply VDD is connected to a virtual high potential power
`supply line (Virtual VDD) 44 via a high threshold voltage
`pMOS transistor 41. The other terminal of the low threshold
`voltage nMOS transistor 43 is connected to the ground
`potential GND. The logic circuits L5—L9 in the CMOS logic
`circuit C1 are each composed in the same fashion as the
`logic circuit L4.
`FIG. 5 illustrates the symbols of the nMOS transistors and
`pMOS transistors as shown in FIGS. 1—4, for the respective
`three types of threshold voltages.
`In the CMOS logic circuit C1, the logic circuits L1, L2
`and L3 have a margin for speed, and are each composed of
`medium threshold voltage MOS transistors or high threshold
`voltage MOS transistors. The medium threshold voltage
`MOS transistors or high threshold voltage MOS transistors
`have a lower leakage current in the operation mode com-
`pared with low threshold voltage transistor, so that the power
`consumed is reduced by an amount corresponding to the low
`leakage current in the operation mode. Accordingly, the total
`power consumption of the CMOS logic circuit C1 is reduced
`by an amount equal to the reduced power consumption by
`the logic circuits L1, L2 and L3.
`FIGS. 7A and 7B show a fabrication method in accor-
`
`dance with the present invention, in which the low, medium
`and high threshold voltage nMOS transistors 101, 102 and
`103 are fabricated whose layout patterns are shown in FIG.
`6A and whose cross-sections are shown in FIG. 6B. Here,
`reference numerals 101-1, 102-1 and 103-1 designate their
`gate electrodes, 101-2, 102-2 and 103-2 designate their drain
`regions, and 101-3, 102-3 and 103-3 designate their source
`
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`the ion implantation of the low threshold
`regions. First,
`impurity is carried out as shown in FIG. 7A by using a low
`threshold mask 111 as shown in FIG. 8A. Second, the ion
`implantation of the medium threshold impurity is carried out
`as shown in FIG. 7B by using a medium threshold mask 112
`as shown in FIG. 8B. Thus, channel regions 104, 105 and
`106 with low, medium and high impurity concentrations
`respectively are formed. That is, the low threshold voltage,
`medium threshold voltage and high threshold voltage MOS
`transistors 101, 102 and 103 are formed which have the
`layout patterns as shown in FIG. 6A and the cross-sections
`as shown in FIG. 6B.
`
`FIGS. 9A—9J illustrate a specific embodiment of process
`steps of the fabrication method in accordance with the
`present invention as shown in FIGS. 7A and 7B.
`The outline of the steps of the fabrication process is as
`follows:
`
`(1) As shown in FIG. 9A, pMOS device regions 201 and
`nMOS device regions 202 are formed on a silicon
`substrate 200 and isolated from each other. Here,
`reference numerals 221 and 222 each designate an SiO2
`insulation layer.
`(2) As shown in FIG. 9B, after forming a resist mask M1
`with openings corresponding to a high threshold pMOS
`device region and a low threshold pMOS device region,
`the ion implantation of an n-type impurity
`(phosphorus) is carried out by using the mask M1,
`thereby forming regions 203, each having an impurity
`concentration of Npl, near the surface of the device
`regions 201.
`(3) As shown in FIG. 9C, after forming a resist mask M2
`with openings corresponding to a high threshold pMOS
`device region and a middle threshold pMOS device
`region,
`the ion implantation of the n-type impurity
`(phosphorus) is carried out by using the mask M2,
`thereby forming a region 204 with an impurity con-
`centration of Npm and a region 205 with an impurity
`concentration of (Npl+Npm), near the surface of the
`device regions 201. Thus, a pMOS device region 230 is
`formed which has the three types of the low, medium
`and high threshold voltage and whose ion impurity
`concentrations are Npl, Npm and (Npl+Npm),
`respectively, through steps (2) and (3).
`(4) As shown in FIG. 9D, after forming a resist mask M3
`with openings corresponding to a high threshold
`NMOS device region and a low threshold nMOS
`device region, the ion implantation of a p-type impurity
`(boron) is carried out by using the mask M3, thereby
`forming regions 206, each having an impurity concen-
`tration of an, near the surface of the device regions
`202.
`
`(5) As shown in FIG. 9E, after forming a resist mask M4
`with openings corresponding to a high threshold nMOS
`device region and a medium threshold nMOS device
`region,
`the ion implantation of the p-type impurity
`(boron) is carried out by using the mask M4, thereby
`forming a region 207 with an impurity concentration of
`Nnm and a region 208 with an impurity concentration
`of (an+Nnm), near the surface of the device regions
`202. Thus, an NMOS device region 240 is formed
`which has the three types of the low, medium and high
`threshold values and whose ion impurity concentra-
`tions are an, Nnm and (an+Nnm), respectively,
`through steps (4) and (5).
`(6) Subsequently, after forming a gate oxide film on the
`surface of the substrate 200, a p-type polysilicon is
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`6,111,427
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`7
`grown with boron doped thereinto on the gate oxide
`film in the pMOS device regions. The p-type polysili-
`con is patterned to form gate electrodes 209 in respec-
`tive pMOS device regions, as shown in FIG. 9E.
`(7) In a similar way, an n-type polysilicon is grown with
`doping phosphorus doped thereinto on the gate oxide
`film in the nMOS device regions. The n-type polysili-
`con is patterned to form gate electrodes 210 in respec-
`tive nMOS device regions, as shown in FIG. 9G.
`(8) As shown in FIG. 9H, after forming a resist mask M5
`with openings corresponding to pMOS device regions,
`the ion implantation of the p-type impurity (boron) is
`carried out, thereby forming high impurity concentra-
`tion source and drain regions 211 of the pMOS device.
`(9) As shown in FIG. 91, after forming a resist mask M6
`with openings corresponding to nMOS device regions,
`the ion implantation of the n-type impurity
`(phosphorus)
`is carried out,
`thereby forming high
`impurity concentration source and drain regions 212 of
`the NMOS device.
`
`(10) Then, after growing an insulation layer 223 on the
`entire surface, electrode windows are opened.
`Subsequently, a wiring metal layer is grown on the
`insulation layer 223. The wiring metal layer is pat-
`terned so as to form source and drain electrodes 213, as
`shown in FIG. 9].
`
`Thus are formed the low, medium and high threshold
`pMOS transistors 231, 232 and 233, and the low, medium
`and high threshold nMOS transistors 241, 242 and 243.
`FIG. 10 is a characteristic diagram illustrating relation-
`ships between the impurity concentration (cm'z) in a chan-
`nel region formed by the ion implantation and the threshold
`voltage Vm (V). If the low threshold voltage is set at 0.1 V
`and the medium threshold voltage is set at 0.2 V,
`it is
`possible to fabricate a high threshold voltage MOS transistor
`having a threshold voltage of about 0.4 V. This method offers
`an advantage that the three threshold MOS transistors can be
`fabricated by the same process as the fabrication for the two
`threshold MOS transistors. Thus, the present invention has
`an advantage that the number of the process steps is not
`increased and that the number of the masks is the same as
`
`that for fabricating the two threshold MOS transistors.
`Embodiment 2
`
`FIG. 11 shows a second embodiment of the present
`invention. In this embodiment, low threshold logic gates 150
`and 151 are interposed in a critical path between an input
`signal VIN and an output signal VOUT. In addition, a medium
`threshold logic gate 152 is interposed in a non-critical path
`to which a signal like a control signal is input. Furthermore,
`a high threshold power switching transistor 153, which is
`turned on and off by a sleep control signal, is connected
`between the supply voltage VDD and the Virtual VDD line
`which is connected to the low threshold logic gates 150 and
`151 and the medium threshold logic gate 152. This high
`threshold voltage transistor makes it possible to reduce the
`leakage current of each of the gates 150, 151 and 152,
`thereby achieving high operating speed and low power
`consumption in the operation mode, and low power con-
`sumption in the sleeping mode.
`Embodiment 3
`
`FIG. 12 is a block diagram showing a third embodiment
`of a logic circuit C2 in accordance with the present inven-
`tion