throbber
6,046,627
`[11] Patent Number:
`[19]
`United States Patent
`
`Itoh et al.
`[45] Date of Patent:
`Apr. 4, 2000
`
`USOO6046627A
`
`[54] SEMICONDUCTOR DEVICE CAPABLE OF
`OPERATING STABLY WITH REDUCED
`POWER CONSUMPTION
`
`[75]
`
`Inventors: KiyOO Itoh, Higashi-kururne; Hiroyuki
`Mizuno, Kokubunji, both of Japan
`
`[73] Assignee: Hitachi, Ltd” Tokyo, Japan
`
`[21] Appl. No.: 09/027,212
`
`[22]
`[30]
`
`Feb. 20’ 1998
`Flled'
`Foreign Application Priority Data
`
`7
`
`Feb. 28, 1997
`
`[JP]
`Japan
`........ 9045235
`
`Int. Cl.
`[51]
`..
`............................... G05F 1/10
`[52] US. Cl.
`..............
`. 327/546; 327/544; 327/534
`
`[58] Field of Search ..................................... 327/534, 535,
`327/544, 545, 546, 547; 326/35, 36
`
`[56]
`
`References Cited
`
`4,837,460
`5,148,393
`5,394,365
`
`U'S’ PATENT DOCUMENTS
`6/1989 Uchida .................................... 327/382
`9/1992 Furuyama ............... 365/149
`
`2/1995 Tsukikawa ......................... 365/189.09
`
`6/1995 Rasgtegar et al.
`5,422,591
`9/1995 Toyoshima et al.
`5,448,198
`5,583,457 12/1996 Horiguchi et al.
`5,748,029
`5/1998 Tomashini et al.
`
`...................... 327/409
`
`.
`327/530
`...................... 326/121
`..................... 327/389
`
`OTHER PUBLICATIONS
`
`.
`.
`.
`T. Kuroda et al, “Low—Power & Communication Signal
`Processing”, IEEE International Solid State Circuit, Digest
`of Technical Papers, 1996, pp. 166—167.
`S.
`Itoh, “Cho—eluesuai”, Baifukan, Nov. 5, 1994, pp.
`239—328.
`
`Primary Examiner—Kenneth B. Wells
`Assistant Examiner—An T. Luu
`Attorney, Agent, or Firm—Beall Law Offices
`
`[57]
`
`ABSTRACT
`
`The well voltage of a CMOS circuit having low-threshold-
`voltage MOSFETs is controlled when the power supply is
`turned on, during normal operation, and when the supply
`voltage is cut off. The CMOS circuit can thus operate stably
`with lower power consumption, because latching-up is
`reduced when the supply voltage is applied to the CMOS
`circuit or when the supply voltage is cut off, and subthresh-
`0101 current is decreased during normal Operation
`
`25 Claims, 23 Drawing Sheets
`
`HIGH-V
`PMOST
`
`v
`
`SUBSTRATE-
`
`
`0‘31
`
`
`
`VOLTAGE
`
`GENERATING AND
`
`
`
`CONTROLLING
`
`CIRCUIT VB
`
`
`
`0001
`
`AMD EX1042
`
`US. Patent No. 6,239,614
`
`AMD EX1042
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 1 0f 23
`
`6,046,627
`
`3PMOS
`
`LEI]
`
`
`
`
`SUBSTRATE-
`
`
` VOLTAGE
`GENERATING AND
`
`CONTROLLING
`
`CIRCUIT VB
`
`
`
`PERIOD OF
`
`TIME —»
`
`VOCI
`
`¢p, I)
`
`Nw,NP
`
`v
`
`C02
`
`FIG_ 2
`
`PERIOD OF
`APPLICATION
`OF POWER
`
`PERIOD OF
`CUT-OFF OF
`POWER
`
`OPERATION
`
`
`
`OF APPARATUS
`
`
`NORMAL
`STANDBY,
`NORMAL
`OPERATION
`SLEEPNON-
`OPERATION
`
`SELECTION
`
`OF CHIP,
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 2 0f 23
`
`6,046,627
`
`
`
`
`
` 1/0 MAIN DRAM CELLARRAY
`ClRCUlT
`(DARY)
`LG -LG
`(
`1
`4)
`V001 WL1 WL2 WL127 WL128
`.WVCC1NMOSPH VND
`DL
`DL
`
`NMOS VCC1PM03
`
`
`
`V001
`
`0003
`
`0003
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 3 0f 23
`
`6,046,627
`
`——————————————————————————————————————————————
`
`E
`
`5
`3
`s
`
`VBP(3 3V)
`
`VCC1(3 3V) E
`
`QPP(H'GH VT)
`
`(DP °——|
`CP
`4’ 0—1
`________ YQQZ
`
`0 ¢ Vap
`
`j
`s
`am
`
`In
`
`OUT
`
`:
`
`-
`
`s “*4
`2
`ON
`f
`0P w—l
`
`
`
`PW
`
`V001
`
`-
`
`QPN(HIGH VT)
`
`VB
`
`:
`
`s
`a
`
`——————————————————————————————————————————————
`
`VBN(-15V)
`
`(DP ‘1’ VBN
`
`f
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 4 0f 23
`
`6,046,627
`
`33v
`
`V001
`
`o
`
`V002
`
`---------------------
`
`NORMAL
`OPERATION
`
`NORMAL
`OPERATION
`
`NORMAL
`OPERATION
`
`T R -
`
`OFUPngENR
`SUPPLY
`
`STANDBY SLEEP,
`.
`NONOSFEIéEgION
`
`SUBSTRATE
`(WELL)
`REFRESH
`
`CUTOFF
`OF POWER
`
`FIG. 6
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 5 0f 23
`
`6,046,627
`
`Era
`
`44.
`
`1.....:.E
`
`w4_
`
`.‘
`
`NW
`
`IZIIII
`
`VCCZ
`
`Vss
`
`PW
`
`
`
`_mbnflflhflflhflhflfiflflhflfinflflflflflflkflfikflflflflflfiflfi.
`.................................................OMN3mCVmw.w.a.__m_M.IMS
`
`................................................._UWUWRRmoeouowm
`ImR.u.CLE)2».Am:m.._rNNmm
`
`finfifiwfimfififiL:
`
`..A_RRCG..AxDDHN
`
`PIIIIHHIIHHIIH-.tleA—m_..DHTOI
`‘IIIIIIIIa!...IIIIIIII.DDnlu.W444u_444NNHLKKKnKKKAAP._rESESEP
`‘DR‘RDLDL7“"OOCUC._CMCMAuRRF3
`
`ENu.
`
`UHmmm5mmA0MW.”
`
`V v V ‘
`M GATE ELECTRODE
`
`FIRST WIRING LAYER
`
`SECOND WIRING LAYER
`
`Z2
`
`|_' I: '_'.I ‘1
`
`DEEP N-WELL
`
`[:IP-WELL
`
`FIG. 7
`
`m
`
`OF PMOS
`
`E
`
`SURFACE HIGH-CONCENTRATION P-LAYER
`FOR SUPPLYING POWER TO SUBSTRATE
`OF NMOS
`
`0006
`
`0006
`
`
`
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 6 0f 23
`
`6,046,627
`
`OXIDE FILM
`
`ELEMENT
`ELEMENT
`ISOLATION
`E
`g
`ISOLATION
`~
`.’
`N-WELL.-
`=.
`-----------------------------------------------------------------------------
`
`
`
`
`ELEMENT
`ISOLATION
`
`GATE
`ELECTRODE
`
`FIRST WIRING
`A LAYER
`SECOND WIRING
`LAYER
`
`SOURCE AND DRAIN
`0F pMOS
`
`fl CONTACT HOLE
`
`I VIA HOLE
`
`""""" N-WELL
`
`FIG. 8(3)
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 7 0f 23
`
`6,046,627
`
`OXIDE FILM
`
`GATE
`OXIDE
`ELEMENT
`FILM
`ISOLATION
`---------------------------------------
`
`o
`
`ELEMENT 8““
`XIDE
`ISOLATION
`FILM
`(LOCOS)
`
`ELEMENT
`ISOLATION
`P-WELL (LOCOS)
`
`
`
`
`DEEP-N-WELL
`\ _____________
`
`GATE
`ELECTRODE
`FIRST WIRING
`\ \ LAYER
`N-WELL
`
`|:] P-WELL
`
`SOURCE AND DRAIN
`OF PMOS
`ZZ| SOURCE DRAIN OF NMOSFET
`'L' " 'I DEEP N-WELL
`
`FIG. 8(b)
`
`0008
`
`0008
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 8 0f 23
`
`6,046,627
`
`
`
`FIG. 9
`
`0009
`
`0009
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 9 0f 23
`
`6,046,627
`
`0T2 (1)
`F 13:660—555wa ' - -E
`i
`; 1.8V
`:
`:
`:‘pP—l
`:
`:
`i QPP
`'
`:
`.
`.
`I
`: ai‘4
`:
`I
`'
`'
`I
`:
`:
`:
`I Cfi_4
`I
`
`.
`'
`
`ARY1
`f ----------- E
`I
`:
`1
`:
`I
`1
`1
`.
`l
`:
`:
`I
`'
`I
`:
`:
`
`MC
`
`fAB
`I ' ' _ ' ' ":
`i
`_ i
`0&3; :
`'
`1
`:
`.
`_ I
`I
`CH
`:
`:
`G}
`I
`I
`L _______'
`
`.
`Au
`
`CLK :
`0p}
`:--\.---:
`CB
`
`FIG' 10(a)
`
`:
`i
`r ““““““
`5
`5
`a
`- ------------
`a
`MC
`
`'"ZZIIZIIE’WTIY"
`I __________
`050000 71
`_ _________P.09.).
`_
`”____[_A_R_Y_2___
`F
`firWLIzg
`I
`'_:
`:_ ________________:
`'_VYE2_5_5_________:
`2CT2(2)
`
`I __________'
`
`NVV 2
`
`:
`
`1.8V
`
`¢p—-—JO
`DON’T CARE
`V
`Ai,Aj \_\\\\\\\
`1.8V
`
`\—-
`
`
`
`FIG. 10(b)
`
`0010
`
`0010
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 10 0f 23
`
`6,046,627
`
`FIG. 11
`
`'N
`
`'CP
`
`Vcc
`
`V P
`
`|—¢p
`
`OPP
`NW
`
`OUT
`
`CN
`
`PW
`
`I'— .5;
`QPN
`
`VBN
`
`REFRESH
`uh.
`
`REFRESH
`REFRESH
`V P
`0"“
`n-M
`O O O I I T— . I OT
`
`¢P
`
`-
`VBN _F'l___ __I_l_
`¢P
`o o u o o
`VCC2
`I I o
`....._l
`LIL! "L—IL
`
`
`
`NW """"""F.". ._._|""" H"l—" ::;_|—’-—:L VaP+lVTP|
`
`
`L__JL|L...J——LF
`
`------------------------------------------ VCC2
`
`0011
`
`0011
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 11 0f 23
`
`6,046,627
`
`‘I
`
`
`4
`
`
`
`
`LR ILiJI“33$:'0
`[III4!
`Ir---_1
`
`‘'"I'I'I
`
`F'""'
`(IIIIIIIII
`
`
`
`
`
`
`fl
`
`
`
`CN
`
`g‘gm‘EESAND DRA'N
`GATE ELECTRODE
`SOURCE AND DRAIN
`-\\ FLRST WIRING LAYER
`/ / SECOND WlRING LAYER N OF PMOS
`‘2
`SURFACE HlGH-CONCENTRATION N-LAYER
`:N-WELL
`m 82%“??me POWER TO SUBSTRATE
`f
`z: CONTACT HOLE
`SURFACE HIGH-CONCENTRATION N-LAYER
`S FOR SUPPLYING POWER TO SUBSTRATE
`OF NMOS
`
`I VIA HOLE
`
`FIG. 13
`
`0012
`
`0012
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 12 0f 23
`
`6,046,627
`
`OXIDE FILM
`
`ELEMENT
`ISOLATION
`
`(LOCOS) N-WELL F'LM
`
`OGQBEE ELEMENT
`|SOLAT|O
`
`W GATE
`Mm ELECTRODE
`FIRST WIRING
`LAYER
`SECOND WIRING
`LAYER
`
`SOURCE AND DRAIN
`OF PMOS
`SURFACE HIGH-CONCENTRATION
`[Z2 N-LAYER FOR SUPPLYING POWER
`TO SUBSTRATE OF PMOS
`E CONTACT HOLE
`
`E-Il....-'§ N-WELL
`
`I VIA HOLE
`
`FIG. 14
`
`0013
`
`0013
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 13 0f 23
`
`6,046,627
`
`V002
`‘D
`HIGH vT
`
`vBP
`
`+— ¢P
`M CP
`V002 NW
`
`FIG. 15
`
`'N
`
`OUT
`
`PW
`
`W CN
`
`I—¢P
`
`VBN
`
`VBP
`
`V002
`
`|—¢P
`
`FIG. 16
`
`'N
`
`OUT
`
`INV
`
`0014
`
`0014
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 14 0f 23
`
`6,046,627
`
`
`FIG. 18(b)
`
`FIG. 18(3)
`
`0015
`
`0015
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 15 0f 23
`
`6,046,627
`
`V902
`
`(1.8V)
`
`,
`
`FIG. 19(3)
`
`OUT
`
`OUT
`
`6P4
`
`LOW v
`
`0016
`
`0016
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 16 0f 23
`
`6,046,627
`
`vcc1(H33v
`
`v
`OCC1IN
`
`QPU(IflGHVfl
`QNU(IMGHVT)
`
`FIG. 20(a)
`
`VCC1(33V)
`
`V0010-
`\0 —fi
`
`OPPGflGHVT)
`
`QP
`
`VBP
`
`IN
`
`ON
`
`OUT
`
`*‘*VBN
`
`VCC1
`$
`_g]—_ —L1
`
`QPNGflGHVT)
`
`FIG. 20(b)
`
`0017
`
`0017
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 17 0f 23
`
`6,046,627
`
`VBN
`0PM (HIGH VT)
`
`
`
`
`0N1 (LOW VT)
`
`DOUT
`
`
`0N2 (LOW VT)
`
`
`PW2
`
`
`
`FLOATING
`
`do, 30
`
`DOUT
`
`0 V
`
`TlME——->
`
`FIG. 21(b)
`
`0018
`
`0018
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 18 0f 23
`
`6,046,627
`
`3.3V
`
`3.3V
`
`6£ ‘1’
`
`(PP-I
`
`CP
`
`NW
`
`FIG. 22(a)
`
`3.3V
`
`¢P_1
`
`Qp (HIGH VT)
`
`3.3V
`
`-9-/——¢ —|
`
`NW
`
`ON (LOW VT)
`
`2.3V (VOL)
`
`FIG. 22(b)
`
`0019
`
`0019
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 19 0f 23
`
`6,046,627
`
`V
`
`CC1
`
`(DP
`
` MAIN
`
`CIRCUIT
`
`VCC1 (3.3V)
`
`VBN (-1 .5V)
`
`FIG. 24
`
`0020
`
`0020
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 20 0f 23
`
`6,046,627
`
`ch (3.3V)
`
`
`
`RING
`OSCILLATOR
`
`FIG. 25
`
`Vcc1 (3.3V)
`
`VREF
`
`Q
`
`vCL (2.3V)
`(=VREF)
`
`FIG. 26
`
`0021
`
`0021
`
`

`

`US. Patent
`
`Apr. 4,2000
`
`Sheet 21 0f 23
`
`6,046,627
`
`VCCI(>VCC2)
`
`V002
`
`CT1
`
`CIRCUIT
`
`(LOW VT)
`(LOW VT)
`
`CIRCUIT
`
`0022
`
`0022
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 22 0f 23
`
`6,046,627
`
`CT1
`
`(LOW VT)
`
`CIRCUIT
`
`MAIN
`
`FIG. 29
`
`Vcc1(1.8V)
`
`VCC2(1.2V)
`
`
`
`CT2
`
`CHIP
`
`0023
`
`0023
`
`

`

`US. Patent
`
`Apr. 4, 2000
`
`Sheet 23 0f 23
`
`6,046,627
`
`F———————._—____—_________...___—————___————_———-—
`
`
`
`0024
`
`0024
`
`

`

`6,046,627
`
`1
`SEMICONDUCTOR DEVICE CAPABLE OF
`OPERATING STABLY WITH REDUCED
`POWER CONSUMPTION
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates generally to semiconductor
`devices, and, more particularly, to semiconductor devices
`that combine high-speed performance and low power con-
`sumption.
`2. Description of the Related Art
`An example of reducing power consumption by substrate
`bias control is described in 1996 IEEE International Solid-
`
`State Circuit, Digest of Technical Papers,
`166—167.
`
`(1996), pp.
`
`With the recent popularity of low-power CMOS LSIs
`(Complementary Metal Oxide Semiconductor Large Scale
`Integrated circuits), a trend has developed to maintain high-
`speed operation by decreasing the threshold voltage VT of
`the MOSFETs as the operating or supply voltage is dropped.
`When the supply voltage drops to 2 V or lower and when the
`threshold voltage VT is decreased to 0.5 V or
`lower
`correspondingly, however, the subthreshold leakage current
`increases, whereby the transistor cannot be cut off com-
`pletely. Consequently, the standby current of the LSI chip
`increases, which represents a bottleneck in the design of a
`system that includes a battery-powered CMOS LSI chip.
`Furthermore,
`the current during normal operation also
`increases as the threshold voltage VT increases.
`In order to break the bottleneck, a well-known system
`achieves a high-speed operation by decreasing the threshold
`voltage of each of the MOSFETs in the chip during normal
`operation, and decreases the standby current by increasing
`the threshold voltage at the time of standby. Nevertheless,
`the following three problems exist in this system:
`(1) An overcurrent flows because of latching-up when the
`power supply is turned on, and the wiring in the CMOS LSI
`chip may fuse, or the normal supply voltage may become
`inapplicable as the load exceeds the current capacitance of
`the power supply. This problem is caused because the layout
`and connections of the circuit are designed so that
`the
`substrate (well) and source of the MOSFET are not at
`equipotential.
`For example, when a p-channel MOSFET (PMOSFET) is
`used for applying a positive supply voltage (e.g., 1.8 V) to
`the source (p-layer), the pn junction between the source and
`well is excessively biased in the forward direction because
`the well (n-well) remains at a floating 0 V just until the
`application of the supply voltage, thus causing latch-up of
`the CMOS. In the case of conventional CMOS LSI products
`at 2 V or higher,
`the pn junction is never biased in the
`forward direction as in the normal operation thereafter, even
`during the application of the supply voltage, since the well
`and source of the MOSFET are connected so that both are
`
`at equipotential as much as possible. Since the threshold
`voltage VT is constant at all times at a value of substantially
`0.5 or higher, moreover, there is no problem of subthreshold
`current.
`
`In the case of an n-channel MOSFET (NMOSFET), the
`problem is not so serious. When the supply voltage is
`applied to the drain, the substrate (p-well) of the NMOSFET
`is at a floating 0 V and the source is fixed to an earth
`potential of 0 V, because the pn junction, formed between
`the drain and the well, is not biased in the forward direction.
`However, there is a subthreshold current flowing between
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`the drain and source when the threshold voltage is 0.5 V or
`lower. By separately controlling the well and source, the
`threshold voltage in the CMOS LSI is lowered.
`(2) The time required to switch the normal mode to the
`standby mode and the time required to switch the standby
`mode to the normal mode are extremely long, on the order
`of Ms. Assuming that
`the substrate voltage is generated
`on-chip, by a charge pumping circuit for pumping the
`capacitor in the chip, the output current is limited to a low
`level. On the other hand, the transistor in the chip is used to
`connect
`the power supply terminals of the substrate in
`common, and consequently the total substrate capacitance
`has an extremely large value (100 pF or greater). Therefore,
`a large load (substrate) capacitance is driven by a substrate-
`voltage generating circuit whose current driving capability is
`low when the mode is switched, so that the response time
`tends to become longer.
`(3) The subthreshold current flows everywhere, even in
`the CMOS circuit, thus increasing the operating current of
`the whole chip. This problem exists because, in the inactive
`state, the threshold voltage of the transistor in the CMOS
`circuit or circuit block is low during normal operation.
`
`SUMMARY OF THE INVENTION
`
`The present invention controls the substrate or well volt-
`age of a transistor in a manner that solves the foregoing three
`problems.
`An object of the invention is to hinder the latching-up that
`occurs when the supply voltage is applied to a CMOS circuit
`that includes MOSFETs having a low threshold voltage, or
`when the supply voltage is cut off to the CMOS circuit.
`Another object of the invention is to decrease the sub-
`threshold current during normal operation.
`A further object of the invention is to realize low power
`consumption while maintaining high operating speed, for a
`CMOS circuit that operates at a voltage of 2 V or below, a
`CMOS LSI, and a semiconductor device using the CMOS
`circuit.
`
`In general, the invention achieves these and other objects
`by controlling the well voltage of a CMOS circuit when the
`power supply is turned on and when cut off, and during
`operation.
`In one embodiment of the invention, in which the CMOS
`circuit includes MOSFETs that cannot be cut off substan-
`
`tially satisfactorily during normal operation, after the well
`voltage is applied to the well of the CMOS circuit so that the
`MOSFETs can be cut off, the supply voltage is applied to the
`CMOS circuit.
`
`In another embodiment, after a third supply voltage
`(generated from a first supply voltage by a voltage conver-
`sion circuit) is applied as a well voltage to the well of the
`CMOS circuit, a second supply voltage is applied to the
`CMOS circuit.
`
`the invention provides a
`In yet another embodiment,
`circuit for fixing the well potential of the CMOS circuit, and
`a circuit for varying the well potential of the MOSFETs by
`capacitive coupling according to the variation of the input
`signal of the CMOS circuit.
`the invention provides a
`In still another embodiment,
`semiconductor device that includes a dynamic memory cell
`comprising a MOSFET, a capacitor, and a CMOS circuit,
`wherein the well potential of the MOSFETs constituting the
`CMOS circuit is subjected to a pulse variation, and wherein
`the substrate voltage of the dynamic memory cell is sub-
`stantially a DC supply voltage.
`
`0025
`
`0025
`
`

`

`6,046,627
`
`3
`In another embodiment, the invention provides a semi-
`conductor device including a static memory cell
`that is
`operated at a high voltage and is constituted by MOSFETs
`of high threshold voltage, and a CMOS circuit operated at a
`low voltage and constituted by MOSFETs having a low
`threshold voltage. The well potential of the MOSFETs
`constituting the CMOS circuit is subjected to a pulse varia-
`tion.
`
`the invention provides a
`In yet another embodiment,
`semiconductor device including at least one CMOS circuit,
`a standby control circuit, and a voltage conversion circuit,
`wherein the voltage generated by the voltage conversion
`circuit is supplied to the standby control circuit, and the
`standby control circuit varies the well potential of the
`CMOS circuit using the output of the voltage conversion
`circuit, depending on operating conditions. A capacitor
`having a capacitance that is greater than the capacitance of
`the well is connected to the output of the voltage conversion
`circuit.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 illustrates a CMOS semiconductor device con-
`
`structed according to the teachings of the present invention;
`FIG. 2 is a chart of timing diagrams for the CMOS
`semiconductor device shown in FIG. 1;
`FIG. 3 illustrates a CMOS LSI chip constructed according
`to the teachings of the present invention;
`FIG. 4 illustrates a section of the CMOS LSI chip of FIG.
`
`3;
`
`FIG. 5 illustrates a CMOS circuit constructed according
`to the teachings of the present invention;
`FIG. 6 is a chart of timing diagrams for the CMOS circuit
`shown in FIG. 5;
`FIG. 7 illustrates a layout for the circuit of FIG. 5;
`FIG. 8(a) illustrates a sectional view taken along line
`VIII—VIII of the layout shown in FIG. 7;
`FIG. 8(b) illustrates a sectional view of another layout of
`the circuit of FIG. 5, taken along line VIII'—VIII';
`FIG. 9 illustrates the selection and driving of a circuit
`subblock according to the present invention;
`FIG. 10(a) illustrates a line selection circuit;
`FIG. 10(b) illustrates a timing chart for the operation of
`the circuit of FIG. 10(a);
`FIG. 11 illustrates a CMOS inverter constructed accord-
`
`ing to the teachings of the present invention;
`FIG. 12 is a chart of timing diagrams for the CMOS
`inverter illustrated in FIG. 11;
`FIG. 13 is a layout for the circuit of FIG. 11;
`FIG. 14 is a sectional view taken along XIV—XIV of the
`layout shown in FIG. 13;
`FIG. 15 shows a modification of the circuit diagram
`shown in FIG. 11;
`FIG. 16 shows another modification of the circuit of FIG.
`11;
`FIG. 17 illustrates an example of an application of the
`present invention to an inverter series;
`FIG. 18(a) shows a PMOS NOR logic circuit constructed
`according to the teachings of the present invention;
`FIG. 18(b) shows an NMOS NOR logic circuit con-
`structed according to the teachings of the present invention;
`FIG. 19(a) shows an NMOS NAND logic circuit con-
`structed according to the teachings of the present invention;
`FIG. 19(b) shows another NMOS NAND logic circuit, in
`which precharged MOSFETs share a common well;
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`
`FIG. 19(C) shows a PMOS NAND logic circuit con-
`structed according to the teachings of the present invention;
`FIG. 20(a) shows an input buffer employing only high-
`threshold-voltage MOSFETs;
`FIG. 20(b) shows an input buffer employing low-
`threshold-voltage MOSFETs with high-threshold-voltage
`MOSFETs serving as switches;
`FIG. 21(a) shows a data output circuit constructed accord-
`ing to the teachings of the present invention;
`FIG. 21(b) shows timing diagrams for the circuit of FIG.
`21(a);
`FIGS. 22(a) and 22(b) show well driving circuits con-
`structed according to the teachings of the present invention;
`FIG. 23 shows a technique for applying a well voltage
`according to the present invention;
`FIG. 24 shows a conventional negative voltage power
`supply circuit;
`FIG. 25 shows a conventional booster power supply
`circuit;
`FIG. 26 shows a conventional step-down voltage power
`supply circuit;
`FIG. 27 shows an arrangement of a dual-power-supply
`chip constructed according to the teachings of the present
`invention;
`FIG. 28 shows a single-power-supply chip constructed
`according to the teachings of the present invention;
`FIG. 29 shows another single-power-supply chip con-
`structed according to the teachings of the present invention;
`FIG. 30 shows another arrangement of a dual-power-
`supply chip constructed according to the teachings of the
`present invention; and
`FIG. 31 shows the internal circuit of a dual-power-supply
`chip constructed according to the teachings of the present
`invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`In the preferred embodiment illustrated in FIG. 1, a circuit
`block CT1 operating with a high supply voltage VCC1 (e.g.,
`3.3 V) employs MOSFETs each having a selectable thresh-
`old voltage VT as high as 0.5 V,
`for example, during
`operation. Since the supply (operating) voltage is suffi-
`ciently high, high-speed operation is possible without drop-
`ping the threshold voltage to 0.1 V or
`thereabouts.
`Therefore, any subthreshold current that exists is sufficiently
`small to be ignored, without especially switching the thresh-
`old voltage during normal operation to the standby voltage,
`whereby the source of the transistor and its substrate can be
`connected at a common voltage.
`FIG. 1 also shows a substrate voltage generating and
`control circuit VB, which is operated with control signals (pp,
`(1).
`
`A circuit block CT2 operating with a low supply voltage
`VCC2 (e.g., 1.8 V), on the other hand, has internal transistors
`that are operated at high speed by dropping their threshold
`voltage to, for example, 0.1 V during normal operation. At
`standby,
`the threshold voltage must be increased to, for
`example, 0.5 V so as to reduce the standby current. The
`control of the threshold voltage is effected by controlling the
`substrates NW, PW of the transistors.
`The substrate voltage of the transistors in the circuit block
`CT2 is controlled as shown in FIG. 2.
`
`The voltages VBP, VBN of the substrates NW, PW are
`produced on the basis of the 3.3 V initially applied as VCCl,
`
`0026
`
`0026
`
`

`

`6,046,627
`
`5
`and the voltages are selected to have a value sufficient for the
`transistors in the circuit block CT2 to be cut off during the
`low-voltage operation. For example, VBP can be set at 3.3 V,
`and VBN at —1.5 V.
`First, the substrate voltage is applied to the circuit block
`CT2, and then the low supply voltage VCC2 is applied
`thereto. Consequently, since the threshold voltage of the
`transistors in the circuit block CT2 becomes sufficiently high
`in the course of applying the low supply voltage, no exces-
`sive chip current appears because the subthreshold current
`from each transistor is accumulated, and no latching-up
`occurs because the supply voltage of each transistor never
`comes into a floating state of about 0 V.
`Then, the operation is changed to the normal operation by
`decreasing the voltages VBP, VBN of the substrates NW, PW
`(to, for example, 2.3 V and —0.5 V or thereabout) in order to
`lower the threshold voltage of the transistors in the circuit
`block CT2. The threshold voltage is increased by boosting
`the substrate voltages VBP, VBN (to e.g., 3.3 V and —1.5 V)
`at standby, when a clock in the circuit block is stopped (fixed
`to a high or low level), at the time of sleeping, or at the time
`of non-selection of the chip, whereby an increase in power
`consumption due to the subthreshold current is reducible.
`When the power supply is cut off, the substrate voltages
`VBP, VBN are sufficiently boosted, and then the supply
`voltage VCC2 is turned off. Further, the supply voltage VCC1
`is also turned off. Thus, the order of application of the supply
`voltages is as follows: a timer sets a time interval following
`the application of the high supply voltage VCCl, and then the
`low supply voltage VCC2 is input.
`The circuit blocks CTl and CT2 may be constituted by
`different semiconductor chips, or they may be integrated
`onto a single chip.
`FIG. 3 shows an embodiment of the present invention in
`which the circuit block CTl and the circuit block CT2 are
`
`integrated onto one chip. In FIG. 3, an interface circuit I/O
`interfaces with the exterior of the chip; circuit blocks
`LGl—LG4 control the substrate voltage and are constituted
`by circuits that include transistors of low threshold voltage;
`a static memory SRAM includes a memory array SARY
`constituted of static memory cells; a power supply voltage
`VCCS supplies power to the memory cells; and a dynamic
`memory DRAM includes a memory array constituted by
`dynamic memory cells, each having MOSFETs and a
`capacitor, on one electrode of which is a capacitor electrode
`voltage VP. In the static and dynamic memory cells, DL, /DL
`represent data lines, and WL represents a word line. The
`memory arrays SARY and DARY may be constituted by
`transistors having a high threshold voltage, although such
`are not required.
`VB denotes a substrate-voltage generating circuit, which
`is controlled by a group of signals (¢P, /(|)P, (1)1, /(|)1, (1)2, /(|)2,
`(1)3, /(|)3, (1)4, /(|)4) from a substrate-voltage control circuit CLG;
`and VBA denotes a substrate-voltage generating circuit for
`supplying substrate voltages VPS, VNS, VND in the memory
`array SARY and in the memory array DARY. Each of the
`substrate voltages VPS, VNS, VND is normally a DC voltage
`or a semi-DC voltage (that is, a DC voltage with an AC
`ripple).
`The principal portion of the circuit block CTl including
`the substrate-voltage generating circuit VB, the substrate-
`voltage control circuit CLG, and the substrate-voltage gen-
`erating circuit VBA, is constituted by MOSFETs of high
`threshold voltage. Moreover, a high supply voltage VCC1 is
`supplied to the interface circuit I/O and the substrate-voltage
`generating circuit VB, whereas a low supply voltage VCC2
`is supplied to the other circuit blocks.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`The memory arrays SARY and DARY receive their sub-
`strate voltages in a different manner, because of the high
`density of the memory cells that make up the arrays (a
`high-density array is generally preferable because its area
`accounts for a large percentage of the area of the whole
`chip). For the high density of cells, the element isolation
`width needs narrowing. However, because the substrate bias
`system ordinarily gives a substrate voltage which is
`constant, with a substantially DC current, to the whole of the
`memory array simultaneously, the power consumption of the
`whole chip increases due to the large substrate capacitance.
`Thus, the element isolation characteristics are deteriorated
`when the substrate capacitance of this portion is driven.
`Therefore, the substrate voltages VNS? VPS in the memory
`array SARY are set at 0 V, respectively, and a voltage equal
`to the supply voltage VCCS, and the substrate voltage VND in
`the memory array DARY is substantially a DC voltage of
`about —1.5 V.
`
`The memory cells in the memory array SARY are flip-
`flops. If the threshold voltage of a transistor forming one of
`the flip-flops is too low,
`the subthreshold current in the
`memory cell increases. Since the memory array SARY is
`constituted by a number of cells, the current required for the
`memory array SARY as a whole amounts to a large value.
`Consequently, the cells are caused to operate at high speed
`by setting not only the threshold voltage of the transistor in
`each cell to be as high as about 0.5 V, but also to set a high
`supply voltage VCCS corresponding to the high threshold
`voltage. For example,
`the supply voltage VCCS can be
`effectively set to the supply voltage VCC1 (3.3 V), which is
`higher than the supply voltage VCC2 (1.8 V) because the
`number of power supplies is not increased.
`FIG. 4 is a schematic diagram of a sectional structure of
`the representative device of FIG. 3. In FIG. 4, capacitors in
`the memory array portion of the static memory SRAM and
`the memory array portion of the dynamic memory DRAM
`are omitted to make the drawing easy to understand.
`Next, a description will be given of the application of the
`invention to each interior circuit block shown in FIG. 3.
`
`FIG. 5 illustrates an embodiment of the present invention
`applied to a sub-circuit block LG (e.g. any of LGl—LG4) of
`FIG. 3. The substrate voltages (of substrates NW, PW) of the
`low-threshold voltage MOSFETs in the circuit block CT2
`are controlled by the circuit block CTl and a circuit block
`/CT1. According to this embodiment, capacitors CP and CN
`are employed in the control. The substrate-voltage
`generating/controlling circuit VB generates and outputs con-
`trol signals (¢P, q), /(|)P, /(|)) and the substrate bias voltages
`(VBP, VBN) from the high supply voltage VCC1 (e.g., 3.3 V).
`A p-channel transistor (PMOSFET) QPP and an n-channel
`transistor (NMOSFET) QPN have high threshold voltages.
`The timing diagrams of FIG. 6 explain the operation of
`the circuit shown in FIG. 5. The substrate bias voltages VBP,
`VBN are generally produced by the substrate-voltage
`generating/controlling circuit VB on the basis of the 3.3 V
`initially applied, and thus a description will be given of an
`example of substituting VCC1 (3.3 V) directly for the sub-
`strate bias voltage VBP.
`First,
`the substrate bias voltage VBP is applied to the
`circuit block CT2, and then the low supply voltage VCC2 is
`applied to the circuit block CT2. Therefore, the threshold
`voltage of each transistor in the circuit block CT2 is suffi-
`ciently high, as high as 0.5 V for example, in the course of
`applying the low supply voltage VCCZ. Thus, the pn junction
`is not biased in the forward direction. Consequently, the
`subthreshold current from the respective transistors does not
`accumulate and become an overcurrent, and no latching-up
`occurs.
`
`0027
`
`0027
`
`

`

`6,046,627
`
`7
`the control
`When the circuit enters normal operation,
`signals ¢Pand /(|)P are respectively set at a high voltage level
`H and a low voltage level L, so as to turn off the transistors
`QPP, QPN; then, the control signals (pp and /(|)P are respec-
`tively set at L and H. Thus, the capacitor coupling (CP, CN)
`causes the substrate voltages on the substrates NW, PW to
`change to, for example, about 2.3 V and —0.5 V, respectively.
`Since the voltage of the substrate decreases, the threshold
`voltage of each transistor in the circuit block CT2 also
`decreases and high-speed operation is made possible.
`In order to change the operation from this state to standby,
`sleeping, or non-selection of the chip, the control signals (pp
`and (pp are respectively set at L and H to turn on the
`transistors QPP, QPN; then, the control signals (1),, and/(1)1, are
`respectively returned to H and L. Since a deep voltage is
`applied to the substrate,
`the threshold voltage of each
`transistor in the circuit block CT2 becomes as high as 0.5 V.
`Consequently,
`the power consumption can be prevented
`from increasing because of the subthreshold current.
`Varying the substrate voltage according to the operating
`mode is advantageous in that it can be performed instantly
`by capacitive coupling through the capacitors CP, CN.
`However, the substrate voltage gradually decreases due to
`the pn junction leakage current of the source and drain, or
`the substrate current of the MOSFET. Particularly,
`the
`substrate current becomes large in proportion to the operat-
`ing frequency.
`The substrate (well) refresh shown in FIG. 6 is the
`operation of resetting the potential to 2.3 V and —0.5 V. The
`refresh operation is performed by, though not limited to,
`monitoring the substrate voltage. Alternatively, the time of
`refresh can be determined by a timer. The refresh operation
`is constituted by placing the circuit from the normal oper-
`ating state into the standby state, and then returning the
`circuit
`to the normal operating state again. Varying the
`refresh interval according to the magnitude of the substrate
`current (for example, making the refresh interval shorter
`when the chip is to perform a high-speed operation than
`when it is to perform a low-speed operation) is effective in
`improving the reliability of the operation.
`FIG. 7 shows an example of a layout of the transistors
`QPP, QPN and the capacitors CP, CN of FIG. 5. FIG. 8(a) is
`a sectional view taken along the lines VIII—VIII of the
`layout of FIG. 7. FIG. 8(b) is a sectional view taken along
`the lines VIII'—VIII' of the layout of FIG. 7. The substrate
`bias voltages VBP, VBN are connected to the sources of the
`transistors QPP, QPN via a second wiring layer (second metal
`wiring layer), respectively. The drains of transistors QPP,
`QPN are connected to the second wiring layer and output the
`substrate voltages to the substrates NW, PW of the main
`circuit. Moreover, the capacitors CP, CN are MOS capaci-
`tances.
`
`FIG. 9 shows an application of FIG. 5, in which one of
`two sub-circuit blocks CT2(1), CT2(2) is selectively driven.
`In a selected sub-circuit, for example, only the substrate-
`voltage generating circuits CT1(1), /CT1(1) associated with
`the sub-circuit block CT2(1) are selectively driven by a well
`block selection signal WB and a start clock (1), and the
`voltages of the wells NW(1), PW(1) which belong thereto
`are driven so that the threshold voltages of the MOSFETs in
`CT2(1) are dropped. Since the wells of the non-selected
`sub-circuit block CT2(2) is not driven, on the other hand, the
`threshold voltage of t

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket