6,034,563
`[11] Patent Number:
`[19]
`United States Patent
`
`Mashiko
`[45] Date of Patent:
`*Mar. 7, 2000
`
`US006034563A
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`HAVING REDUCED CURRENT LEAKAGE
`AND HIGH SPEED
`Inventor: Koichiro Mashiko, Tokyo, Japan
`[75]
`_
`.
`_
`_
`_
`_
`_
`_
`[73] Ass1gnee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`FOREIGN PATENT DOCUMENTS
`0 690 510
`1/1996 European Pat Off
`1—289137
`11/1989
`Japan ..................................... 327/544
`2:33:32
`alga:
`i252: ...................................... 327/544
`7—212217
`8/1995
`Japan .
`
`OTHER PUBLICATIONS
`
`I * l Notice:
`
`This. patent 1.5511de on a continued pros-
`ecution application filed under 37 CFR
`153(9) and 15 SUblef3t t0 the tWWW year
`patent
`term PTOVISIOHS 0f 35 U~S-C-
`154(a)(2).
`
`MTC MOS Logic Circuit Technology, “Intention of Decreas-
`ing the Electric Power Consumption for LSI—l V. Small
`Power Consumption High—speed Operation”, Densi—Gijutsu
`(Electronics Technology) 1994—9, pp. 29—32.
`
`[21] Appl. N0~3 08/651,588
`[22]
`Filed:
`May 22, 1996
`[30]
`Foreign Application Priority Data
`
`Oct. 19, 1995
`
`[JP]
`
`Japan .................................... 7—271574
`
`[51]
`
`Int. Cl.7 ........................................................ G05F 1/10
`
`.
`............................................. 327/544, 327/377
`
`[52] US. Cl.
`_
`[58] Fleld of Search ..................................... 327/390, 589,
`327/377, 170, 108—112, 544; 326/88, 80,
`81
`
`[56]
`
`_
`References Clted
`U.S. PATENT DOCUMENTS
`
`4,904,885
`2/1990 Yamada et al.
`......................... 327/536
`
`570419739
`8/1991 GO“) ~~~~~~~~~~~~~~~~~~~~~ 327/536
`
`57128560
`"""" 326/81
`7/1992 Chem et al‘
`
`5,159,214 10/1992 Okumura .......
`.. 326/110
`6/1994 Hardee et al. ............. 326/80
`5,321,324
`
`...... 327/534
`5,461,338 10/1995 Hirayama et al.
`.
`............................ 326/81
`5,528,173
`6/1996 Merritt et al.
`
`Primary Examiner—Kenneth B. Wells
`Attorney, Agent, 0r Firm—Oblon, Spivak, McClelland,
`Maier & Neustadt, PC.
`[57]
`ABSTRACT
`
`A SCWiCOHdUCtQY integrated dram induding a firSt MOS
`transistor supplied With a first power supply voltage and
`haVing a high threShOId VOHage; a second MOS ”9515“”
`supplied With a second power supply voltage and haVing the
`high threshold voltage; a logic circuit connected between the
`first transistor and the second transistor and including a
`plurality of MOS transistors having a low threshold voltage;
`a control circuit for generating a control signal when the
`logic circuit is in a standby state; and a voltage generating
`circuit for generating a first voltage which is a higher than
`the first power supply voltage and a second voltage which is
`a lower than the second power supply voltage, for supplying
`the first voltage to a gate of the first MOS transistor and for
`supplying the second voltage to a gate of the second MOS
`transistor when the logic circuit is in the standby state,
`thereby to decrease leakage current through the first and
`second transistors and through the logic circuit when in the
`standb state
`y
`
`'
`
`34 Claims, 11 Drawing Sheets
`
`0 VDD
`
`
`
`
`
`
`HIGH VOLTAGE
`GENERATING
`CIRCUIT
`
`
`
`
`
`VPP
`
`
`SELECTING
`CIRCUIT
`
`GND
`
` CONTROL
`CIRCUIT
`
`VDD
`
`SELECTING
`
`CIRCUIT
`VBB
`
`
`
`
`
`LOW VOLTAGE
`
`
`
`GENERATING
`CIRCUIT
`
`
`GND
`
`0001
`
`AMD EX1041
`
`US. Patent No. 6,239,614
`
`AMD EX1041
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Mar. 7,2000
`
`Sheet 1 0f 11
`
`6,034,563
`
`
`
`HIGH VOLTAGE
`GENERATING
`
`
`
`
`
`CIRCUIT
`
` CONTROL
`
`
` CIRCUIT
`
` LOW VOLTAGE
`
`GENERATING
`CIRCUIT
`
`
`
`GND
`
`FIG.2
`
`LOGIC CIRCUIT 11
`
`(SPJE)
`
`/E;L
`
`\IEDD
`
`29a
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 2 0f 11
`
`6,034,563
`
`FIG.3
`
`VDD
`
`S1
`
`GND
`
`VPP
`
`VDD
`
`5L
`
`GND
`
` 82
`
`VDD
`
`GND
`
`VDD
`
`: ................... ‘
`
`/SL
`
`GND ----------------------------------------------
`VBB -----------:
`
`ACTIVE TIME?
`
`STANDBY EACTIVE TIME
`TIME
`
`................................
`
`0003
`
`0003
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 3 0f 11
`
`6,034,563
`
`FIG.5
`
`VDD
`
`fl38a
`
`:‘ """"""""""""""""""""":
`
`K413
`
`i
`
`02
`
`__
`
`35
`
`flsab
`,439
`
`VPP
`
`FIG.6
`
`
`
`GND
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 4 0f 11
`
`6,034,563
`
`FIG.7
`
`16
`K
`
`
`
`/SL
`
`FIG.8
`
`LOGIC CIRCUIT 11
`
`k2
`
`GND
`
`29a
`
`/SL
`
`8
`
`26c 26b
`
`SL
`
`VDDV
`
`voo 9b
`2
`
`
`
`Q2
`
`TN1 TN2
`
`23 21a 21b 21C 21d
`
`22d 22C 22b
`
`22a
`
`24
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 5 0f 11
`
`6,034,563
`
`
`
`
` CONTROL
`CIRCUIT
`
`
`
`ACTIVE TIME I
`
`STANDBY - ACTIVE TIME
`TIME
`
`0006
`
`0006
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 6 0f 11
`
`6,034,563
`
`FIG.11
`
`
`
`
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 7 0f 11
`
`6,034,563
`
`FIG.13
`
`
`
`62 S4
`HIGH VOLTAGE
`GENERATING VPP
`
`CIRCUIT
`
`
`
`
`
` CONTROL
`CIRCUIT
`
`
`11
`
`
`
`LOW VOLTAGE vea
`GENERATING
`61
`CIRCUIT
`
`
`
`83
`
`FIG.14
`
`
`
`62
`
`HIGH
`VOLTAGE
`GENERATING
`CIRCUIT
`
`S4
`
`
`LOW
`VOLTAGE
`
`GENERATING
`CIRCUIT
`
`83
`
`
`
`63a
`
`
`
`63b
`
`0008
`
`0008
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 8 0f 11
`
`6,034,563
`
`FIG.15
`
`S2
`
` 81
`
`S3
`
`84
`
`I
`
`I
`
`GND -----------
`
`-----------------
`
`ACTIVE TIME I
`
`STANDBY I ACTIVE TIME
`TIME
`
`
`
`0009
`
`0009
`
`

`

`US. Patent
`
`Mar. 7, 2000
`
`Sheet 9 0f 11
`
`6,034,563
`
`
`
`0010
`
`0010
`
`

`

`US. Patent
`
`uMww%
`
`6,034,563
`
`meE
`
`
`
`>>O._ammM.EDOEO
`._OE.ZOO
`
`IQIm0<k._0>W.EDOEO.EDOEO0miGZ_._.<mm_Zm®OZF<¢mZmO”a>mmu<._...0>
`
`
`
`NF
`
`mm
`
`0011
`
`2mmmmm
`
`mmom
`vmmmwmmmno2mmommUNNU—moFNarmmm
`
`
`0011
`
`
`
`

`

`US. Patent
`
`Ddar.7,2000
`
`Sheetll 0f11
`
`6,034,563
`
`FIG.19
`PRIOR ART
`
`VDD
`
`SL—%
`
`Q1
`
`LOQHCCHRCUFF
`/
`
`VDDV
`
` /SL—+
`
`GND
`
`GNDv
`
`FIG.20
`PRIOR ART
`
`LOGKDCWKHMT11
`
`70 7b
`
`
`
`0012
`
`0012
`
`

`

`6,034,563
`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`HAVING REDUCED CURRENT LEAKAGE
`AND HIGH SPEED
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`integrated
`This invention relates to a semiconductor
`circuit, for example, a logic circuit, exhibiting decreased
`leakage current and increased processing speed during
`operation under control of a state signal from a control
`circuit.
`
`2. Discussion of Background
`In recent years, semiconductor integrated circuits are used
`in various technical fields thanks to advances in semicon-
`
`ductor technology. But the semiconductor integrated circuit,
`for example a microprocessor which includes CMOS
`technology, has two important problems involving input
`power consumption and device speed. It is difficult to solve
`the two problems and achieve low input power consumption
`and high speed performance at the same time, for example,
`using CMOS technology.
`Recently, MT—CMOS (Multi-Threshold CMOS) has been
`developed in an attempt to solve the two problems at the
`same time. FIG. 19 shows a circuit diagram of an
`MT—CMOS semiconductor integrated circuit which is used
`in a compact information terminal. The MT—CMOS inte-
`grated circuit includes a transistor having a high threshold
`voltage and a transistor having a low threshold voltage. In
`FIG. 19, the MT—CMOS semiconductor integrated circuit
`includes a p type MOS transistor Q1, an n type MOS
`transistor Q2, a potential line VDDV (hereinafter referred to
`as “VDDV”), a potential line GNDV (hereinafter referred to
`as “GNDV”), and a logic circuit 11 shown in dotted line. The
`transistors in the logic circuit have a low threshold voltage.
`The p type MOS transistor Q1 and the n type MOS transistor
`Q2 each have a high threshold voltage. VDDV is supplied
`with VDD via transistor Q1. GNDV is supplied with GND
`via transistor Q2. The logic circuit is composed of CMOS
`transistors powered by VDDV and GNDV. The gate of the
`p type MOS transistor Q1 is connected to a signal line SL,
`the source of the p type MOS transistor Q1 is supplied with
`VDD and the drain of the p type MOS transistor Q1 is
`connected to VDDV. The gate of the n type MOS transistor
`Q2 is connected to a signal line E, the drain of the n type
`MOS transistor Q2 is supplied with GND and the source of
`the n type MOS transistor Q2 is connected to GNDV. The
`signal lines SL and i are complementary digital signals.
`When the level of the signal line SL is a high level (“H”,
`e.g., VDD) and the level of the signal line K is a low level
`(“L”, e.g., GND),
`the logic circuit
`is non-conducting
`because both the p type MOS transistor Q1 and the n type
`MOS transistor Q2 are in the “OFF” state as the logic circuit
`11 is not supplied with VDD and GND. This state is the
`standby state.
`When the level of the signal line SL is “L” and the level
`of the signal line i is “H”, both the p type MOS transistor
`Q1 and the n type MOS transistor Q2 are “ON” and the logic
`circuit is supplied with VDD and GND. This state is the
`active state.
`
`A threshold voltage of the p type MOS transistor Q1 is
`—0.5——0.7 V and a threshold voltage of the n type MOS
`transistor Q2 is 0.5—0.7 V. The threshold voltage of each p
`type MOS transistor and that of each n type MOS transistor
`in the logic circuit are —0.2——0.3 V and 0.2—0.3 V, respec-
`tively. Because the threshold voltages of the MOS transistors
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`the logic circuit 11 can
`in the logic circuit 11 are low,
`perform logic functions at a low voltage (about 1 V) when
`in the active state. Because the threshold voltages of the p
`type MOS transistor Q1 and the n type MOS transistor Q2
`are at a higher voltage than that of the transistors in the logic
`circuit, the leakage current is decreased when in the standby
`state.
`
`Generally, when in the standby state, the leakage current
`(a subthreshold current) is generated in the MOS transistor.
`When the threshold voltage (Vth) decreases to 0.1 V, the
`leakage current increases at least 10 times. Therefore, in
`such a case,
`the leakage current of the MOS transistors
`having a low threshold voltage (in the logic circuit) becomes
`not less than 1,000 times that of the MOS transistors having
`a high threshold voltage (i.e., the p type MOS transistor Q1
`and the n type MOS transistor Q2).
`But, in FIG. 19, when in the standby state, the leakage
`current is not generated in the logic circuit, because the p
`type MOS transistor Q1 and the n type MOS transistor Q2
`are turned OFF by the signals SL and K. Thus,
`the
`semiconductor integrated circuit of FIG. 19 has only the
`leakage currents of the p type MOS transistor Q1 and the n
`type MOS transistor Q2 when in the standby state.
`Therefore, the input power consumption of the MT—CMOS
`logic circuit is low (1/1,ooo or less than that without the MOS
`transistors Q1 and Q2 (n-MT—CMOS)), because the leakage
`current of the logic circuit is not generated when in the
`standby state.
`FIG. 20 is a sectional view of a semiconductor chip to
`realize the CMOS transistor circuits. In FIG. 20, the semi-
`conductor chip includes a silicon substrate 1 in which a p
`type well 2 and an n type well 3 are formed. Aplurality of
`n type semiconductor regions 4a—4d are formed in the p type
`well 2, a plurality of p type semiconductor regions 5a—5d are
`formed in the n type well 3, a plurality of n type gate
`electrodes 6a—6c are formed on the p type well 2 through an
`insulating layer (not shown), a plurality of p type gate
`electrodes 7a—7c are formed on the n type well 3 through an
`insulating layer (not shown), an isolation layer 8 is formed
`to separate the p type well 2 and the n type well 3, a p type
`semiconductor region 9 have a higher impurity concentra-
`tion than the rest of the well 2 is formed in the p type well
`2, and an n type semiconductor region 10 have a higher
`impurity concentration than the rest of the well 3 is formed
`in the n type well 3.
`The logic circuit 11 includes a transistor T1 which con-
`sists of the n type semiconductor regions 4b, 4c and the gate
`electrode 6b, an transistor T2 which consists of the n type
`semiconductor regions 4c, 4d and the gate electrode 6c, a
`transistor T3 which consists of the p type semiconductor
`regions Sc, 5d and the gate electrode 7b and a transistor T4
`which consists of the p type semiconductor regions 5c, 5d
`and the gate electrode 76. The p type MOS transistor Q1
`consists of the p type semiconductor regions 5a, 5d and the
`gate electrode 7a. The n type MOS transistor Q2 consists of
`the n type semiconductor regions 4a, 4b and the gate
`electrode 6a. The gate electrode 7a and the gate electrode 6a
`are connected to the signal line SL and the signal line K,
`respectively. The n type semiconductor region 10 and the p
`type semiconductor region 9 are formed with a higher
`impurity concentration to provide the p type MOS transistor
`Q1 and the n type MOS transistor Q2 with a higher threshold
`voltage compared to that of the transistors T1, T2, T3 and
`T4.
`
`In the p type well 2, the n type semiconductor regions 4a,
`4b, 4c, 4d are formed at the same time by the same doping
`
`0013
`
`0013
`
`

`

`6,034,563
`
`3
`process. After that process, the p type semiconductor region
`9 is formed between n type semiconductor region 4a and n
`type semiconductor region 4b by ion implantation of alu-
`minum ions or boron ions. Then, in the n type well 3, the p
`type semiconductor regions 5a, 5b, Sc, 5d are formed at the
`same time by the same doping process. After that process,
`the n type semiconductor region 10 is formed between the n
`type semiconductor region 5a and the n type semiconductor
`region 5b by ion implantation of phosphorus ions.
`In the above semiconductor integrated circuit, a low input
`power consumption is desired. The threshold voltages
`(absolute value) of the p type MOS transistor Q1 and the n
`type MOS transistor Q2 are designed so as not to generate
`a large leakage current in the standby state between the
`power supply (VDD and GND) and the logic circuit 11.
`However,
`it is difficult to obtain the desired threshold
`voltage by the impurity doping process at the present level
`of technical skill in semiconductor manufacturing. As a
`result, not only is low input power consumption not
`achieved, but also manufacturing yield decreases due to
`sub-standard MOS transistors.
`
`the provision of low voltage threshold MOS
`Further,
`transistors and high voltage threshold MOS transistors on a
`common semiconductor substrate in the above semiconduc-
`
`tor integrated circuit results in a complicated manufacturing
`process due to the extra doping steps required to dope an
`impurity in the channel region 9 of the p type MOS transistor
`Q1 and in the channel region 10 of the n type MOS transistor
`Q2, as well as the concomitant masks required to dope the
`impurities in the semiconductor integrated circuit. As a
`result,
`the manufacturing productivity is remarkably
`reduced.
`
`Still further, it is not possible to ignore the ON resistance
`of the p type MOS transistor Q1 and that of the n type MOS
`transistor Q2 shown in FIG. 19. These ON resistances
`prevent high performance of the logic circuit. For example,
`even though the threshold voltage of the p type MOS
`transistor Q1 is reduced, or the threshold voltage of n type
`MOS transistor Q2 is increased, although the leakage cur-
`rent is thereby decreased, when the MOS transistors is in the
`ON state, the ability to drive the MOS transistors is pre-
`vented by such threshold voltages.
`SUMMARY OF THE INVENTION
`
`Accordingly, one object of the present invention is to
`provide a novel semiconductor integrated circuit exhibiting
`low input power consumption due to decreased the leakage
`current generated between a logic circuit and a power supply
`when in the standby state.
`Another object of this invention is to improve the perfor-
`mance speed of the logic circuit
`in the semiconductor
`integrated circuit when in the active state.
`These and other objects are achieved by providing a new
`and improved semiconductor integrated circuit including a
`first MOS transistor supplied with a first power supply
`voltage and having a high threshold voltage; a second MOS
`transistor supplied with a second power supply voltage and
`having the high threshold voltage; a logic circuit connected
`between the first transistor and the second transistor and
`
`including a plurality of MOS transistors having a low
`threshold voltage; a control circuit for generating a control
`signal when the logic circuit is in a standby state; and a
`voltage generating circuit for generating a first voltage
`which is a higher than the first power supply voltage and a
`second voltage which is a lower than the second power
`supply voltage, for supplying the first voltage to a gate of the
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`first MOS transistor and for supplying the second voltage to
`a gate of the second MOS transistor when the logic circuit
`is in the standby state, thereby to decrease leakage current
`through the first and second transistors and through the logic
`circuit when in the standby state.
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`A more complete appreciation of the invention and many
`of the attendant advantages thereof will be readily obtained
`as the same becomes better understood by reference to the
`following detailed description when considered in connec-
`tion with the accompanying drawings, wherein:
`FIG. 1 is a circuit diagram of a first embodiment of a
`semiconductor integrated circuit of the present invention.
`FIG. 2 is a sectional view of NAND gate 11a, p type MOS
`transistor Q1 and n type MOS transistor Q2 of the semi-
`conductor integrated circuit of FIG. 1.
`FIG. 3 is a timing diagram of signals indicating operation
`of the semiconductor integrated circuit of FIG. 1.
`FIG. 4 is a circuit diagram of the low voltage generating
`circuit 14 shown in FIG. 1.
`
`FIG. 5 is a circuit diagram of the high voltage generating
`circuit 13 shown in FIG. 1.
`
`FIG. 6 is a circuit diagram of the selecting circuit 15
`shown in FIG. 1.
`
`FIG. 7 is a circuit diagram of the selecting circuit 16
`shown in FIG. 1.
`FIG. 8 is a sectional view of a second embodiment of the
`
`logic circuit 11 as shown in FIG. 1.
`FIG. 9 is a circuit diagram of a third embodiment of the
`semiconductor integrated circuit of the present invention.
`FIG. 10 is a timing diagram of signals indicating opera-
`tion of the semiconductor integrated circuit of FIG. 9.
`FIG. 11 is a circuit diagram of a fourth embodiment of a
`semiconductor integrated circuit of the present invention.
`FIGS. 12(A) and 12(B) are alternative circuit diagrams of
`the semiconductor integrated circuit of the fourth embodi-
`ment.
`
`FIG. 13 is a circuit diagram of a fifth embodiment of a
`semiconductor integrated circuit of the present invention.
`FIG. 14 is a sectional view of the semiconductor inte-
`
`grated circuit of FIG. 13.
`FIG. 15 is a timing diagram of signals indicating opera-
`tion of the semiconductor integrated circuit of FIG. 13.
`FIG. 16 shows a circuit diagram of the low voltage
`generating circuit 61 of FIG. 13.
`FIG. 17 shows a circuit diagram of the high voltage
`generating circuit 62 of FIG. 13.
`FIG. 18 is a sectional view of a sixth embodiment of the
`
`semiconductor integrated circuit of the present invention.
`FIG. 19 shows a circuit diagram of the conventional
`semiconductor integrated circuit (MT-CMOS).
`FIG. 20 is a section view of a semiconductor chip to
`realize the conventional CMOS transistor circuits of FIG.
`19.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Referring now to the drawings, wherein like reference
`numerals designate identical or corresponding parts
`throughout the several views, various embodiments of the
`present invention are next described.
`
`0014
`
`0014
`
`

`

`6,034,563
`
`5
`
`(First Embodiment)
`A first embodiment of the present
`described with reference to FIGS. 1—7.
`
`invention is first
`
`FIG. 1 shows a circuit diagram of a semiconductor
`integrated circuit of the first embodiment of the present
`invention, including a logic circuit 11, a control circuit 12,
`a high voltage generating circuit 13, a low voltage generat-
`ing circuit 14, selecting circuits 15, 16, a power supply VDD
`(hereinafter referred to as “VDD”), a ground voltage GND
`(OV) (hereinafter referred to as “GND”), a potential power
`line VDDV, a potential ground line GNDV, a p channel
`transistor Q1, and an n channel transistor Q2. The logic
`circuit 11 includes a NAND gate 11a having transistors TP1
`(p type), TP2 (p type), TN1 (n type) and TN2 (n type). A gate
`of the p channel transistor Q1 is connected to a signal line
`SL from the selecting circuit 15. A gate of the n type MOS
`transistor is connected to a signal line i from the selecting
`circuit 14. The p type MOS transistor Q1 is connected to the
`logic circuit 11 through VDDV. The n type MOS transistor
`Q2 is connected to the logic circuit 11 through GNDV. The
`high voltage generating circuit 13 generates a voltage VPP
`higher than VDD, and supplies VPP to the selecting circuit
`15. The low voltage generating circuit 14 generates a voltage
`VBB lower than GND, and supplies VBB to the selecting
`circuit 16. The control circuit 12 is connected to the selecting
`circuit 15 through a signal line S1 and is connected to the
`selecting circuit 16 through a signal line S2. The selecting
`circuit 12 generates control signals for controlling a standby
`state and an active state in the logic circuit 11, and supplies
`the selecting circuits 15 and 16 with the control signals
`through the signal line S1 and S2. The selecting circuit 15
`selectively outputs VPP or GND in response to the level of
`the signal from the control circuit 12 through the signal line
`S1. The signal selected by the selecting circuit 15 is supplied
`to the gate of the p type MOS transistor Q1 through the
`signal line SL. The selecting circuit 16 selectively outputs
`VBB or VDD in response to the level of the signal from the
`transistor circuit 12 through the signal line S2. The signal
`selected by the selecting circuit 16 is supplied to the gate of
`the n type MOS transistor Q2. The transistors Q1 and Q2
`serve as switching circuits for supplying or cutting off VDD
`and GND to the logic circuit 11.
`FIG. 2 is a sectional view of the logic circuit (NAND gate)
`11, p type MOS transistor Q1 and n type MOS transistor Q2
`of the semiconductor integrated circuit of FIG. 1. The
`semiconductor integrated circuit is formed of CMOS tran-
`sistors.
`In FIG. 2,
`the semiconductor integrated circuit
`includes a plurality of n type semiconductor regions
`21a—21d formed in a p type well 2, a plurality of p type
`semiconductor regions 22a—22d formed in an n type well 3,
`a p type region 23 having a high impurity concentration, an
`n type region 24 having a high impurity concentration, a
`plurality of gate electrodes 2541—256 formed on the p type
`well 2 through an insulating layer (not shown), a plurality of
`gate electrodes 26a—27c formed on the n type well 3 through
`an insulating layer (not shown), an isolation layer 27 is
`formed to separate the p type well 2 and the n type well 3,
`a wiring 28 is for connecting the n type semiconductor
`region 21d and the p type semiconductor region 226, a
`wiring 29a which supplies GND to the n type semiconductor
`region 21a and the p type region 23, a wiring 29b which
`supplies VDD to the p type semiconductor region 22a and
`the n type region 24, a region 30 which is between the n type
`semiconductor region 21a and the n type semiconductor
`region 21b and has a higher impurity concentration than the
`rest of the p type well 2, a region 31 which is between the
`p type semiconductor region 22a and the p type semicon-
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`ductor region 22b and has a higher impurity concentration
`than the rest of the n type well 3.
`The n type MOS transistor TN1 includes the n type
`semiconductor regions 21b, 21c as a source region and a
`drain region, and the gate electrode 25b. The n type MOS
`transistor TN2 includes n type semiconductor regions 21C,
`21d as a source region and a drain region and the gate
`electrode 25C. The p type MOS transistor TP1 includes the
`p type semiconductor regions 22b, 226 as a source region
`and a drain region and the gate electrode 26b. The p type
`MOS transistor TP2 includes the p type semiconductor
`regions 22c, 22d as a source region and a drain region and
`the gate electrode 266. The wiring 28 connects the n type
`MOS transistor TN2 to the p type MOS transistors PN1 and
`PN2, a wiring connected to the n type semiconductor region
`21b corresponds to GNDV, and a wiring connected to the p
`type regions 22b and 22d corresponds to VDDV.
`The n type MOS transistor Q2 includes the n type
`semiconductor regions 21a, 21b as a source region and a
`drain region and the gate electrode 25a. The p type MOS
`transistor Q1 includes the p type semiconductor regions 22a,
`22b as a source region and a drain region, and a gate
`electrode 26a. The wiring 29a supplies GND to the n type
`semiconductor region 21a (the source region of the n type
`MOS transistor Q2). The wiring 29b supplies VDD to the p
`type semiconductor region 22a (the source region of the p
`type MOS transistor Q1). The wiring 29a supplies GND to
`the p type region 23 as a backgate electric potential of the
`MOS transistors which are formed on the p type well 2. The
`wiring 29b supplies VDD to the n type region 24 as a
`backgate electric potential of the MOS transistors which are
`formed in the n type well 3.
`A threshold voltage of the n type MOS transistors of the
`logic circuit 11 is 0.2 V—0.3 V. A threshold voltage of the n
`type MOS transistor Q2 is a higher voltage (for example 0.6
`V) than 0.2 V—0.3 V, because of the channel region 30. A
`threshold voltage of the p type MOS transistors of the logic
`circuit 11 is —0.2 V——0.3 V. Athreshold voltage of the p type
`MOS transistor Q1 is a lower voltage (for example —0.6 V)
`than —0.2 V——0.3 V, because of the channel region 31.
`Moreover, there may be other logic circuits in addition to
`or in the alternative to the NAND gate 11a included in the
`logic circuit 11. Although these logic circuits are not shown
`in FIG. 2, n type MOS transistors may be formed in another
`portion of the p type well 2, and p type MOS transistors may
`be formed in another portion of the n type well 3. Although
`the control circuit 12, the high voltage generating circuit 13,
`the low voltage generating circuit 14, the selecting circuits
`15 and 16 of FIG. 1 are not shown in FIG. 2, these circuits
`are likewise formed on the same semiconductor substrate.
`
`FIG. 3 is a timing diagram of the operation of the
`semiconductor integrated circuit in FIG. 1, showing signals
`on the signal lines S1, S2, SL and E.
`The control circuit 12 decides whether the logic circuit 11
`is to be set to an active state or a standby state based on a
`signal from another circuit (not shown). For example, in a
`personal computer, when the activity detection circuit
`detects no input activity for a fixed period of time from an
`input circuit, such as a key board or a mouse, etc., which
`would cause operation of the logic circuit 11, the activity
`detection circuit outputs a signal indicating that the personal
`computer or the logic circuit 11 is in the standby state. As
`FIG. 3 shows, when the logic circuit 11 is in the active state,
`the control circuit 12 applies VDD to the signal line S1, and,
`when the logic circuit 11 is in the standby state, the control
`circuit 12 applies GND to the signal line S1. When the logic
`circuit 11 is in the active state, the control circuit 12 applies
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`GND to the signal line S2. And, when the logic circuit 11 is
`in the standby state, the control circuit 12 applies VDD to the
`signal line S2.
`The selecting circuit 15 selects GND when the signal line
`S1 is a high level (VDD) or selects VPP when the signal line
`S1 is a low level (GND), and outputs a selected signal to the
`signal line SL. The selecting circuit 16 selects VBB when
`the signal line S2 is a high level (VDD) or selects VDD
`when the signal line S2 is a low level (GND), and outputs
`a selected signal to the signal line E. Therefore, as FIG. 3
`shows, the signal line SL is GND when the logic circuit 11
`is in the active state or the signal line SL is VPP when the
`logic circuit 11 is in the standby state. The signal line E is
`VDD when the logic circuit 11 is in the active state or the
`signal line E is VBB when the logic circuit 11 is in the
`standby state.
`The p type MOS transistor Q1 and the n type MOS
`transistor Q2 are in the ON state, when the logic circuit 11
`is in the active state, because the gate electrode of the p type
`MOS transistor Q1 is supplied with GND and that of the n
`type MOS transistor Q2 is supplied with VDD. Therefore, as
`VDDV is supplied with VDD and GNDV is supplied with
`GND, the logic circuit 11 executes logically using VDDV
`and GNDV as a power supply. The logic circuit 11 can
`operate even with a voltage smaller than VDD, because the
`MOS transistors in the logic circuit 11 can operate with a
`small threshold voltage (0.2 V—0.3 V in the absolute value).
`When the logic circuit 11 is in the standby state, both the
`p type MOS transistor Q1 and the n type MOS transistor Q2
`are in OFF state, because the gate electrodes of the p type
`MOS transistor Q1 and the n type MOS transistor Q2 are
`supplied with VPP and VBB, respectively.
`For the example of the n type MOS transistor, the leakage
`current is known to vary as a function of the following
`formula:
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`exp{(VGS—Vth)/s}
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`where VGS is a potential difference between the gate voltage
`and source voltage, Vth is a threshold voltage of the n type
`MOS transistor, and s is a voltage (fixed value) which needs
`to change a subthreshold leakage current value by a factor of
`ten. The smaller the voltage which is supplied to the n type
`MOS transistor Q2, the smaller the subthreshold leakage
`current. Similarly, the higher the voltage which is supplied
`to the p type MOS transistor Q1, the smaller the subthresh-
`old leakage current.
`Generally, during the manufacturing process, there is a
`very strong possibility that the threshold voltages of MOS
`transistors will vary and not be exactly as designed. For
`example, in FIG. 2, the regions 30 and 31 are doped with an
`impurity by a respective ion implantation. The actual thresh-
`old voltage of the region 30 may be 0.55 v, although the
`threshold voltage is designed to be 0.6 V. The actual thresh-
`old voltage of the region 31 may be —0.55 V, although the
`threshold voltage is designed to be —0.6 V.
`As the formula shows, if the threshold voltage decreases,
`the leakage current increases. In the example of the n type
`MOS transistor Q2, if the threshold voltage of the n type
`MOS transistor Q2 decreases by 0.05 V lower than the
`numerical design value,
`the leakage current remarkably
`increases over the numerical design value. When GND is
`supplied to the gate electrode of the n type MOS transistor
`Q2, a large leakage current of more than the maximum
`permissible transistor current is generated in the n type MOS
`transistor Q2. Therefore, the n type MOS transistor Q2 is
`rejected as sub-standard during quality control examination.
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`In this invention, the above large leakage current can be
`decreased, because the gate electrode of the n type MOS
`transistor Q2 is supplied with VBB which is a lower than
`GND.
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`Similarly, when the p MOS transistor Q1 is in OFF state,
`the above large leakage current can be decreased, because
`the gate electrode of the p type MOS transistor Q1 is
`supplied with VPP which is a greater than VDD. Therefore,
`the input power consumption can be decreased, and the
`manufacturing yield improves, because fewer MOS transis-
`tors are rejected.
`FIG. 4 shows a circuit diagram of the low voltage
`generating circuit 14, which includes a ring oscillator 35, a
`capacitor C1 and n type MOS transistors 36a and 36b. The
`ring oscillator 35 includes an odd number of inverters. The
`drain of the n type MOS transistor 36a is connected to the
`source of the n type MOS transistor 36b at a node N1. An
`output terminal of the ring oscillator 35 is connected to the
`node N1 and to the gate electrode of the n type MOS
`transistor 36b through the capacitor C1. The source of the n
`type MOS transistor 36a is connected to VBB, and the drain
`of the n type MOS transistor 36b is connected to GND. The
`source of the n type MOS transistor 36a is connected to its
`gate electrode, and the connecting point VBB is the output
`of the low voltage generating circuit 14. The threshold
`voltages of the n type MOS transistors 36a and 36b are each
`Vthn, which is lower than VDD.
`A high level of an output voltage of the ring oscillator 35
`is VDD. When the output voltage changes from the “L” level
`to “H” level (VDD), the n type MOS transistor 36a is in the
`OFF state. The potential of the node N1 becomes Vthn
`because the n type MOS transistor 36b changes to the ON
`state due to capacitive coupling of the capacitor C1. The
`capacitor C1 blocks direct current. Then, when the output of
`the ring oscillator 35 changes from the “H” level to the “L”
`level, ignoring parasitic capacitance,
`the potential of the
`node N1 changes to (Vthn—VDD) due to the capacitor
`coupling of capacitor C1. At this time, the n type MOS
`transistor 36a is in the ON state and the potential of the
`output terminal 37 becomes (Vthn—VDD)+Vthn=2 Vthn—
`VDD. On the other hand, the n type MOS transistor 36b is
`in the OFF state. Next, when the output of the ring oscillator
`35 cha