Hill 11111 1111 "III III“ lllll ||||| "Ill 1111 llllllllllllll III" 111
`
`[1800578 1 062A
`
`United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,781,062
`
`Mashiko et a].
`[45} Date of Patent: Jul. 14, 1998
`
`
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`
`[75]
`
`Inventors: Koichiro Mashiko: Kimio Ueda;
`Hiroaki Suzuki; Hiroyuki Morinaka.
`all of Tokyo. Japan
`
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha.
`Tokyo. Japan
`
`[21] Appl. No.: 582,416
`
`[22] Filed:
`
`Jan. 3, 1996
`
`[30]
`
`Foreign Application Priority Data
`
`Aug. 21. 1995
`
`[JP]
`
`Japan .................................... 7-211772
`
`........................................................ G05F 1/10
`Int. CLC‘
`[51}
`[52] US. Cl. ........................... 327/544: 329/546; 329/215
`[58] Field of Search ................................ 327/77. 87. 198.
`327/530. 538. 540. 541. 543. 545. 544.
`546. 199. 215. 217; 365/222
`
`[56]
`
`References Cited
`PUBLICATIONS
`
`Denshi Gijutsu. pp. 29—32. lunzo Yamada. et al.. “1v Low—
`Power High—Speed Operation MTCMOS Logical Circuit
`Technology” Sep. 1994.
`
`Primary Examiner—Timothy P. Callahan
`Assistant Examiner—Jung Ho Kim
`Attorney, Agent, or FErm—Oblon. Spivak. McClelland.
`Maier & Neustadt. RC.
`
`[57]
`
`ABSTRACT
`
`A logic circuit (1...) is connected between a virtual power
`supply line (VDDV) connected to an actual power supply
`(VDD) through a PMOS transistor (Q1) and a virtual
`grounding line (GNDV) connected to an actual ground
`(GND) through an NMOS transistor (Q2). During an active
`period. the transistors (Q1. Q2) are constantly conducting.
`and the virtual power supply line (VDDV) and virtual
`grounding line (GNDV) are at the power supply potential
`(VDD) and ground potential (GND). respectively. During a
`standby period. the transistors (Q1. Q2) periodically repeat
`conduction/non-conduction to charge and discharge the vir-
`tual power supply line (VDDV) and virtual grounding line
`(GNDV). suppressing power consumption while preventing
`loss of information held by the logic circuit (L).
`
`22 Claims, 8 Drawing Sheets
`
`VDD O
`
`STANDBY
`
`CONTROL
`
`SIGNAL
`SB
`
`GND
`
`
`AA_AA__~_--..-_-_-.1
`
`
`TIMER
`CIRCUIT
`
`0001
`
`AMD EX1039
`
`US. Patent No. 6,239,614
`
`AMD EX1039
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 1 of 8
`
`5,781,062
`
`SL
`
`VDD
`
`GND
`
`VDD
`
`GND --------------- ,
`
`VDD
`
`VDDV'
`GNDV
`
`
`I
`I
`I
`1
`i
`l
`g
`g
`3
`z
`:
`:
`GNDV
`f-----i
`?___-_;
`' —————:—
`-1
`
`:
`STANDBY PERIOD
`: ACTIVE PERIOD
`
`GND
`ACTIVE PERIOD
`
`FIG. 2
`
`
`
`
`TIMER
`CIRCUIT
`
`.................
`
`STANDBY
`
`CONTROL
`SIGNAL
`SB
`
`GND
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 2 of 8
`
`5,781,062
`
`FIG. 3
`
`VDDO
`
`STANDBY
`CONTROL
`
`POTENTIAL
`DETECTOR
`
`CIRCUIT
`
`
`
`A
`
`v
`
`SIGNAL
`SB
`
`GND
`
`FIG.4
`
`VDD _______________
`
`SL GND
`
`VDD
`
`GND
`
`VDD
`
`GND
`
`
`
`.
`
`,
`
`‘
`
`ACTIVE PERIOD I
`
`STANDBY PERIOD
`
`:ACTIVE PERIOD
`
`VDDV.
`
`GNDV
`
`0003
`
`0003
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 3 of 8
`
`5,781,062
`
`FIG. 5
`
`VDD.
`
`GND
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 4 0f 8
`
`5,781,062
`
`WD
`
`FIG. 6
`
`SL1
`
`GM
`
`VM
`
`GND --------------- ‘
`
`W0
`
`VDDVL
`
`Gm
`
`GNDVl
`
`SL2
`
`MD
`
`MD
`
`MD
`
`WD
`
`GM
`
`WD
`
`VDDVZ
`
`GNDV2
`
`ACTIVE PERIOD
`
`STANDBY PERIOD
`
`31mm PERIOD
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 5 of 8
`
`5,781,062
`
`VDD. STANDBY
`
`CONTROL
`
`SIGNAL
`SB
`
`GND
`
`0006
`
`0006
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 6 of 8
`
`5,781,062
`
`FIG. 8
`
`VDD. STANDBY
`
`CONTROL
`SIGNAL
`SB
`
`POTENTIAL
`DETECTOR
`CIRCUIT
`MONOSTABLE
`A MULTIVI BRATOR
`
`GND
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 7 0f 8
`
`5,781,062
`
`.VDD
`
`F I G. 9
`PRIOR ART
`
`
`VDDV
`
`__ HT
`LOW POWER CONSUMPTION
`DURING STANDBY
`
`
`
`
`1,T
`g fir
`{‘5'—""“““" EIGHT SPEED OPERATION
`:'
`'
`AT LOW VOLTAGE
`
`
`
`
`
`HT
`
`LOW POWER CONSUMPTION
`DURING STANDBY
`
`l 0
`F I G.
`PRIOR ART
`
`VDD _______________
`
`SI;
`
` GND
`
`VDD
`
`GND ............... l
`
`GND
`
`VDD
`
`VDDM
`
`(EIJI)\/
`
`ACTIVE PERIOD §
`
`STANDBY PERIOD
`
`i ACTIVE PERIOD
`
`0008
`
`0008
`
`

`

`US. Patent
`
`Jul. 14, 1998
`
`Sheet 8 of 8
`
`5,781,062
`
`VDD o
`
`
`STANDBY
`CONTROL
`SIGNAL
`55
`
`GND
`
`TIMER
`CIRCUIT
`
`'
`3COMBINATO-.
`3 RIAL AND E
`:SEQUENTIAL ; ...
`
`..................
`
`FIG.
`
`II
`
`0009
`
`0009
`
`

`

`5.78l.062
`
`l
`SEMICONDUCTOR INTEGRATED CIRCUIT
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a semiconductor inte—
`grated circuit and. more particularly. to a semiconductor
`integrated circuit intended for reduction in leakage current
`during standby by electrically disconnecting a power supply
`line and a grounding line from a logic circuit portion.
`without loss of logic stored in a sequential circuit such as a
`latch circuit and a register circuit of the logic circuit portion
`over a prolonged standby period.
`2. Description of the Background Art
`Recent advances in integration level and performance of
`semiconductor integrated circuits and wide expansion of the
`application fields thereof have presented a major technical
`consideration of how to reduce power consumption of the
`semiconductor integrated circuits or semiconductor chip
`bodies. The reduction in power consumption of the semi-
`conductor integrated circuit as well as the increase in
`performance has become an important technical factor that
`adds high values to the semiconductor integrated circuits
`because of the requirement to increase built-in battery life
`for a portable information equipment
`into which a
`telephone. an electronic notebook and a miniature personal
`computer are integrated. because of the requirement
`to
`reduce the size of a cooling device and a power supply
`device for a high-performance information processing
`equipment. and because of the social requirement for global
`environmental protection by eifective use of energy
`resources.
`
`One of the most effective approaches to reduce the power
`consumption of a semiconductor device is to decrease the
`voltage required to operate the semiconductor device. as will
`be described below. The power consumption of a CMOS
`(complementary metal—oxide-semiconductor) LSI (large
`scale integration) circuit is determined by:
`
`10:1ch VDD+Crf-VDDZ
`
`where Idc is a DC component. Cris a total capacitance in the
`LSI circuit. f is an average operating frequency. and VDD is
`a power supply voltage.
`Another approach having been proposed is an architecture
`designed. for example. to pause the operation of a circuit
`block. which is not required for some information
`processing. during the information processing to eifectively
`decrease the values CT and f. thereby decreasing a current 1.
`Unfortunately. the values CT and f in the above described
`equation are expected to keep increasing in the future
`because of the latest overall tendency toward advances in
`integration level and performance of the semiconductor
`integrated circuits.
`.
`On the other hand. there is a great likelihood that the
`power supply voltage VDD is decreased as technology
`advances. and approximately squared power supply voltage
`VDD has an effect on the power consumption. Thus. the
`power supply voltage VDD greatly influences the power
`consumption. Therefore. the development of low-voltage
`circuits is now in increasing demand to such an extent that
`the reduction in power consumption is equal to the reduction
`in voltage.
`For example. when a semiconductor device with a power
`supply voltage of 5 V is operated at 1.5 V.
`the power
`consumption is reduced to approximately one-tenth (more
`specifically. [1.5/5.012‘).
`
`2
`Unwanted secondary eifects which follow the reduction in
`power supply voltage are the reduction in transistor’s ability
`to feed current and the resultant reduction in operating
`speed. as will be described below.
`the difference
`To ensure a normal circuit operation.
`between on—state current and off-state current of a transistor
`must be about seven orders of magnitude. To ensure the
`difference. a threshold voltage Vth must not be indiscrimi-
`nately reduced. For example. the leakage current (current
`flowing when a transistor is off) of a typical existing
`transistor increases by more than one order of magnitude
`when the threshold voltage Vth is decreased by 0.1 V. For
`this reason. the reduction in threshold voltage Vth causes a
`sharp rise in current during standby (referred to hereinafter
`as standby current). resulting in great decrease in battery life
`of the portable information equipment.
`In this manner. the reduction in power supply voltage
`VDD does not correspondingly decrease the threshold volt-
`age Vth because of the need to suppress the standby current.
`Since the current feeding ability is proportional to (VDD—
`Vth)2. the reduction in power supply voltage VDD decreases
`the value (VDD—Vthf. resulting in decreases in current
`driving ability of the transistor and in circuit operation
`speed.
`In the background art. suppressing the power consump-
`tion by decreasing the power supply voltage makes it quite
`difficult to avoid the decrease in operation speed.
`To solve the problem. a semiconductor device using a
`plurality of threshold voltages. or a so-called multi—threshold
`CMOS (referred to hereinafter as a MTCMOS). has been
`proposed. Such technique is disclosed in “Electronic
`Engineering. The Nikkan Kogyo Shimbun Ltd.. September
`1994. pp.29—32”.
`FIG. 9 is a conceptual circuit diagram of the MTCMOS
`circuit. The MTCMOS circuit comprises two types of
`CMOS transistors: high threshold transistors HT and low
`threshold transistors LT.
`The high threshold transistor HT is a transistor for use in
`a general process. The low threshold transistor LT has a
`threshold voltage Vth set at 0.2 to 0.3 V which prevents a
`normally-on condition (the condition in which the transistor
`is not off when the gate voltage is zero) in the case of
`variations resulting from fabrication steps.
`In such a case. the leakage current of the transistor LT is
`more than 1000 times that of the transistor HT. The circuit
`comprised of only the transistors LT causes seriously
`increasing standby current. The MTCMOS circuit
`is
`designed to suppress the increase in standby current.
`Aplurality of logic circuits Li (i=1. 2. .
`.
`. ) are connected
`to a virtual power supply line VDDV and a virtual grounding
`line GNDV. The virtual power supply line VDDV is con-
`nected to an actual power supply VDD through a PMOS
`transistor Q1 which is the high threshold transistor HT.
`Likewise. the virtual grounding line GNDV is connected to
`an actual ground GND through an NMOS transistor Q2
`which is the high threshold transistor HT.
`A signal SL is applied to the gate of the transistor Q1
`whereas the inverted signal ST: is applied to the gate of the
`transistor Q2.
`FIG. 10 is a waveform chart illustrating the operation of
`the MTCMOS circuit of FIG. 9. During an active period. the
`signal SL is at the ground potential GND (the same reference
`character is used to represent the ground GND and the
`ground potential GND) and the signal fl is at the power
`supply potential VDD (likewise. the same reference char-
`acter is used to represent the power supply VDD and the
`power supply potential VDD).
`
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`0010
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`

`3
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`4
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`5.781.062
`
`During the active period. the PMOS transistor Q1 and
`NMOS transistor Q2 are on. and the virtual power supply
`line VDDV and virtual grounding line GNDV are connected
`to the power supply VDD and ground GND. respectively.
`Thus.
`the virtual power supply line VDDV.
`the virtual
`grounding line GNDV. and the logic circuits L, receive
`current through a low-resistance current path. permitting
`high-speed operation when the power supply voltage is low.
`During a standby period. the signal SL is at the power
`supply potential VDD and the signal E is at the ground
`potential GND. Then. the transistors Q1 and Q2 are both off.
`The power supply VDD and ground GND are electrically
`disconnected from the logic circuits Li comprised of the
`transistors LT. and the leak current of the whole circuit is
`generated only in the transistors Q1 and Q2 which are the
`transistors HT. Since the transistor LT consumes more power
`as above described. the MTCMOS circuit may reduce a
`greater amount of power consumption during standby than
`the circuit comprised of only the transistors LT.
`The conventional semiconductor device intended for low
`voltage operation is constructed as above described During
`the standby period. the virtual power supply line VDDV and
`Virtual grounding line GNDV are electrically disconnected
`from the actual power supply VDD and actual ground GND.
`respectively. into a high impedance state.
`Over a prolonged standby period. current leaks from the
`virtual power supply line VDDV and virtual grounding line
`GNDV through the transistors LT forming the logic circuits
`L. The above stated large leakage current of the transistors
`LT causes the potentials of the virtual power supply line
`VDDV and virtual grounding line GNDV to approach each
`other with time.
`
`In this case. there is a particularly increasing danger that
`a sequential circuit (including a memory circuit) for storing
`logic therein. such as a register circuit. a latch circuit. and a
`flip-flop circuit. included in the logic circuits Li may no
`longer hold the logic thereof to lose the information stored
`therein. This causes the semiconductor device not to be
`returned to the original state when the standby period is
`changed to the active period. resulting in considerable
`inconvenience for practical use.
`
`SUMMARY OF THE INVENTION
`
`According to a first aspect of the present invention. a
`semiconductor integrated circuit comprises a first power
`supply. a first power supply line for functioning to hold
`electrical charge. a first switch having a first end connected
`to the first power supply. and a second end connected to the
`first power supply line. and at least one logic circuit includ—
`ing a sequential circuit connected to the second end of the
`first switch through the first power supply line. wherein the
`first switch is constantly conducting during a first period
`over which the logic circuit is active. and the first switch is
`intermittently conducting during a second period over which
`the logic circuit is on standby.
`Preferably. according to a second aspect of the present
`invention. the at least one logic circuit includes a plurality of
`logic circuits.
`Preferably. according to a third aspect of the present
`invention. the semiconductor integrated circuit further com-
`prises a timer for generating a control signal for controlling
`conduction of the first switch during the second period.
`Preferably. according to a fourfli aspect of the present
`invention. the semiconductor integrated circuit further com-
`prises a potential detector circuit for detecting a first poten—
`tial which is the potential of the first power supply line. the
`
`potential detector circuit bringing the first switch into con-
`duction when the first potential falls outside a predetermined
`range during the second period.
`Preferably. according to a fifth aspect of the present
`invention. the semiconductor integrated circuit further com—
`prises a second power supply. a second power supply line for
`functioning to hold electrical charge. a second switch having
`a first end connected to the second power supply. and a
`second end connected to the second power supply line. and
`the sequential circuit being connected to the second end of
`the second switch through the second power supply line.
`wherein conduction/non-conduction of the second switch
`coincides with conduction/non-conduction of the first
`switch.
`
`Preferably. according to a sixth aspect of the present
`invention. the logic circuit further includes a combinational
`circuit. the semiconductor integrated circuit further com-
`prises a second switch having a first end connected to the
`first power supply. and a second end connected to the
`combinational circuit. and the second switch is constantly
`conducting during the first period. and the second switch is
`constantly non-conducting during the second period.
`Preferably. according to a seventh aspect of the present
`invention. the semiconductor integrated circuit further com-
`prises a second power supply. a second power supply line for
`functioning to hold electrical charge. a third switch having
`a first end connected to the second power supply. and a
`second end connected to the second power supply line. a
`fourth switch having a first end connected to the second
`power supply. and a second end. the sequential circuit being
`connected to the second end of the third switch through the
`second power supply line. and the combinational circuit
`being further connected to the second end of the fourth
`switch. wherein conduction/non—conduction of the third
`switch coincides with conduction/non-conduction of the first
`switch. and wherein conduction/non-conduction of the
`fourth switch coincides with conduction/non—conduction of
`the second switch.
`
`According to an eighth aspect of the present invention. a
`semiconductor integrated circuit comprises a power supply
`for providing a predetermined potential. a power supply line
`for functioning to hold electrical charge. and a logic circuit
`including a sequential circuit. the sequential circuit being
`constantly connected to the power supply through the power
`supply line during a first period. the sequential circuit being
`intermittently connected to the power supply through the
`power supply line during a second period
`Preferably. according to a ninth aspect of the present
`invention. the logic circuit further includes a combinational
`circuit. the combinational circuit being constantly connected
`to the power supply during the first period. the combina—
`tional circuit being constantly disconnected from the power
`supply during the second period.
`The semiconductor integrated circuit according to the first
`aspect of the present invention is not required to drive the
`logic circuit during the second period but must hold the state
`generated during the first period previous to the second
`period so as to prevent malfunction of the sequential circuit
`of the logic circuit during the first period subsequent to the
`second period. Since the first power supply is intermittently
`connected to the sequential circuit during the second period.
`power consumption is suppressed and the state of the
`sequential circuit is held by the application of electrical
`charge to the first power supply line.
`In the semiconductor integrated circuit according to the
`second aspect of the present invention. when the plurality of
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`
`0011
`
`

`

`5
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`5.78LO62
`
`logic circuits are on standby. the electrical charge which
`prevents malfunction of all logic circuits may be applied to
`the first power supply line only by actuating the first switch.
`In the semiconductor integrated circuit according to the
`third aspect of the present invention. the first switch may be
`automatically intermittently brought into conduction during
`the second period.
`In the semiconductor integrated circuit according to the
`fourth aspect of the present invention. the electrical charge
`sufficient for the sequential circuit to hold the state for the
`first period may be constantly present on the first power
`supply line during the second period.
`In the semiconductor integrated circuit according to the
`fifth and seventh aspects of the present invention. the second
`power supply is intermittently connected to the sequential
`circuit. Thus. power consumption is suppressed and the state
`of the sequential circuit is held by the application of elec—
`trical charge to the second power supply line.
`In the semiconductor integrated circuit according to the
`sixth aspect of the present invention. the combinational
`circuit whose output is determined only by the state of the
`currently applied signal need not hold the signal state for the
`first period previous to the second period during the second
`period and need not be provided with electrical charge. The
`semiconductor integrated circuit is not required to en sure
`electrical charge for the logic circuit
`indiscriminately
`during. the second period and does not apply electrical
`charge to the combinational circuit. thereby further sup-
`pressing power consumption.
`In the semiconductor integrated circuit according to the
`eighth aspect of the present invention. the logic circuit is
`driven to be active during the first period. The logic circuit
`is on standby and need not be driven during the second
`period. but must hold the state generated during the first
`period previous to the second period so as to prevent
`malfunction of the sequential circuit during the first period
`subsequent
`to the second period The power supply is
`intermittently connected to the power supply line during the
`second period so that the electrical charge which allows the
`retention of the state of the sequential circuit may present on
`the power supply line. thereby suppressing power consump-
`tion.
`
`In the semiconductor integrated circuit according to the
`ninth aspect of the present invention.
`the combinational
`circuit whose output is determined only by the state of the
`currently applied signal need not hold the state for the first
`period previous to the second period during the second
`period. Thus. it is not necessary to previously apply elec-
`trical charge to the combinational circuit in the logic circuit
`which is on standby during the second period. The semi-
`conductor integrated circuit is not required to ensure elec-
`trical charge for the logic circuit indiscriminately during the
`second period and does not apply electrical charge to the
`combinational circuit.
`thereby further suppressing power
`consumption.
`The present invention has been made to solve the problem
`of a sequential circuit which no longer returns to the original
`state during an active period after a prolonged standby
`period. It is therefore an object of the present invention to
`provide a semiconductor device which operates at high
`speeds at a low voltage during an active period and which
`suppresses a leakage current during a standby period as well
`as achieving a reliable operation during the subsequent
`active period.
`These and other objects. features. aspects and advantages
`of the present invention will become more apparent from the
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`following detailed description of the present invention when
`taken in conjunction with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a waveform chart illustrating operation tinting of
`a first preferred embodiment according to the present inven-
`tion:
`
`FIG. 2 is a circuit diagram of a second preferred embodi~
`ment according to the present invention:
`FIG. 3 is a circuit diagram of a mird preferred embodi—
`ment according to the present invention:
`FIG. 4 is a waveform chart illustrating operation timing of
`the third preferred embodiment according to the present
`invention;
`
`FIG. 5 is a circuit diagram of a fourth preferred embodi-
`ment according to the present invention:
`FIG. 6 is a waveform chart illustrating operation timing of
`the fourth preferred embodiment according to the present
`invention:
`
`FIG. 7 is a circuit diagram of a fifth preferred embodiment
`according to the present invention;
`FIG. 8 is a circuit diagram of a sixth preferred embodi-
`ment according to the present invention:
`FIG. 9 is a conceptual circuit diagram of an MTCMOS
`circuit:
`
`FIG. 10 is a waveform chart illustrating operation of the
`MTCMOS circuit.
`
`FIG. 11 is a block diagram of an embodiment of the
`present invention supporting a circuit having combinatorial
`and sequential circuit elements.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`First Preferred Embodiment
`FIG. 1 is a waveform chart illustrating operation timing of
`a first preferred embodiment according to the present inven-
`tion. The first preferred embodiment is applied to the MTC—
`MOS circuit shown in FIG. 9. that is. to the MTCMOS
`circuit which comprises a power supply VDD providing a
`power supply potential VDD. a ground GND providing a
`ground potential GND. 3 virtual power supply line VDDV.
`a virtual grounding line GNDV. a high threshold PMOS
`transistor Q1 having a source connected to the power supply
`VDD and a drain connected to the virtual power supply line
`VDDV. a high threshold NMOS transistor Q2 having a
`source connected to the ground GND and a drain connected
`to the virtual grounding line GNDV. and a plurality of logic
`circuits Ll- (i=1. 2. .
`.
`. ) connected to the drain of the PMOS
`transistor Q1 through the virtual power supply line VDDV
`and connected to the drain of the NMOS transistor Q2
`through the virtual grounding line GNDV. The logic circuits
`Li are formed by low threshold transistors LT.
`Each of the logic circuits Li includes a sequential circuit
`which needs previous logic to determine present logic. The
`virtual power supply line VDDV has a capacitor CV parasitic
`thereon. and the virtual grounding line GNDV has a capaci—
`tor Cz7 parasitic thereon. FIG. 11 is a block diagram of the
`present invention illustrating a logic circuit Li including
`combinatorial and sequential logic.
`An active period is a period over which the logic circuits
`Ll. must practically perform logic processing. and a standby
`period is a period over which the logic circuits Li need not
`perform logic processing. A system for driving a semicon-
`ductor integrated circuit
`including the MTCMOS circuit
`determines the operating conditions (for example. a key
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`entry wait time of a personal computer. a wait state of a
`portable telephone. and the like) of the system to accord-
`ingly apply a control signal to the semiconductor integrated
`circuit. thereby determining which one of the active and
`standby periods is set. Signals SL and E are produced in the
`semiconductor integrated circuit in response to the control
`signal. During the standby period. the transistors Q1 and Q2
`are off to suppress leakage current in the logic circuits L,.
`During the standby period specified by the system in the
`background art. since the signals SL and ST: in the semi—
`conductor integrated circuit always hold the potentials VDD
`and GND. respectively. the transistors Q1 and Q2 are 011° and
`the Virtual power supply line VDDV and virtual grounding
`line GNDV are electrically disconnected from the actual
`power supply VDD and actual ground GND. respectively.
`Thus. the prolonged standby period specified by the system
`lowers the potential of the virtual power supply line VDDV
`and raises the potential of the virtual grounding line GNDV
`with time until the potential difference therebetween finally
`becomes very small. resulting in losses of potential infor—
`mation (logic) held by a latch. a register. a flip-flop. and the
`like.
`
`In this preferred embodiment. however. during the
`standby period specified by the system the signals SL and
`ST are intermittently set to active—period potentials. that is.
`the potentials GND and VDD. respectively. and the transis-
`tors Q1 and Q2 produce intermittent conduction between the
`actual power supply VDD and virtual power supply line
`VDDV and between the actual ground GND and virtual
`grounding line GNDV. respectively. This allows the decreas-
`ing potential of the virtual power supply line VDDV and
`increasing potential of the virtual grounding line GNDV to
`stop halfway and return to the original potentials during the
`standby period as shown in FIG. 1.
`This means that electrical charge is fed to the parasitic
`capacitance CV on the virtual power supply line VDDV
`(charging) and electrical charge is emitted from the parasitic
`capacitance CO on the virtual grounding line GNDV
`(discharging). Thus. the virtual power supply line VDDV
`and virtual grounding line GNDV may feed electrical charge
`required for logic storage to the logic circuits L,- comprised
`of the transistors LT having a large leakage current. particu-
`larly to the sequential circuits thereof.
`Further. since the plurality of logic circuits L. are con—
`nected to the virtual power supply line VDDV and virtual
`grounding line GNDV. the intermittent charge supplement
`during the standby period requires only to function the
`transistors Q1 and Q2 as switches but need not be pmformed
`on each of the plurality of logic circuits L...
`Therefore. the state of the logic circuit L is returned to
`that for the active period after a prolonged standby period.
`Ease of use and performance are not deteriorated when a
`semiconductor integrated circuit is used which frequently
`repeats the active and standby conditions.
`Second Preferred Embodiment
`
`FIG. 2 is a circuit diagram of a second preferred embodi-
`ment according to the present invention. A semiconductor
`integrated circuit (chip) 101 is connected to the (actual)
`power supply VDD and the (actual) ground GND and
`receives a standby control signal SB from a system not
`shown.
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`The chip 101 comprises the Virtual power supply line
`VDDV. the virtual grounding line GNDV. the transistors Q1
`and Q2. and the logic circuits L in the same manner as the
`first preferred embodiment to form the arrangement of FIG.
`9. The chip 101 further comprises a timer circuit 11 and
`inverters 12 and 13.
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`The system instructs the chip 101 to set the standby period
`by using the standby control signal SB. Upon receipt of the
`standby control signal SB. the timer circuit 11 applies an
`initial high level (e.g.. the potential VDD) to the inverter 12.
`The inverter 12 inverts the received signal logic to output the
`signal S—L which is thus at the potential GND in the initial
`state. On the other hand. the inverter 13 inverts the received
`signal logic to output the signal SL which is thus at the
`potential VDD in the initial state. As described in the first
`preferred embodiment. the transistors Q1 and Q2 are off
`during the standby period.
`The timer circuit 11 then starts clocking. and applies a low
`level (e.g..
`the potential GND) to the inverter 12 for a
`predetermined drive period after an elapse of a predeter—
`mined quiescent period. Thus. the inverter 12 outputs the
`signal SE at the potential VDD and the inverter 13 outputs
`the signal SL at the potential GND. This causes the transis-
`tors Q1 and Q2 to turn on to charge the virtual power supply
`line VDDV having a decreased potential up to the potential
`VDD and to discharge the virtual grounding line GNDV
`having an increased potential down to the potential GND.
`After a lapse of the drive period. the timer circuit 11
`returns to the initial state to output the high level again
`during the predetermined quiescent period. In this manner.
`intermittently bringing the chip 101 into the active state even
`during the standby period prevents the loss of logic of the
`sequential circuits of the logic circuits L,-.
`The system instructs the chip 101 to set the active period
`again by using the standby control signal SB. Upon receipt
`of the standby control signal SB. the timer circuit 11 applies
`a constantly low level output to the inverter 12. and the
`signals SL and 5—1. are at the potentials GND and VDD.
`respectively. Then the transistors Q1 and Q2 turn on. and the
`Virtual power supply line VDDV and virtual grounding line
`GNDV function as low—impedance power supply line and
`grounding line. respectively. allowing high—speed circuit
`operation of the chip 101.
`In the above stated operation. the timer circuit 11 may be
`quiescent when active or used to other purposes. The timer
`circuit 11 may be readily constructed by using a delay
`element.
`
`As hereinabove described. the second preferred embodi-
`ment may embody the generation of the signals SL and
`i for providing the effects of the first preferred embodi-
`ment.
`Third Preferred Embodiment
`FIG. 3 is a circuit diagram of a third preferred embodi-
`ment according to the present invention. A chip 102 is
`constructed such that the timer circuit 11 of the chip 101
`described with reference to FIG. 2 in the second preferred
`embodiment is replaced with a potential detector circuit 21
`and a monostable multivibrator 22.
`The system for determining the timing of intermittently
`charging and discharging the virtual power supply line
`VDDV and virtual grounding line GNDV during the standby
`period by the timer circuit 11 as in the second preferred
`embodiment is advantageous in simple circuit arrangement.
`However.
`to previously setting the timing by the timer
`circuit 11. consideration must be given to allowance for
`operation of the semiconductor integrated circuit due to
`variations in operating conditions such as voltage and tem-
`perature and variations in chip fabricating conditions.
`More specifically. consideration must be given to the
`lowest level of the decreasing potential of the virtual power
`supply line VDDV and the highest level of the increasing
`potential of the virtual grounding line GND which can hold
`logic stored in the latch. register. and flip—flop of the logic
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`circuits Li. Such consideration must be given for each of all
`logic circuits L. In addition. since the virtual power supply
`line VDDV and v