IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. l, FEBRUARY 1984
`
`5
`
`Special Papers
`A Subnanosecond 2000 Gate Array with
`ECL 1 OOK Compatibility
`
`FUMIHIKO SATO, TORU TAKAHASHI, HIROYUKI MISA WA, AND KODO KIMURA, MEMBER, IEEE
`
`Abstract-This paper describes a subnanosecond gate array with 2000
`g2te complexity using liD advanced bipolllr process. The high performance
`of this process and the optimized circuit design have made it possible to
`achieve a 700-ps delay time for a basic ECL gate under a general usage
`condition of a 3 fan-in, 3 fan-out and 3-mm wiring length, in spite of a low
`power dissipation of 1.9 mW /gate. A 450-MHz typical toggle frequency
`has been obtained by using a series-gated flip-nop. Utilizing the integrated
`computer aided design (CAD) system, a quick and error-free-design can be
`achieved. As a result, 100 percent routability has been attained for auto(cid:173)
`matic placement and wiring in spite of 90 percent cell utilil.ation. Low
`thermal resistance (6°CjW) packages are employed for this LSI chip to
`enable installation in an air cooled system.
`
`I. INTRODUCTION
`
`T HE DEMANDS of higher system speed are increasing
`
`from manufacturers of mainframes, telecommunica(cid:173)
`tions equipment, IC testers, and electric measuring instru(cid:173)
`ments. One very effective improvement for a high-perfor(cid:173)
`mance data processing system is the change to a high-speed
`and a highly complex gate array from standard IC's. The
`media delay caused by the interconnect and package capa(cid:173)
`citance can be reduced by using customized and more
`highly integrated circuits. In order to meet these require(cid:173)
`ments, this high-speed and highly complex gate array has
`been developed. Furthermore, this gate array was designed
`using the following concepts to extend the application of
`high-speed LSI.
`
`A. High-Speed Opermion in Systems
`
`This concept includes high-speed operation of the chip
`itself and reduction of media delay. In order to achieve
`high-speed operation of the chip itself an advanced bipolar
`process [1] and optimized circuit configuration are em(cid:173)
`ployed. Since sufficient drive capability is required for
`media delay reduction, an ECL lOOK output buffer having
`a 50-n terminated resistor is adopted.
`
`B. Necessity of Predictable Performance
`
`In order to achieve an optimum system design, perfor(cid:173)
`mance prediction before production of gate arrays is
`
`Manuscript received May 30. 1983; revised October 10. 1983.
`The authors are with 1\EC Corporation, Kawasaki City, Kanagawa,
`211. Japan.
`
`AUTOMATIC LAYOUT AREA
`
`---------------------
`' : ..-----.
`
`' ' I
`
`I
`L..~--J :
`L ____ ---------- ___ J
`
`INTERNAL VOL TAG£ REGULATOR
`
`Fig. 1. Logic flow.
`
`strongly required by the customer. For this concept, a
`reproducible simple structured process has been developed,
`and a stable circuit configuration has been adopted.
`
`C. Adoption of an Air Cooled Environment
`
`Since the air cooling technique is popular and inexpen(cid:173)
`sive for systems, the operation in an air cooled environ(cid:173)
`ment is considered to be important for wide use in many
`systems. Accordingly, low power internal gates and low
`thermal resistivity packages are used for this gate array.
`
`D. Quick and Error-Free Design of Customized Circuits
`
`The quick and error-free design is an essential concept
`for the custom design of gate arrays. In order to satisfy this
`concept, the integrated CAD system [2] which is based on a
`macro cell design method is utilized.
`
`II. LOGIC FLow
`
`This gate array was designed to be compatible with ECL
`lOOK logic levels which are used in the fastest standard
`logic integrated circuits. ECL lOOK levels are converted to
`internal ECL levels to perform logic through the input
`buffer, and then converted back again to ECL lOOK levels
`through external function blocks and output emitter fol(cid:173)
`lowers to facilitate system compatibility (Fig. 1). A small
`logic swing is used for internal ECL levels in order to
`achieve high-speed operation and a two-level series-gated
`structure. The internal voltage regulators (~s; and ~,)
`drive all the constant current sources of internal and
`
`0018-9200/84/0200-0005$01.00 ©1984 IEEE
`
`0001
`
`AMD EX1026
`U.S. Patent No. 6,239,614
`
`

`

`6
`
`WEE JOURNAL Of SOUD·STATE CIRCUITS, VOL. SC-19, NO.1, FEBRUARY 1984
`
`Base
`
`Emitter
`
`Collector
`
`p- sub
`
`Fig. 2. Cross section of the basic transistor fabricated by an advanced
`bipolar process.
`
`TABLE I
`CHARACTERISTICS Of AN INTERNAL GATE TRANSISTOR
`
`C-B Junction Capacitance Cjc 0.015 pF
`B·E Junction Capacitanc e Cje 0.016 pF
`C-Sub Junction Capacitance Ccs 0.041 pf
`Base Resistance
`Rbb 1080 Ohm
`Collect or Resistance
`Rsc
`79 Ohm
`Cut -Off Frequency
`8 GHz
`fr
`70
`Current Gain
`hfe
`
`external gates respectively to keep the logic swing stable.
`The stable reference voltages for internal gates (VR1) and
`input buffers (Vbb) are also generated by the internal
`voltage regulators.
`The function blocks, or predefined logic elements, con(cid:173)
`taining the intracell connections are used for implementa(cid:173)
`tion of the custom logic. According to the design database
`for custom logic implementation, internal and external
`function blocks are automatically placed in the appropriate
`cell position within the automatic layout area and are
`further interconnected using the CAD system.
`
`hand, the double base transistor is used in the external cells
`which have relatively small load resistors. The emitter sizes
`are 1.5 x 3 p. m2 for internal gate transistors and 1.5 x 5 p.m2
`for internal emitter follower transistors. Table I shows
`characteristics of an internal gate transistor.
`Three layer aluminum metallization is used for signal
`and bias routing and for the power buses. The third layer is
`only used for the power buses to reduce the power line
`resistance. The first layer metallization for signal is 3 J.l.m
`wide with a 5 J.l.ffi pitch and the second layer metallization
`is 4 p.m wide with a 10 p.m pitch.
`
`III. PROCESS
`
`IV. CIRCUITS AND FUNCTION .BLOCKS
`
`An advanced bipolar process using oxide isolation [1]
`has been adopted for this gate array (Fig. 2). In order to
`predict precise gate array performance before production,
`the small distribution of characteristics is considered to be
`important to a gate array process. In contrast with new
`devices for high-speed operation having complex structure
`and a complicated fabrication sequence [3], [4], [5], the
`simple structure is applied to realize reproducible high
`volume production for a high complexity LSI chip. As a
`result, a high predictability in production yields and circuit
`performance has been obtained prior to production.
`Generally, the reduction of parasitic capacitances, the
`decrease of base resistance, and higher cutoff frequency are
`known to be effective methods for increasing speed in ECL
`circuits. In order to reduce the parasitic capacitances of a
`transistor, the oxide isolation and narrow emitter stripe are
`adopted. In an attempt to decrease base resistance, the
`spacing between an emitter electrode and a base electrode
`is reduced to 2 p.m. which is the minimum electrode
`spacing in this process. A shallow junction structure which
`has 0.1 }J.m base width 0.1 }J.m emitter depth have been
`realized using ion implantation and a polysilicon arsenic
`emitter. Consequently, a high cutoff frequency of 8 GHz
`has been obtained. A thin n-type epitaxial layer 1 }J.m thick
`is used for this process.
`ln order to minimize the propagation delay time, the
`tradeoffs bet• 1een the small capacitance of a single base
`transistor an< the smaU base resistance of a double base
`transistor are considered using circuit simulation. As a
`result, the single base transistor proved to be effective for
`the circuits which have relatively large load resistors and
`effective for high packing density. Accordingly, the single
`base transistor is used in the internal cells. On the other
`
`A stable small logic swing ECL circuit has been adopted
`in this gate array to achieve high speed operation. The
`stable logic swings within the logic array are tightly con(cid:173)
`trolled by the active transistor current sources, whose bias
`voltage is fully voltage and temperature compensated by
`internal voltage regulators. Consequently, the internal logic
`swing has been reduced to 560 m V.
`In an attempt to achieve high-speed operation, current
`levels for internal transistors have been optimized through
`circuit simulation and trial production. The effect of cutoff
`frequency falloff at high currents [6] and the current divi(cid:173)
`sion between gate and emitter followers are considered in
`the circuit simulation using a Gumrnel- Poon model [7]. As
`a result, a current of 0.4 rnA has been selected for internal
`gates and emitter followers.
`In order to increase the function capabilities and reduce
`the gate equivalent delay, series gating, collector dotting,
`and emitter dotting can effectively be used for function
`implementation. Fig. 3 shows a basic internal circuit of the
`OR-AND block using the diode-clamped collector dot. Th.is
`block uses only one internal cell out of 832 internal cells in
`this gate array. The internal cell bas 8 transistors for the
`gates, 4 transistors for the emitter followers, 12 resistors for
`the gates, and 8 resistors for the emitter followers. For
`internal function block outputs, emitter followers having a
`low output impedance are used to minimize the delay
`variation due to an unpredictable wiring length. Unused
`emitter followers in the multioutput blocks are not con(cid:173)
`nected by the integrated CAD system so that unnecessary
`power dissipation may be avoided. Emitter dotting be(cid:173)
`tween blocks can be enhanced by widening the intercon(cid:173)
`nection between emitter followers to minimize the logic
`level drops of the emitter dotting. As a result, a maximum
`
`0002
`
`

`

`SATO eta{.: 2000 GATE ARRAY WITH llCL100K COMPATIBILITY
`
`7
`
`T
`Vj •560mV
`1
`
`· OUTPUT
`
`OUTPUT
`
`(a)
`
`IN~UT
`
`...J_ _ _J_ _ _ __J._-.n:
`(b)
`
`(c)
`Fig. 3. (a) Schematic diagram of a basic internal circuit of the OR-AND
`block. (b) Schem~tic diagram of an input buffer. (c) Schematic diagram
`of an output buffer.
`
`of 4 multiinput emitter dots between blocks is allowable
`for this gate array.
`The 60 types of internal function bldcks ranging from
`one simple gate to complicated circuits ate available for the
`custom logic implementation. Only a simple gate is applied
`for external function blocks to minimize the external cell
`area which is occupied by large external transistors.
`A 50 kQ pull-down resistor is provided for the input
`buffer to keep a logic "low" state for the open input
`terminals as shown in Fig. 3(b). Furthermore, the input
`buffers contain circuitry to protect the inputs against
`damage due to high static voltages or electric fieids.
`Fig. 3(c) shows the output buffer which has lOOK ECL
`interface. lOOK ECL logic lias temperature and voltage
`compensated high ( -955 mV) and low ( -170§ mV) volt(cid:173)
`age levels.
`
`v. DEVICE LAYOUT
`The microphotograph of the gate array chip is sh~wn iri
`Fig. 4. The 832 (26 X 32) internal cells are placed within the
`internal logic circuit area. The 48 (24 x 2) external cells are
`placed on the left and right sides. Therefore the output
`signals appear on the left and right side bonding pads.
`Since the 108 input buffers are provided on all four sides,
`
`Fig. 4. Microphotograph or the gate array chip.
`
`the left and right side pads cari also be used as input
`terminals. The power supply terminals are located on all
`four sides of the chip to reduce the voltage drops in power
`busses caused by the m;udmum power supply current of 2
`A. As a result, the voltage drops in power busses are
`limited to 60 rnY. Power supply terminals are provided
`separately for internal and external logic cells (Vee) and
`for the output emitter followers CVccA) in order to rriini(cid:173)
`mize coupling of the output emitter follower switching
`noise back into the internal arid external logic. The chip
`size is 7.5 mm by 7.2 mm. The bonding pad with 174 J.IID
`pitches are used to increase the signal and power terminals.
`
`VI. PERFORMANCE
`
`In order to achieve high-speed operation and low power
`dissipation, tlie circuit and process parameters have been
`optimized through circuit simulation and trial production.
`The general usage condition of 3 fan-in, 3 fan-out having a
`3-mm wiring length is used for optimization for high-speed
`operation in custom circuits. As a result, the internal gate
`delay of 700 ps (FI - FO - 3 wiring length - 3 mm) and
`400 ps (FI = FO = 1) have been achieved in spite Of a low
`power dlssipation of 1.9 mW. The fan-out delay coefficient
`of the internal gate is 0.022 ns/fan-out (Fig. 5) and the
`interconnect delay coefficient in the internal cells is 0.06
`ns/mm (Fig. 6). A typical toggle frequency for flip-flop
`blocks using series gating is 450 MHz with 7.3-mW power
`dissipation. The ECL lOOK interface provides voltage and
`temperature compensated output logic levels having less
`than a 0.2 mY ;oc temperature variation and 20 mY jV
`source voltage variation. The output emitter followers can
`be connected to - 2 v with so-n loads to obtain large drive
`capability.
`The features of this gate array are shown in Table iL
`
`VII. P ACKAGE
`
`In order to maintain high-speed operation of the gate
`array chips, small capacitance and inductance signal termi(cid:173)
`nals are necessary for the package. Good heat transfer
`
`0003
`
`

`

`8
`
`IEEE JOURNAL Of SOLID-STATE CIRCUITS, VOL. sc-19, NO. 1, FEBRUAJI.Y 1984
`
`0o
`
`'
`
`l
`
`3
`
`4
`
`'
`
`6
`
`7
`
`8
`
`Fig. 5. Propagation delay time of an internal gate versus number of
`fan-out
`
`Fig. 7. 72 and 132 pin pin-grid array package.
`
`0o 1 2
`J 4 5 6 7 8
`tirnl>
`Wirlnv t..ngth
`Fig. 6. Propagation delay time of an internal gate vmus wiring lcnglh.
`
`TABLE II
`MAIN FEATURES
`
`lnt ... I~Ce LPI!el
`Equivalent Gates
`
`lOOK
`
`ECL
`2000
`
`Propagalion Delay Time
`
`0.7ns/1.9mW
`Internal Gate
`(F I:F0 :3 Wiring Lt'ngth:3mml
`Input BuHer
`0.6nsll9mW
`
`Output Buffer
`
`1.0ns/22.5rriN
`
`Power Dissipation
`Sourct' Voltage
`Signal Pins
`
`Number of Cells
`lntt'rnal
`
`E•tern~l
`
`Padcagt'S
`
`6.0W (Typ.)
`-4.5V
`
`108 (Max.)
`
`832
`48
`
`72 Of t32 pin pin9'id array
`68 pin l@ad1g-s chlp carrier
`
`properties and small size are also required for a high
`packing density implementation. In order to meet these
`requirements, the ceramic pin-grid array package and 68
`pin JEDEC leadless crup carrier have been utilized for this
`gate array. The 72 pin and 132 pin pin-grid array packages
`(Fig. 7) have a low thermal resistance of 6°C/W with 4
`mjs air flow. Good heat transfer is assued since the LSJ
`chip is mounted on the lid of the package attached to the
`heat sink.
`Due to the low thermal resistance package, this gate
`array can be used in an air cooled system. Furthermore,
`the height of the package (from the bottom of the package
`substrate to the top of the heat sink) was designed to be
`less than 11 mm. Accordingly, a high packing density of 17
`mm pitch between printed circuit boards can be employed.
`
`Fig. 8. CAD system configuration.
`
`VIII. CAD SUPPORt
`
`For quick and error-free design of custom circuit imple(cid:173)
`mentation, the integrated CAD system [2] is utilized. The
`CAD system provides design utilities for all logical and
`physical design stages (Fig. 8).
`This system is based on the design database containing
`function block connection data, functional test patterns,
`and pin assignments. In the first design step, the custom
`\;in.;uits an~ checked by the logic design rule checker to
`determine if the circuits satisfy the design rules such as
`number of fan-in and fan-out, and power dissipation. In
`addition, the function of the circuits are verified by the
`logic simulator.
`An estimation of the propagation delay time is im(cid:173)
`portant for the performance verification of a high-speed
`gate array. In order to assure the customer requirements,
`the delay simulation assuming typical interconnection
`length can be performed before layout. After the automatic
`placement and wiring, precise delay simulation can be
`accomplished using the actual interconnection length. Using
`two level interconnection, 100 percent mutability has been
`attained for automatic placement and wiring in spite of 90
`percent cell utilization.
`In the final steps, a pattern generation tape for a mask
`maker is created by an artwork file converter, and a test
`program generator creates the test program for an IC
`tester.
`
`0004
`
`

`

`SATO eta/.: 2000 GATE ARRAY WITH ECL lOOK COMPATIBILITY
`
`9
`
`LOOP"d Bus
`lntt~rtac~
`
`REFERENCES
`
`[1] H. Yamamoto eta!., "High speed performance of a basic ECL gate
`witb 1.25 micron design rule," in Dig. Tech . Papers 1981 Symp.
`VLSI Tee/mol., pp. 38-~9, 1981.
`[2] H. Yoshizawa ef a/., "A CAD system for gate array automated
`desig'!," in Pr0c.· CICC 82 , pp. 260- 262, 1982.
`(3] T. Sakai et al., " A 3-ns l·kbit RAM using super self-aligned process
`technology," IEEE J. Solid-State Circuits, vol. SC-~6, no. 5, pp.
`424- 428, Oct. 1981.
`[4] H. Nakashiba et al., "An advanced PSA technology for high-speed
`bipolar LSI," IEEE Trans. Electron Devices, vol. ED-27, n9. 8. pp.
`l390- P94, Aug. 1980.
`[5) A. Anzai et a/., "The high speed bipolar LSI technology," in Proc.
`High Speed Digital Technologies Con{., vol. II-2, Jan. 1981.
`(6] R. 1. Whitter et a/., "Current gain and cutoff (requeocy fall-off at
`high currents," IEEE Trans. Electron Devices, vol. ED-16, no. l ,'Jan.
`1969.
`[7] H. K. Gummel and H. C. P.oon, "An integral charge control mode of
`bipolar transistors," Bell Sysr. T~c/1. 1., vpl. 49, pp. 827-852,
`MayjJunc 1970.
`.
`
`FumihikQ Sato was born in Tokyo, Japan, on
`October 13, 1952. He received t!Je B.S. degree in
`electrical engineering from Keio University,
`Tokyo, Japan~ in 1975.
`He joined NEC Corporation, Tokyo, Japan, in
`1975. In 1976 he transferred to NEC-Toshiba
`Information Systems Inc., Tokyo, Japan. where
`he was engaged in the research of high-speed
`bipolar VLSI. He is currently involved in the
`development and circuit design of high-speed
`ECL gate arrays with the 1st LSI Division, NEC
`Corporation, Tokyo, Japan.
`
`Toru Takahashi was born in Tokyo, Japan, on
`May 6, 1947. He received the B.S. degree in
`electronic engineering £rom Tokyo Denki U ni·
`versity, Tokyo, Japan, in 1971.
`lie has been engaged in the design and devel·
`9pmcnt of high-speed bipolar LSI's since he
`joined NEC Corporation. Tokyo, Japan, in 1971.
`He is currently a Supervisor of the 1st LSI Divi(cid:173)
`siop, and is responsible for the development of
`high-speed ECL gate arrays.
`Mr. Takahashi won the 1978 ISSCC Best Paper
`Award.
`
`Hiroyuki Misawa was born in Tokyo, Japan, on
`January 1, 1952. He received the B.S. degree in
`electrical engineering from Gumma University,
`Gumma, Japan, in 1974.
`He joined NEC Corporation, Tokyo, Japan, in
`1974 where he has been engaged in the research
`and development of high-speea bipolar logic 1,-SI's
`in the 1st LSI Divisi9n.
`
`KOdo Kimura (M'79) received the B.S. degree in
`communication engineering from Tohoku Uni·
`versity, Send~, Japan, in 1965.
`He joined NEC Corporation Tokyo, Japan, in
`196S where he has been engaged in research and
`development of bip(>lar IC's for elcctrqryic
`switching system. Since 1970, he bas been en(cid:173)
`gaged in the devdop!Dcnt of high-spec<! bipolar
`logic LSI's for digital equipment. [n 1978, be
`became a cooperative mewb<:r of N'EC·Tu>Liba
`.Information Systems Inc., Tokyo, Japan, for the
`research of VLSI. He is currently Engineering Manager of the 1st LSI
`Division, NEC Corporation,· and is responsible for the development of
`digital logic LSI's.
`
`Proc~sor
`lnt~rtacf'
`Fig. 9. Blcx:k diagram of loop bus controller (LBC).
`
`IX. APPLICATION
`
`Fig. 9 shows a block diagram of the loop bus controller
`(LBC) using this gate array. Packet data are sent to looped
`buslines through the loop bus interface under the control
`of LBC. LBC also has the processor interface and the
`receiver circuit interface. This LSI has 2039 equivalent
`gates in spite of 85 percent cell utilization. Due to the high
`performance of this gate array, an 100-MHz operation has
`been achieved. In this circuitry, a 4-bit universal counter is
`implemented using 26 cells, whjch has 140-mW power
`dissipation and 1.0-ns propagation delay time from clock
`to output. In contrast with standard MSI counter chip
`which has 624-mW and 3.3-ns propagation delay time, a
`high-performance counter bas been realized in this gate
`array.
`This LSI bas 5.3-W power dissipation and uses 132 pin
`pin-grid array package.
`
`X. CONCLUSION
`
`A subnanosecond gate array with ECL lOOK compatibil(cid:173)
`ity has been developed. This gate array has a 700-ps
`propagatjon delay time (FI "" FO = 3, wiring length = 3
`rom), 2000 equivalent gate complexity, and a 132 pin low
`thermal resistance package. These features have been real(cid:173)
`ized by usipg an advanced bipolar process, an optimized
`circuit design, and il good heat transfer package. In addi·
`tion, a quick and error-free design of customized circuits is
`realized by the integrated CAD system: This type of ga,te
`array will contribute greatly to a high-speed data process(cid:173)
`ing system.
`
`ACKNQWLEDGMENT
`
`The authors would like to thank T. Goto, H. Sasaki, S.
`Y?~wata, H. Yamamoto, T. Nakamura for their helpful
`suggestions and encOuragements, and K. Tanaka of NEC
`IC Microcomputer System Co., Ltd., for his technical
`a~>sistance.
`
`0005
`
`