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`CMOSl4 N'MOS CMOS14 PMOS
`
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`
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`
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`—_______.I___.__..._....
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`
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`0004
`
`
`
`CMOS
`
`Circuit Design, Layout, and Simulation
`
`R. Jacob Baker, Harry W. Li and David E. Boyce
`Depanmenr of Electrical Engineering
`Microelectronics Research Center
`
`The University ofIdaho
`
`IEEE Press Series on Micrdelecu'onic Systems
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`Printed in the United States of America
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`IEEE Order Number: PC5689
`
`Library of Congress Calaluélng-ill-Pubiicafian Data
`
`Baker. R. Jacob (dale)
`CMOS circuit design. layout. and simulation 1 R. Jacob Baker.
`Harry W. Li. and David E. Boyce.
`p.
`cm. «- (IEEE Press series on nficroelecu‘onie systems]
`Includes bibliographical references and index.
`ISBN [ll—780334164?
`l. Metal oxide semiconductors. ComplementaryaDesign and
`construction.
`2. Integrated cficuitstesign and construction.
`3. Metal oxide semiconduclm fieldreffect transistors.
`1. Li.
`
`II. Bnyce, David E.
`Harry W.
`TK?87L99.M44335
`I997
`621.3815--DC2I
`
`[11. Title.
`
`IV, Series
`
`97—21905
`CE’
`
`
`
`0006
`
`
`
`To
`
`Julie and Melanie
`
`0007
`
`
`
`0008
`
`
`
`Cc‘mtents
`
`Preface
`
`Part I CMOS Fundamentals
`
`Chapter 1
`
`Introduction
`
`xix
`
`1
`
`3
`
`1.1 The CMOS IC Design Protesi ...................................... 3
`1.1.1 Fabrication
`3
`
`1.2 Using the LASI Program ...... ... . .. ............................... 5
`1.2.] Cells in LASI
`7
`
`1.2.2 Navigating LASI
`
`1.2.3 Adding Objects
`1.2.4 Editing Objects
`
`1.2.5 Placing Cells
`1.2.6 Common Problems
`
`10
`
`10
`11
`
`12
`14
`
`1.3 MOSIS ............................................................. 15
`
`23
`Chapter 2 The Well
`2.] The Substrate ................................ . ................... .. 23
`
`2.1.1 Patterning
`
`2.1.2 Patterning the N-wel-l
`
`24
`
`27
`
`2.2 Laying out theN—wel] .............................................. 27
`
`0009
`
`
`
`viii
`
`2.2.1 Design Rules for the N-well
`
`Contents
`
`28
`
`30
`2.2.2 Using the LASIDRC program
`2.3 Resistance Calculation ........... . ........ . ........................ 30
`2.3.] The N«well Resistor
`32
`
`2.4 The N—well/Substrate Diode. ..................... . ......... . ........ 32
`
`2.4.] Depletion Layer Capacitance
`
`2.4.2 Storage Capacitance
`
`2.4.3 SPICE Modeling
`
`33
`
`35
`
`37
`
`2.5 The RC Delay Through an N-wel]
`
`.......... . ............. r .........38
`
`45
`Chapter 3 The Metal Layers
`3.| The Bonding Pad .... ........................., ..................... 45
`
`3.1.] Laying our the Pad
`
`3. [.2 Design Rules for Pads
`
`45
`
`48
`
`3.2 Design and Layout Using the Metal Layers ......................... 50
`
`3.2.] Design Rules for-the Metal Layer's
`
`3.2.2 Parasitics Associated with the Metal Layers
`
`3.2.3 Current Carrying Limitations
`3.2.4. ParasitiCs Associated with the Via
`
`50
`
`50
`
`54
`55
`
`3.3‘ Crosstalk and Ground Bounce ....................... . ............. 56
`3.3.1 Ground Bounce
`57'
`
`3.4 Layout Using Cell Hierarchy ........................................ 59
`
`Chapter 4 The Active and Poly Layers
`
`65
`
`4.] Design Rules ................. . ........ . ............................ 66
`
`4. I .] Design Rules for the n+fp+Active Layers
`
`4.|.2 Design Rules for Poly]
`
`66
`
`69
`
`4.2- Layout of a Standard Cell Frame ..................... . ............. .7]
`
`4.3 Patterning the Active Layers .....- ......... . ......................... 7]
`
`4.4 LayOut of the MOSFET .. .......................................... 77
`
`4.4.] Parasitics Associated with the Active Layers
`
`Chapter 5 The MOSFET
`
`77
`
`83
`
`5.1 The MOSFET Capacitances
`5.1.] Case 1:.Accun1ulation
`
`.t ........................ . ............ 84
`84
`
`5.1.2 Case II: Depletion
`
`85
`
`0010
`
`
`
`Contents
`
`5.1.3 Case 111: Strong Inversion
`
`5.1.4 Summary
`
`ix
`
`36
`
`87
`
`5.2 The Threshold Voltage .............................- ............... 8B
`5.3 IV Characteristics of MOSFETE ............. ... .. .. ................ 93
`
`5.3.1 MOSFET Operation in the Triode Region
`
`5.3.2 The Saturation Region
`
`94
`
`96
`
`5.4 SPICE Modeling of the MOSFET .................................. 98
`
`5.4.1 Level 1 Model Parameters Related to 11m,
`5.4.2 Level 1 Model Parameters-Related to Transconductance
`
`5.4.3 SPICE Modeling of the Source and Drain Implants
`
`5.4.4 Layout of the MOSFET
`
`Chapter 6 The BSIM SPICE Model
`6.1 BSIMI Model Parameters
`...............................
`
`98
`99
`
`100
`
`102
`
`107
`109
`
`6.2 BSIMl DC Equations . ........... . ...............................
`
`111
`
`6.2.1 The Threshold Voltage
`6.2.2 The Drain Current
`
`6.2.3 The Subthreshold Content
`
`6.3 Short Channel MOSFETS ........................................
`
`6.3.1 MOSFET Sealing
`6.3.2 Short Channel Effects
`
`1 1 1
`1 13
`
`116
`
`I 19
`
`120
`122
`
`6.4. The BSIM3 SPICE Model
`
`........ . ..............................
`
`[24
`
`6.5 Convergence ... . ............ . .
`
`. .. ............................... 127
`
`Chapter 7 0111105 Passive Elements
`
`131
`
`7.1 The Second Poly Layer (poly2) .
`
`-. ................................. 13]
`
`7.1.1 Design Rules for CapacitOr Formation
`
`7.1.2 Parasitics of the Poly. Cap
`
`7.1.3 Other Types of Capacitors
`
`131
`
`132
`
`134
`
`7.2 Temperature and Voltage Dependence of Capacitors and
`Resistors
`....... . ......................
`7.2.1 Resistors
`
`. .. . 134
`
`134
`
`7.2.2 Capacitors
`"1.3 Noisein Resistors
`
`140
`,.......... .................. ,. ......... _. ....... 141
`
`Chapter 8 Design Verification with LASICKT
`8.1 Fundamentals of LASICKT ................... . . . . .............. ..
`
`149
`1'51]
`
`001 1
`
`
`
`x
`
`8.1.1 The Inverter
`
`8.1.2 Running LASICKT
`
`8.1 .3 Highersrariking Cells; The OR Gate
`
`Contents
`
`15]
`
`157
`
`160
`
`165
`Chapter 9 Analog MOSFET Models
`9.1 Low-Frequency MOSFET Mode]
`................................ 165
`
`9.1.1 Small—Signal Model of the MOSFET in Saturation
`
`166
`
`9.2 High-Frequency MOSFET Model
`
`., ....................... . ...... 171
`
`9.2.1 Variation of Transconductance with Frequency
`
`173
`
`9.3 Temperature Effects in MOSFETS ................ . .............. 175
`94 Noise in MOSFETs ....................................... _. ...... 178
`
`185
`Chapter 10 The Digital Model
`10.1 The Digital MOSF'ET Model
`.................................... 185
`
`10.1.1 Capacitive Effects
`
`10.1.2 Process Characteristic Time Constant
`
`187
`
`138
`
`189
`It} 1. 3 Delay- and Transition-Times
`10 2' Series Connection of MOSFETS ............................... 192
`
`10.2.1 DC Behavior of SeriesConnected MOSFETS
`
`10.2.2 Delay Through Series—Connected MOSFETS
`
`192
`
`194
`
`Possible Student Projects .........
`
`.................................. 196
`
`Part II CMOS Digital Circuits
`
`199
`
`201
`Chapter 11 The Inverter
`1 1.1 DC Characteristics ............................................. 202
`
`11.1.1 Noise Margins
`
`1 1.1.2 Inverter Switching Point
`
`203‘
`
`204
`
`l 1.2 Switching Characteristics . ........... , ....... . .................. 205
`
`11.2.1 The Ring Oscillator
`
`1 1.2.2 Dynamic Power Dissipation
`
`209
`
`210
`
`11.3 Layoutofthe Inverter .-. .................... 212
`
`11.3.1 Latch—up
`
`212
`
`1 1.4 Sizing for Large Capacitive Loads ........ . ...... . .......... I... 216
`11.4.1 Distributed Drivers
`221
`
`0012
`
`
`
`Contents
`
`11.4.2 Driving Long Lines
`
`11
`
`223
`
`1 1 .5 Other Inverter Configurations
`
`........... . . . . .
`
`.
`
`. . .
`
`.
`
`. . . . ._ ........ 224
`
`11.5.1 NvChanrtel Only Output Drivers
`
`11.5.2 Inverters with Tri-State Outputs
`
`11.5.3 The Bootstrapped NMOS inverter
`
`224
`
`226
`
`.226
`
`231
`Chapter '12 Static Logic Gates
`12-1 DC Characteristics of the HAND and NOR Gates .. ............. 231
`
`12.1.1 DC Characteristics of the NAND Gate
`12.1.2 DC Characteristics of the NOR Gate
`
`23']
`234
`
`12.2 Layout of the NOR and NAND Gates ..
`
`......................... 235
`
`12.3 Switching Characteristics
`12.3.1 NAND Gate
`
`.......... , ........ .
`
`. ........ . ........ 236
`238
`
`12.3.2 Number of Inputs
`
`242.
`
`12.4 Complex CMDS Logic Gates ................................... '243
`
`12.4.1 CasCode Voltage Switch Logic
`
`12.4.2 Differential Split—Level Logic
`
`12.4.3 Tri-State Outputs
`
`247
`
`247
`
`2-52
`
`255
`Chapter 13 The TG and Flip-Flops
`13.1 The PassTransiStor
`....... . .......................... , ..... . . .. 255
`
`13.2 The CMOS TG ................................................. 257
`
`13.2.1 Layout of the CMOS 116
`
`13.2.2 Series Cortnectipn of Transmission Gates
`
`258
`
`260
`
`. .. ...... 260
`.
`.
`. . . .. . .. .
`.
`.
`13.3 Applications of the Transmission Gate. ... .
`13.4 The Flip-Flop ................................................... 265
`
`13.4.1 Clocked FlipaFIOps
`
`266
`
`275
`Chapter 14 Dynamic Logic Gates
`14.1 Fundamentals of Dynamic Logic ...................... . . . -.. . . , . 275
`
`14.1.1 Charge Leakage
`
`.14.] .2 Simulating Dynamic Circuits
`
`14.1.3 Nonoverlapping Ciock Generation
`
`14.1.4 CMOS T0“ in Dynamic Circuits
`
`276
`
`277
`
`279
`
`281
`
`14.2 Clocked CMOS Logic ........ . ....... . .......................... . 231
`
`0013
`
`
`
`xii
`
`Chapter 15 VLSI Layout
`
`Contents
`
`289
`
`15.1 Chip Layout .................................................... 290
`
`15.2 Layout Steps
`
`..... .............................................. 301
`
`Chapter 16 BiCMOS Logic Gates
`
`313
`
`16.1 Layom of meJunetinn-[sola'ted BJT
`
`. . ,. ..
`
`. ..
`
`..... 314
`
`................ 316
`16.2 Modeling'the NPN . ....................... .
`16.3 The BiCMOS Inverter .......................................... 320
`
`16.4' Other BiCMOS' Logic Gates .................................... 323
`
`16.5 CMOS and ECL Conversions Using BiCMOS .. .. ............ .. 326
`
`331
`Chapter 17 Memory Circuits
`17.1 RAM Memory Cells ............................................. 332
`17.1.1 The DRAM Cell
`333
`
`17.1.2 The SRAM cell
`
`337
`
`........................................... 338
`17.2 The Sense Amplifier
`17.3 Row/CelurnnDecoders
`........ . ......... 341
`
`17.4 Timing Requirements for DRAMS ........ ....................... 343
`17.5 Modem DRAM Circuits ......................................... 345
`
`17.5.1 DRAM Memery Cell Layout
`17.5.2 FoldedfOpen Architectures
`
`345
`347
`
`17.6 Other Memory Cells ............................................. 350
`
`355
`Chapter 18 Special-Purpose Digital Circuits
`18.1 The ‘Schmitt Trigger ............................................ 355
`
`18.1.1 Design of the Schmitt Trigger
`
`18.1.2 Switching Characteristics
`
`18.1.3 Applications at” the Schmjtt Trigger
`
`356
`
`359.
`
`359
`
`361
`18.1.4 High—Speed Schmitt Trigger
`18.2 Multivihratnr Circuits
`.... ...................................... 362
`
`18.2.1 The Mnnnstable Multivibrator
`18.2.2 The Astable Multi‘vibrator
`
`362
`363
`
`18.3 Voltage Generators ............... . ........................ ...... 364
`
`18.3.1 Improving the Efficiency
`
`18.3.2 Generating Higher Voltages
`
`13.3.3 Example
`
`366
`
`367
`
`368
`
`0014
`
`
`
`Contents
`
`xiii
`
`373
`chapter 19 Digital Phase-Locked Loops
`19.1 The PhaseDeleclor ............ , ..... . .......................... 375
`19.1.1 The XOR Phase Detector
`375
`
`19.1.2. Phase Frequency Detector
`
`379
`
`19.2 The Voltage-Controlled Oscillator .............................. 333-
`19.2.1 The Current»Starved VCO
`384
`
`19.2.2 Source Coupled VCOS
`
`387
`
`19.3 The Loop Filter
`19.3.1 XOR DPLL
`
`......... . ...... , ..................... . ........ 39]
`391
`
`[9.3.2 PFD DPLL
`
`398
`
`19.4 System Considerations
`
`.................. . .............. . .. ..-... 403-
`
`19.4.1 Clock Recovery from NR2 Data
`
`407
`
`19.5 Delay-Locked Loops .. .. .
`
`.
`
`. . . ..
`
`................ ............... 417
`
`Part III CMOS Analog Circuits
`
`425-
`
`427
`Chapter 20 Current Sources and Sinks
`20.1 The Current Mirror ............................................. 427'
`
`20.1.1 The Cascode Connection
`
`20.1.2 Sensitivity Analysis.
`
`20.].3 Temperature Analysis
`
`20.l.4 Transient Response
`
`20.1.5 Layout of the Simple Current Mirror
`
`433
`
`438
`
`439
`
`442
`
`444
`
`446
`20.1.6 Matching in MDSFET MirrOrs
`20.2 Other Current SourcesISinks
`............. . ...................... 450
`
`463
`Chapter '21 References
`21.1 Voltage Dividers ................................. . ............. 463
`21.1.1 The ResistoerOSI-TET Divider
`464
`
`21.1.2 The MOSFET-Only Voltage Divider
`
`21.2 Current'Source Self—Biasing ................ ,.
`
`.
`
`. .. . .......
`
`21.2.1 Threshold Voltage Referenced Self—Biasing
`
`21.2.2 Diode Referenced Self~Biasing
`
`21.2.3 Thermal VoltageRefereneed Self—Biasing
`
`465
`
`469
`
`469
`
`470
`
`474
`
`0015
`
`
`
`xi v
`
`Content-s
`
`21.3 Bandgap Voltage References
`
`.._ ................................. 477
`
`21.3.1 Ban‘dgap Referenced Biasing
`
`478
`
`21.4 Beta Multiplier Referenced SeItZBiasing ........................ 480
`
`21.4.1 A Voltage Reference
`
`21.4.2 Operation in the Subthreshold Region
`
`481
`
`433
`
`Chapter 22 Amplifiers
`22.1 Gate-Drain Connected Loads .
`
`489
`-. ................................. 489
`
`22.1.1 Common Source Amplifiers
`
`22.1.2 The Source Follower
`
`4.89
`
`493
`
`500
`22.1.3‘ Common Gate Amplifiers
`222 Current Source Loads
`.......................................... 500
`
`22.2.1 The Cascade Connection
`
`22.2.2 The Push—Pull Amplifier
`
`506
`
`510
`
`22.3 Noise and Distortion in Amplifiers
`
`............................. 512
`
`22.3.1 Modeling Amplifier Noise
`
`515
`
`22.4% A Class AB Amplifier ......... . ................................. 517
`
`Chapter 23 Feedback Amplifiers
`
`525
`
`23.1 The Feedback Equation ................................ . ....... 526
`
`23.2 Properties of Negative Feedback on Amplifier Design ........... 52?
`
`23 .2.1 Gain Desensitivity
`23.2.2 Bandwidth Extension
`
`23.2.3 Reduction in Nonlinear Distortion
`
`23.2.4 Input and Output Impedance Control
`
`527
`523
`
`529
`
`530
`
`23.3 Recognizing Feedback Topologies .............................. 532
`
`23.3.1 Input Mixing
`
`23.3.2 Output Sampling
`23.3.3 The Feedback Network
`
`23 3.4 Calculating Open~Loop Parameters
`
`23.3.5 Calculating Closed—Loop Parameters
`
`533
`
`533
`534
`
`537
`
`539
`
`23.4 The Voltage Amp (Series~3hunt Feedback)
`
`... .. . . ........ , . ..... 540
`
`23.5 The Transimpedance Amp (Shunt~Shunt Feedback) ...... _. ...... 547
`
`23.5.1 Simple Feedback Using a Gate-Drain Resistor
`
`555
`
`23.6 The Transcenduemnce Amp (Series—Series Feedback) . . . . ....... 558
`
`23.7 The Current Amplifier (Shunt~Seties Feedback)
`
`...- .
`
`. . .. . .. . . 562
`
`0016
`
`
`
`Contents
`
`xv
`
`23.8 Stability.. ........... 564
`
`23.3.1 The Return Ratio
`
`568
`
`519
`Chapter 24 Differential Amplifiers
`24.1 The Source Coupled Pair ..................................... .. . 579
`
`24.1.1 Current Source Lead
`
`24.1.2 Common-Mode Rejection Ratio
`24.1.3 Noise.
`
`24.1.4 Matching Considerations
`
`582
`
`591
`592
`
`594
`
`24.2 The Source Cross-Coupled Pair ................................. 596
`24.2.1 Current Source Load
`599
`
`24.3 Cascade-Loads
`
`......... . .................. . ....... . ...... . ..... 602
`
`24.4 Wide-Swing Differential Amplifiers ............................ 605
`
`24.4.1 Current Differential Amplifier
`
`24.4.2 Constant T‘ransconductance Diff—Amp
`
`Chapter '25 Operational Amplifiers
`
`60?
`
`60—8
`
`617
`
`25.] Basic CMOS Opt—Amp Design .................................... 6‘1 8
`
`25.1.1 Characterizing the Op-Amp
`
`25.1.2 Compensating the Op-Amp Without Buffer
`
`25.1.3 The Cascade Input Op-Amp
`
`630
`
`634
`
`636
`
`25.2 Operational Transconductance Amplifiers ...................... 637
`25.2.1 Wide-Swing UTA
`642
`25.2.2 The Folded~Cascode OTA
`654
`
`25.3 The Differential Output Op-Arnp ...... , ........................ 664
`25.3.1 Fully Differential Folded—Caseode OTA
`666
`25.3.2 Gain Enhancement
`674»
`
`Part IV Mixed-Sig nal Circuits
`
`683
`
`685
`Chapter 26 Nonlinear Analog Circuits
`26.] Basic CMOS Comparator Design ............................... 685
`
`26.1.1 Characterizing the Comparator
`
`26.2 AdaptiveBiasing
`
`691
`
`............ 699
`
`26.3 Aoa'logMuitipliers .. ............ . ....... .. 704
`
`0017
`
`
`
`xvi
`
`263.1 The Multiplying Quad
`
`26.3.2 Level _Shifting-
`26.3 .3 Multiplier Design Using Squaring Circuits
`
`Chapter 27 Dynamic Analog Circuits
`27.1 The MOSFET Switch ................... . ..................
`
`Contents
`
`705
`
`710
`715
`
`.719
`719
`
`27.2 Switched-Capacitor Circuits ................................... .. 728
`
`731
`27.2.1 Switched-Capacitor Integrator
`27.3 Circuits ........................................................ 745
`
`755
`Chapter ‘98 Data Converter Fundamentals
`28.1 Analog. Versus Diserete Time Signals ........................... 755
`
`28.2 Converting Analog Signals to Digital Signals ... . .. . .. .......... 756
`
`28.3 Sample-and-Hold (SIH) Characteristics ......................... 759
`
`28.4 Digital-[o‘Analog Convener (DAG) Specifications. .............. 762
`
`28.5 Analogto-Digital Converter (ADC) Specifications ...... ........ 772
`
`28.6 Mixed-Signal Layout Issues
`
`.............. . ...............
`
`.
`
`. .. 783
`
`791
`Chapter 29 Data Convener Architectures
`29.] DAC Architectures .......................................... .. .. 79]
`
`29.1.1 Digital Input Code
`
`29.1.2 Resistor String
`29. I .3 R~2R Ladder Networks
`
`29.1.4 Current Steering
`
`29. l .5 Charge Scaling DACs
`
`29.1.6 Cyclic DAC
`
`791
`
`792
`797
`
`800
`
`805
`
`810
`
`811
`29.1.7 Pipeline DAC
`29.2 ADC Architectufes ................. . ........ . . ........ . ....... . 813-
`29:.2.[ Flash
`813
`
`29.2.2 The Tw0=Step Flash ADC
`
`29.2.3 The Pipeline ADC
`
`29.2.4 integrating ADCS
`29.2.5 The SuccessiveApproximation ADC
`
`29.2.6 The Oversampling ADC
`
`818
`
`823
`
`827
`832
`
`837
`
`855
`Appendix A Orbit's CN20 Process
`AA Process Specifications ........................................... 857
`
`0018
`
`
`
`Contcnts
`
`A.1.l Electrical Specifications
`
`A.] .2 N-Channc] SPICE Models
`A. 1.3 P—Chanuel SPICE Models
`
`xvii
`
`857
`
`359
`361
`
`A. 2 Hand Calculations
`
`.............................................. 862
`
`A. 2 l The N-channel MOSFET Equations
`
`A. 2. 2 Th; P—channei MOSFET Equations
`
`862
`
`365
`
`A. 3 Design Rules .................................................... 867
`
`Appendix B MOSIS Scalabie Design Rules
`
`Appendix C HP's CMOS14TB
`Index
`
`About the Authors
`
`LAS‘I Software
`
`873
`
`885
`893
`
`903
`
`904'
`
`0019
`
`
`
`0020
`
`
`
`Preface
`
`Over the last ten years the electronics industry has exploded. A recent report by the
`Semiconductor Industry Association (51A) [1] proclaimed that in 1995 alone, world
`chip revenues increased by 41.7 percent and for the past five years the growth had been
`exponéntial. By the year 1999, the report estimates that world chip sales will Surpass
`$234.5 billion, up from $154' billion in 1996. The largest portion of total worldwide
`sales is dominated by the MOS market. Composed primarily of memory, micro and
`logic sales, the total combined MOS revenue contributed approximately 75 percent of
`total world-wide sales {$114.2 billion), illustrating the strength of CMOS technology-
`The percentage of 'MOS sales relative to all chip revenues is expected to remain
`constant through 1999. when MOS sales will total $178 billion.
`
`CMOS technology continues to mature, with minimum feature sizes now
`approaching 0.1 urn. Texas Instruments recently announced a (1-18 tun process. [2] in
`which the equivalent of 20 high-performance microprocessors could exist on the same
`substrate..with a transistor density of 125 million transistors. This high density allows
`for
`true systemdevel
`integration on a
`chip, with digital
`signal processors.
`microprocessors or microcontroller cores, memory. analog or mined—signal functions all
`residing on the same die.
`
`As educators we are often asked by our students, "Isn't analog dead? I thought
`everything was going digital!" How untrue! The prediction of the future demise of
`analog electronics has been amund since the mid-19703. ACchding to the SIA report
`[1]. the revenues generated by analog products closely parallel the M08 logic market
`and achieved a 22.5 percent increase in 1-995. The analog. market expects to reach
`$13.2 billion in 1996 (a 9.5 percent increase) with double—digit growth projected for the
`next three years:
`in 1999, the total revenues generated by analog sales is forecasted to
`peak at $26.6 billion (11.34pEIcentof total chip salesl). However, while there is still
`
`0021
`
`
`
`x-x
`
`Preface
`
`demand for analog designers, their role-is definitely changing. As was communicated
`by Paul Gray in [3], the days of pure analog design are over, meaning that very few
`systems remain purely analog. More and more-systems are integrated, with increased
`functionality being performed in the digital domain. He goes on [estate that the analog
`designer should bemme broad»based. with analog transistor-level design as the core
`skill. This means that the analog designer should also
`
`' Have a good understanding of digital very large soale integration (VLSI) and
`be competent at using the latest computer-aided design (CAD) tools.
`
`-
`
`-
`
`know-how to apply digital signal processing (DSP). analog signal processing
`(ASP)1 and filtering concepts to System—level design.
`
`possess insight into system implications of component-level performance-
`
`For example. DSP and transistor-level analog design skills are needed for oversampling
`applications such as data converters. filtering. and a host of relatively new circuit
`topologies based on sigtnaedelta modulation. Being able to design both analog and
`digital circuits, as well as understand the interactions between the two domains, will
`provide an added dimension to a designer's portfolio that is difficult to match. Analog
`designers are in demand more than ever, simply because the end limitations of digital
`electronics need to be examined under the "analog" microscope to fully understand the
`mechanisms that are occurring. Therefore, this text attempts to combine digital and
`analog IC design in one complete reference.
`
`Layout is the process of physically defining the layers that compose an integrated
`circuit. Typically,
`layouts are constructed using a computenaided design program.
`CAD companies such as Mentor Graphics, Synopsis, and Cadence specialize in
`providing extremely powarful CAD software for the entire integrated circuit (IC) design
`process. including design; synthesis, simulationt and layout tools within an integrated
`framework. These Workstation-based software.
`tools can literally coast millions of
`dollars. but provide convenient and powerful features found nowhere else. CAD tools
`also exist for the PC. Tanner Tool's LsEdit provides a complete IC design CAD
`program for the personal Computer. The program discussed in‘ this book, LAyOut
`System for Individuals (LASI) (pronounced "LAZY"), also provides the student with the
`ability to lay out ICs on a PC and includes design rule checking and design verification
`capability. It is distributed as shareware, free for educational purposes.
`
`With decreases in feature size come added complexities in the design. Layouts
`must now be considered heavily i_n the design process as matching and parasitic effects
`become the limiting factors in many precision and high-speed applications. The more
`the designer knows about the process with respect to layout and modeling. the more
`performance the engineer can "squeeze" out the design. However, performance is not
`the only reason to consider the layout. The economic impact of IC layouts Can be
`detrimental to the oir-cuit's marketing potential.
`In some cases a 20 percent increase in
`chip. area can reduce the profits of a chip by several hundreds of thOusands of dollars.
`Chip area should be considered as premium real estate. Therefore, much of the first ten
`
`0022
`
`
`
`Preface
`
`xxi
`
`chapters of this book 'is devoted to fundamental
`presented as the need arises.
`
`layout
`
`issues, with other issues
`
`Modeling is also a key issue. A simulation is only as accurate as its model.
`Although the Berkeley Short-channel IGFET Model (BSIM) model has become the
`industry standard its relatively nonintuitive structure makes hand analysis using BSIM
`model parameters an intimidating process. To many students (and engineers).
`the
`BSIM parameters are nothing more than sets of numbers at the end of their SPICE
`decks. However. some very useful information can be gleaned from the BSIM model
`which helps make the hand analysis more closely resemble the simulated result.
`Chapter 6 provides a great deal of information that relates the BSIM model
`to
`first-order handsanalysis equations.
`
`A successful CMOS integrated circuit design engineer has knowledge in the
`areas of device operation. circuit design.
`layout. and simulation. Students learning
`CMOS [C design should be trained at a fundamental level in these areas.
`In the past.
`courses on CMOS integrated circuits dealt mainly with circuit design or analysis. Little
`to no time was spent on layout of the integrated circuits. This may have been justified.
`It is difficult to find a reason to lay out an entire chip and then not have the chip
`fabricated. However, through the use of the MOSIS‘ program. students can submit their
`chip designs for fabrication through one of the MOSIS‘ contracted vendors-
`in
`approximately ten weeks the chips are returned to the university for evaluation. The
`MOSIS program is an outstanding way of introducing students to the design of 10;.
`
`Although many texts [432] are available covering some aspects of CMOS
`analog or digital cirtuit design. none integrates the coverage of both topics with layout
`and includes- layout SoftWare as is done in this text. Our focus. when writing this text.
`was on the fundamentals of coatom CMOS integrated circuit design.
`It wasour goal
`that a student who studies and masters the material
`in this text will possess the.
`fundamental skills needed to design high—performance analog and digital CMOS
`circuits and have the basic understanding and problem-solving skills needed to enhance
`the performance of an [O or to determine why an IC doesn‘t function as simulated.
`
`Use of This Text
`
`This text can be used for two courses. Both courses can be offered at the seniorlfirst-
`year graduate level. The first course concent‘ratEs on the physical design of CMDS
`digital integrated circuits with prerequisites of junior level Electronics 1 and a course on
`digital logic design. A possible semester Course outline is as follows.
`
`Week 1
`
`Week 2
`
`Chs. l & 2., introduction, course requirements. layout and SPICE
`demonstrations. the n-well. sheet resistance.
`
`Chs. 2 d: 3, the nvwell. pn junction. capacitance. resistance, delay
`through the well. introduction to the metal layers.
`
`' MOSIS - MOS Implementation System through the Information Sciences institute at the
`University of Southern California. (310) 322—151 I or httpflwwwxriosiaorg.
`
`0023
`
`
`
`Xxii
`
`Week 3
`
`Week 4
`
`Week 5
`
`Week 6
`
`Week?
`
`Week 8
`
`Week 9
`
`Week to
`
`Week 11
`
`Week )2
`
`Week 13
`
`Week l4
`
`Week 15
`
`Preface
`
`Chs. 3 8:4. the metal layers. parasitics. electonfigmtion. layout of the
`padframe. activelpoly layers. layout of the MOSFET and standard frame.
`
`Ch. 5, MOSFE'I.‘ operation
`
`Chs. 5 & 6. completion of MOSFET operation. discussion of r‘nodeling
`using the BSW model.
`
`Chs. 6 & 7. completion of BSIM model. layout of a capacitor, MOS temp
`dependence.
`
`Chs. 10 3: ll. digital models and the inverter.
`
`Ch. l'l, the interior, switching point voltage and switching times. layout,
`latch—up. and design.
`
`Ch. 12, static logic gates. switching point voltages. speed. and layout.
`
`C115. 13 3: 14, the n-afismission gate. flip-flops, and dynamic logic gates.
`
`Chs. 15 e lo. VLSI layout and BECMOS logic.
`
`Ch. [7, memory circuits. basic memory cells. and organization.
`
`Ch. l8. special~purpose digital circuits.
`
`Ch. 19, introduction to digital phase locked loops. phase detectors.
`VCOs.
`
`Ch. 19, digital PLL design.
`
`The second course concentrates on CMOS analog circuit design. A possible semester
`course outline is as follows.
`
`Weeks 1 8: 2
`
`Review of Chs. L6.
`
`Week 3
`
`Week 4
`
`Week 5
`
`Week 6
`
`Week 7
`
`Week 8
`
`Week 9
`
`Chs. 7. CMOS passive elements. noise characteristics.
`
`Ch. 9. analog MOSFET models.
`
`Ch. 20. current sources and sinks.
`
`Ch. 21. references.
`
`Ch. 22. amplifiers.
`
`Ch. 23. selected togics in feedback amplifier design.
`
`Ch. 24. differential ainplifiers.
`
`Weeks 10- l2
`
`Ch. 25. operatiOnal amplifiers.
`
`Week 13
`
`Week 14
`
`Ch. 26, nonlinear analog circuits.
`
`Ch. 27, dynamic analog circuits.
`
`0024
`
`
`
`Preface
`
`xxi ii
`
`Week 15
`
`Chs. 28 8:29, selected topics in data converter design.
`
`This text can also be used as an accompanying text in a VLSI systéms course that
`focuses on the-implementation of systems rather than- circuits. Use of the text in this
`manner is benefited by inclusion of the LASI layout software,
`REFERENCES
`
`[1]
`
`[2]
`
`[3]
`
`Revised Forecast for Worid Chip Market Shows Growth of 6.7% in i996. 19%
`by i999, Semiconductor Forcast Summary 19954998, Semiconductor Industry
`Association.
`
`"New TI Technology Doubles Transiétor Density." Texas
`Integration- Newsletter. Vol. 13, No. 5, July 1995.
`
`insrmmgnm
`
`"Possible Analog IC Scenarios
`P'. Gray,
`eons.berkeIEy.eduislides.htrnl
`
`for
`
`the 90's."
`
`http:/fkahuki.
`
`Digital! Circuits and V1.5! System Design
`
`14]
`
`[5]
`
`[6]
`
`171
`
`13]
`
`191
`
`[ 1'0]
`
`1111
`
`[12]
`
`[131
`
`[I4]
`
`[151
`
`C. Mead and L. Conway, introduction to VLSi Systems, Addison—Wesley, 1930.
`
`Glasser and Dopperpuhl, The Design and Anaiys'is of VLSI Circuits. Addison
`Wesley, 1935..
`
`M. Annaralone, Digital CMOS Circuit Design, Kluwer, 1936.
`
`A. Mukherjee, Introduction to NMOS and CMOS VLSJ Systems Design,
`Prentice—Hall Publishers, 1986. ISBN 0—13—490947-X
`
`D. A. Hodges and H. G- Jackson. Analysis and Design of Digital integrated-
`Circuits, McGraw—I-Iill , 2nd ed.. 1988. ISBN 0 - 07 - 029158 — 6.
`
`M. Shoji-, CMOS Digitoi Circuit Technoiogy, Premioe—Hall. 1988.
`D-l 343885.09.
`
`ISBN
`
`P. Uyemura, Fundamntais of MOS Digital
`I.
`Addison-Wesley, 1988. ISBN (1-201-13318-0.
`
`Integrated Circuits,
`
`R. L. Geiger, P. E. Allen, and N. 'R. Strader, VLSI —.Design Techniques for
`Analog and Digirai Circuits, McGra'w-Hill, 1990.
`lSBN 0—07~023253.—9.