United States Patent
`Tobita et al.
`
`[19]
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`INCLUDING STABILIZING CAPACITIVE
`ELEMENTS EACH HAVING A MOS
`CAPACITOR STRUCTURE
`
`[75]
`
`Inventors: Yoichi Tobita; Kenji Tokami, both of
`Hyogo, Japan
`
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`[21] Appl. No.: 471,047
`
`[22]
`
`Filed:
`
`Jun. 6, 1995
`
`lllllllllllllllllllllllllllIlllllllllllllllllllllllllllllllllllllllllllllll
`US005544102A
`
`[11] Patent Number:
`
`5,544,102
`
`[45] Date of Patent:
`
`Aug. 6, 1996
`
`4,980,799 12/1990 Tobita ..................................... 361/311
`
`FOREIGN PATENT DOCUMENTS
`
`of 1974
`49—114337
`2-273393 of 1990
`
`Japan.
`Japan.
`
`OTHER PUBLICATIONS
`
`Martino Jr., et 21., “An On—Chip Back—Bias Generator for
`MOS Dynamic Memory”, IEEE Journal of Solid—State
`Circuits, vol. SC—15, No. 5, Oct. 1980, pp. 820—826.
`
`Primary Examiner—David C. Nelms
`Assistant Examiner—F. Niranjan
`Attorney, Agent, or Firm—Lowe, Price, LeBlanc & Becker
`
`Related US. Application Data
`
`[57]
`
`ABSTRACT
`
`[63] Continuation of Ser. No. 151,248, Nov. 12, 1993.
`
`[30]
`
`Foreign Application Priority Data
`
`Dec. 18, 1992
`
`[JP]
`
`Japan .................................... 4—338705
`
`Int. Cl.6 ....................................................... G11C 7/00
`[51]
`[52] US. Cl.
`................................ 365/189.09; 365/189.01;
`365/226
`
`[58] Field of Search ............................... 365l189.09, 226,
`365/189.01, 149, 182
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`In a semiconductor memory device including a boosting
`circuit for generating a high voltage constantly, and a word
`line driving circuit for transmitting a high voltage from the
`boosting circuit on a selected word line, a capacitor for
`stabilizing the high voltage generated by the boosting circuit
`is formed of a series of capacitive elements using a FET
`having a gate insulating film identical in thickness to that of
`a insulating gate type field efiect transistor in the memory
`device. A voltage applied across each capacitive element is
`relaxed, and the capacitor is improved in dielectric break-
`down voltage characteristics,
`to stably supply the high
`voltage.
`
`4,788,664
`
`11/1988 Tobita ..................................... 361/311
`
`6 Claims, 18 Drawing Sheets
`
`Vpp
`
`203:5’1:1 &
`231b 4213
`3.33
`218
`
`1“” 33a
`
`/33b
`
`I
`
`
`
`AMD EX1022
`
`US. Patent No. 6,239,614
`
`0001
`
`AMD EX1022
`U.S. Patent No. 6,239,614
`
`

`

`US. Patent
`
`Aug. 6, 1996
`
`Sheet 1 of 18
`
`5,544,102
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`US. Patent
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`Aug. 6, 1996
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`5,544,102
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`US. Patent
`
`Aug. 6, 1996
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`
`5,544,102
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 4 of 18
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`5,544,102
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`US. Patent
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`Aug. 6, 1996
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`5,544,102
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`US. Patent
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`Aug. 6, 1996
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`5,544,102
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`US. Patent
`
`Aug. 6, 1996
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`Sheet 7 of 18
`
`5,544,102
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`US. Patent
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`Aug. 6, 1996
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`5,544,102
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`US. Patent
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`Aug. 6, 1996
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`5,544,102
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 10 of 18
`
`5,544,102
`
`FIG.‘
`[1.1
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 11 of 18
`
`5,544,102
`
`FIG.
`
`23A
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`

`US. Patent
`
`Aug. 6, 1996
`
`Sheet 12 of 18
`
`5,544,102
`
`FIG. 24
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` SAME GATE INSULATING
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`LEAD
`TERMINAL
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`FILM THICKNESS
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 13 of 18
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`5,544,102
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 14 of 18
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`5,544,102
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`US. Patent
`
`Aug. 6, 1996
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 16 of 18
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`5,544,102
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 17 of 18
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`5,544,102
`
`FIG. 29 PRIORART
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`US. Patent
`
`Aug. 6, 1996
`
`Sheet 18 of 18
`
`5,544,102
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`

`5,544,102
`
`1
`SEMICONDUCTOR IVEMORY DEVICE
`INCLUDING STABILIZING CAPACITIVE
`ELEMENTS EACH HAVING A MOS
`CAPACITOR STRUCTURE
`
`This application is a continuation of application Ser. No.
`08/151,248 filed Nov. 12, 1993.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to semiconductor memory
`devices, and more particularly, to improvement of a circuit
`for transmitting a driving signal boosted to a potential level
`exceeding internal power supply voltage to a selected word
`line. Particularly, the present invention relates to a structure
`for stabilizing an output voltage of a boosting circuit used
`for generating a boosted word line driving signal and a
`structure of an input buffer for receiving an external signal.
`2. Description of the Background Art
`FIG. 25 schematically shows a structure of a conventional
`dynamic random access memory. Referring to FIG. 25, a
`dynamic random access memory includes a memory cell
`array MA in which memory cells for storing information are
`arranged in a matrix of rows and columns, an address buffer
`AB responsive to externally applied address AO-An for
`generating an internal address, an X decoder ADX for
`receiving an internal row address from address bufierAB for
`generating a word line selecting signal selecting a corre-
`sponding row of memory cell array MA, a word line driving
`circuit WD responsive to a word line selecting signal from
`X decoder ADX for amplifying this word line selecting
`signal to transmit the same to a selected row (word line), and
`an Y decoder ADY for receiving an internal column address
`from address buffer AB for generating a column selecting
`signal selecting a corresponding column out of memory cell
`array MA.
`Address bufler AB receives in a time-divisional manner a
`row address specifying a row and a column address speci-
`fying a column out of memory cell array MA for generating
`an internal row address and an internal column address at
`respective predetermined timings to provide the same to X
`decoder ADX and Y decoder ADY.
`
`In order to read out data from a memory cell specified by
`external address AO-An (a memory cell provided corre-
`sponding to a crossing of a selected row and column), the
`dynamic random access memory includes a sense amplifier
`for detecting and amplifying data of a memory cell con-
`nected to a row selected by a word line selecting signal from
`X decoder ADX and to which a driving signal is transmitted
`by word line driving circuit WD, and an input/output inter-
`face (10) responsive to a column selecting signal from Y
`decoder ADY for transmitting to an output buffer OB data of
`a memory cell connected to a corresponding column out of
`the memory cells of a selected row (word line). In FIG. 25,
`the sense amplifier and the input/output interface (10) are
`indicated by one block SI.
`Output buffer OB generates an external read out data from
`internal data transmitted via input/output interface (10) to
`provide the same external to the device.
`
`Although only output buffer OB for reading out the data
`is indicated in FIG. 25, an input buffer is also provided for
`writing data. This input buffer may be implemented to input
`data from an external device via a pin terminal identical to
`that of output buffer OB or via a different pin terminal. An
`input buffer generates an internal write data from an exter-
`
`2
`nally applied write data to write the data into a selected
`memory cell via an input/output interface (I/O).
`Control signal generating peripheral circuitry CG for
`generating control signals to control various operation tim-
`ings of a dynamic random access memory is provided.
`Control signal generating peripheral circuitry CG responds
`to an externally applied control clock signal,
`i.e. a row
`address strobe signal/RAS, a column address strobe signal/
`CAS, and a write enable signal/WE to generate a word line
`driving signal ¢x, an equalize signal ¢E, a precharge signal
`(pp, and sense amplifier activation signals ¢A and q)B.
`Control signal generating peripheral circuitry CG also gen—
`erates a precharge potential VB for precharging a bit line or
`the like to a predetermined potential.
`
`FIG. 26 schematically shows a structure of the memory
`cell array of FIG. 25 and relating circuitry. Referring to FIG.
`26, a memory cell array MA includes a plurality of memory
`cells 1 arranged in a matrix of rows and columns (n rows, m
`columns), word lines WLl, WL2,
`.
`.
`.
`, WLn provided
`corresponding to the rows of memory cell array MA, and bit
`lines BLO, lBLO, BLl, lBLl, .
`.
`.
`, BLm, lBLm, provided
`corresponding to each column in memory cell array MA. A
`bit line BL (indicating generically bit lines BLO-BLm) and
`a bit line/BL (indicating generically complementary bit lines
`/BLO-/BLm) form a folded type complementary bit line pair.
`One pair of bit lines connects memory cells 1 of one column
`in memory cell array MA.
`
`In FIG. 26, a bit line BLO and a complementary bit line
`/BLO form a pair of bit lines, and a bit line BLl and a
`complementary bit line lBLl form another pair of bit lines.
`Similarly, a bit line BLm and a complementary bit line BLm
`form a pair of bit lines.
`
`A memory cell 1 is provided corresponding to the cross-
`ing of one word line and one of the pair of bit lines. More
`specifically, memory cell 1 is provided corresponding to the
`crossing of one word line WL (indicating generically word
`lines WLl-WLn) and one of the bit line pair BL or /BL.
`A precharge/equalize (PIE) circuit 150 for equalizing the
`potential of each bit line at the time of standby of a dynamic
`random access memory and for precharging to a predeter-
`mined potential VB is provided to each pair of bit lines BLO,
`lBLO, .
`.
`.
`, BLm, lBLm. Each precharge/equalize circuit 150
`attains a conducting state in response to a precharge desig-
`nating signal ¢P and an equalize designating signal ¢E to
`precharge and equalize the potential of each bit lines BLO,
`lBLO—BLm, [BLm to a predetermined precharge potential
`VB.
`
`A sense amplifier circuit 160 for detecting and amplifying
`data of a selected memory cell is provided for each bit line
`pairs BL and /BL. Sense amplifier circuit 160 is activated in
`response to a first sense amplifier driving signal ¢A and a
`second sense amplifier driving signal ¢B transmitted via
`signal lines 162 and 164, respectively, to detect the potential
`difference of a corresponding bit line pair for difierential
`amplification.
`
`. Tma,
`.
`Column selecting gates T0a, T0b, Tla, le, .
`Tmb are provided for each of bit line pairs B10, lBLO, .
`.
`.
`, BLm,
`lBLm,
`responsive to column selecting signals
`Y0-Ym from Y decoder ADY to attain an ON state for
`connecting a corresponding pair of bit lines to internal data
`bus DB, IDB. Internal data bus DB and /DB are connected
`to output buffer CB shown in FIG. 25.
`
`Column selecting gates T0a, T0b are provided corre-
`sponding to the pair of bit lines BLO, /BLO. Colurrm select—
`ing gates Tla and le are provided corresponding to the pair
`of bit lines BLl, lBLl. Column selecting gates Tma and
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
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`
`50
`
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`
`60
`
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`
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`
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`
`

`

`3
`
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`
`5,544,102
`
`Tmb are provided corresponding to the pair of bit lines
`BLm, lBLm.
`
`Only one of column selecting signals YO—Ym from Y
`decoder ADY is activated according to a column address,
`whereby the corresponding column selecting gate is turned
`on. As a result, a corresponding pair of bit lines is connected
`to internal data bus DB and /DB.
`
`FIG. 27 shows the structure of components associated
`with one word line of FIG. 26, and particularly indicates the
`specific structure of the circuit driving a word line.
`Referring to FIG. 27, memory cell 1 disposed at the
`crossing of a word line 3 (WLi) and a bit line 2 (BLj)
`includes a memory capacitor 6 for storing information in the
`form of charge, and a selecting transistor 5 turned on in
`response to a word line driving signal ¢xi transmitted on
`word line 3 to connect memory capacitor 6 to bit line 2.
`Selecting transistor 5 is formed of an n channel insulating
`gate type field effect
`transistor (referred to simply as
`“n—FET” hereinafter), having the gate connected to word line
`3, the source to bit line 2, and the drain to storage node 4.
`Memory capacitor 6 has one electrode connected to the
`drain of selecting transistor 5 via storage node 4, and the
`other electrode connected to receive a potential of 1/2 the
`operating power supply potential Vcc.
`Word line 3 is accompanied with a parasitic capacitance
`7. Parasitic capacitance 7 also includes the gate capacitance
`of selecting transistor 5 of memory cell 1.
`Corresponding to word line 3 (WLi), a (unit) X decoder
`ADXi for decoding an internal row address from the address
`buffer for generating a word line selecting signal for word
`line 3 (WLi), and a (unit) word line driver WDi for receiving
`an output of X decoder ADXi via a node 9 and transmitting
`a word line driving signal ¢xi on word line 3 are provided.
`X decoder ADXi generates a signal of “”H (logical high)
`on node 9 when selected.
`
`Word line driver WDi includes an n-FET 14 for passing
`along a signal from X decoder ADXi provided on node 9, an
`n-FET 11 responsive to a signal on node 15 transmitted from
`n-FET 14 for transmitting a word line driving signal (bx from
`node 10 to word line 3 via a node 13, an inverter circuit 16
`for inverting an output of X decoder ADX applied on node
`9, and an n-FET 12 responsive to an output of inverter circuit
`16 for discharging the potential of word line 3 (WLi) to the
`level of ground potential via node 13.
`n~FET 14 receives an internal operating power supply
`voltage Vcc at its gate. Word line driving signal ox applied
`to node 10 is a signal boosted to a potential level higher than
`internal operating power supply voltage Vcc. Here,
`the
`potential of node 15 rises (due to capacitive coupling
`between the gate and drain of the n-FET) by the self-
`bootstrap function of n—FET 11. n-FET 14 is provided to
`prevent the boosted potential of node 15 from being trans—
`mitted to node 9. In other words, n-FET 14 functions as a
`decoupling transistor.
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`Inverter circuit 16 has a CMOS structure. The operating
`power supply voltage is set to internal operating power
`supply voltage Vcc (not shown) applied to node 8.
`Word line driver WDi functions to receive a word line
`selecting signal of the level of internal operating power
`supply voltage Vcc from X decoder ADXi and apply the
`ability of driving word line 3 to this signal.
`In order to generate a word line driving signal (bit of a
`boosted potential level, a high voltage generation circuit
`HVG and a word line driving signal generation circuit HSG
`are provided. High voltage generation circuit HVG responds
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`to a pulse-like repetitive signal ¢c to boost constantly
`internal operating power supply voltage Vcc for generating
`a boosted high voltage Vpp. Word line driving signal gen-
`eration circuit HSG responds to a clock signal ¢x0 for
`transmitting high voltage Vpp generated from high voltage
`generation circuit HVG to a node 18 as a word line driving
`signal ox. A clock signal ¢x0 is generated at a timing before
`the output potential of X decoder ADXi
`is ascertained
`(generated after a predetermined time elapse in response to
`the fall of row address strobe signal/RAS).
`The repetitive signal the is generated from an on-chip ring
`oscillator or provided from an external source.
`High voltage generation circuit HVG includes an n—FET
`29 provided between internal power supply voltage node 8
`and node 32, an n-FET 30 provided between nodes 35 and
`27, a capacitor 31 provided between nodes 28 and 35, and
`a capacitor 33 provided between output node 27 and a
`second power supply voltage supplying source (ground
`potential source).
`
`n—FET 29 has its gate and drain connected to charge the
`node 32 according to internal operating power supply volt-
`age Vcc applied to node 8. n-FET 30 has the gate and drain
`connected and functions as a diode. Capacitor 31 provides
`capacitive coupling between nodes 28 and 35. Node 35
`(node 32) is accompanied with a parasitic capacitance 34.
`Capacitor 33 serves to stabilize a high voltage Vpp generated
`at output node 27. Capacitor 31 serves to boost the potential
`level of node 35 by the repetitive signal the. High voltage
`generation circuit HVG generates high voltage Vpp of a
`voltage level higher than internal power supply voltage Vcc
`by the charge pumping function of capacitor 31.
`Word line driving signal generation circuit HSG includes
`a p channel
`insulating gate type field effect
`transistor
`(referred to simply as “p-FET” hereinafter) 23 provided
`between nodes 17 and 25, a p-FET 20 provided between
`nodes 17 and 22, an n—FET 24 responsive to a control signal
`¢x0 provided to node 19 for discharging node 25 to the level
`of ground potential, an inverter circuit 26 for inverting
`control signal ¢x0, and an n—FET 21 responsive to an output
`of inverter circuit 26 for reducing the potential of node 22 to
`ground level. p—FET 23 and p-FET 20 have their gates and
`drains cross-coupled. High voltage Vpp from high voltage
`generation circuit HVG is transmitted to node 17. A word
`line driving signal (bx is generated to an output node 18 of
`word line driving signal generation circuit HSG. Word line
`driving signal generation circuit HSG functions to convert
`control signal ¢x0 of the level of internal operating power
`supply voltage Vcc applied to node 19 to a word line driving
`signal (bx of a level of high voltage Vpp. The structure of
`such a circuit with this function is disclosed in Japanese
`Patent Laying Open No. 49-114337.
`High voltage generation circuit HVG and word line
`driving signal generation circuit HSG are included in control
`signal generating peripheral circuitry CSG shown in FIG.
`25. Inverter circuit 26 has a CXOS structure to operate with
`internal operating power supply voltage Vcc as the operating
`power supply voltage. High voltage generation circuit HVG
`and word line driving signal generation circuit HSG are
`provided in common to respective word lined drivers pro-
`vided for word line 3 (word lines WLO—WLn). The operation
`of each circuit shown in FIG. 27 will be described herein-
`after.
`
`the operation of high voltage generation circuit
`First,
`HVG will be described with reference to FIG. 28 which is
`an operation waveform diagram thereof. A repetitive signal
`the applied to node 28 is generated from an on-chip or
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`external oscillation circuit utilizing ring oscillation. The
`signal ¢c is assumed to be a pulse signal having a prede-
`termined period and pulse width.
`When internal operating power supply voltage Vcc is
`applied to internal operating power supply voltage terminal
`8, the potentials of nodes 32 and 35 are charged to the
`potential level of Vcc —VTN by charging n-FET 29. Here,
`VTN is the threshold voltage of n-FET 29. By rectifying
`n-FET 30, the potential level of node 27 is charged to the
`potential level of Vcc —2-VTN.
`
`The provision of repetitive signal the to node 28 causes
`initiation of a boosting operation in high voltage generation
`circuit HVG. For the sake of simplification, it is assumed
`that the boosting operation in high voltage generation circuit
`HVG is initiated after the potential level of node 32 and
`output node 27 are stabilized to the above-described poten-
`tial levels of Vcc—VTN and Vcc—2-VTN.
`
`When repetitive signal the rises after the potentials of node
`32 and output node 27 attain the level of Vcc—VTN and
`Vcc—Z-VTN, respectively, charge is introduced to node 35
`via boosting capacitor 31. Therefore, the potential of node
`35 rises. This potential rise of node 35 causes charge to be
`provided to output node 27 via n-FET 30, whereby potential
`V27 of output node 27 is raised by:
`
`AV27=C31-Vcc/(C31+C33)
`
`Here, C31 represents the capacitance value of boosting
`capacitor 31, and C33 represents the capacitance value of
`stabilizing capacitor 33.
`When repetitive signal the falls, the potential of node 32
`(node 35) is decreased due to capacitive coupling by boost-
`ing capacitor 31. However, because n-FET 30 has the gate
`and drain connected to serve as a diode, it enters a non-
`conducting state, and potential V27 of output node 27 is not
`decreased and maintains the potential boosted at the time of
`the prior rise of repetitive signal ¢c. In response to the fall
`of repetitive signal (pc, the potentials of nodes 32 and 35 are
`charged by n-FET 29 to be restored to the level of Vcc—
`VTN.
`
`By repeating the above—described operation, charges are
`injected into nodes 32 and 35 via boosting capacitor 31.
`Charge is introduced to output node 27 via n-FET 30 every
`time the potential thereat rises. As a result, the potential of
`output node 27 gradually rises.
`The eventual potential V32max of node 32 (node 35) is as
`follows:
`
`V32max=(Vcc—-VTN)+C31-Vcc/(C31+C34)
`
`where C34 represents the capacitance value of parasitic
`capacitance 34. Here, potential V27 of output node 27
`attains a value lower by the threshold voltage VTN of n—FET
`30 than the potential V32 (=V35) of node 32 (node 35).
`More specifically, the eventual potential V27max of output
`node 27 is as follows:
`
`V27max=V32max —VTN=(Vcc—2-WN)+C31-Vcc/(C31+C34)
`
`In practice, capacitance value C31 of boosting capacitor
`31 can easily be made high enough in comparison with
`capacitance value C34 of parasitic capacitance 34. There-
`fore, the third term in the above two equations are approxi—
`mately equal to internal operating power supply voltage
`Vcc. Suppose Vcc=3.3V, and VTN:0.8V,
`the potential
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`V27max of output node 27 is as set forth in the following
`from the above equation.
`
`V27max=2(Vcc—VTN)=S.0(V)
`
`More specifically, potential V27max of output node 27 is
`approximately 1.5 times the internal operating power supply
`voltage Vcc. This high voltage is stabilized by a stabilizing
`capacitor 33 having a great capacitance value.
`The operation of a word line driving signal generation
`circuit and a word line driver will be described with refer-
`ence to FIG. 29 which is a waveform diagram thereof.
`At time t0 when control signal ¢x0 attains a L level
`(logical low), n-FET 24 is turned oif and n-FET 21 is turned
`on by inverter circuit 26. Therefore, the potential of node 22
`attains the L level of ground potential, and the potential of
`node 25 attains the level of high voltage Vpp applied to node
`17 via p-FET 23. When the potential of node 25 attains the
`level of high voltage Vpp, p-FET 20 is completely turned
`oil”, so that the potential of node 22 is reliably discharged to
`the level of ground potential via n-FET 20. The potential of
`word line driving signal
`(bx reliably attains the level of
`ground potential.
`In word line driver WDi, the output potential (the poten-
`tial of node 9) of X decoder ADXi attains a L level (ground
`potential level), whereby n-FET 12 and n-FET 11 are turned
`on and off, respectively. As a result, the potential level of
`word line driving signal qui on word line 3 attains the L level
`of ground potential.
`Next, when row address strobe signal IRAS (refer to FIG.
`25) falls to a L level, a row selecting operation is initiated.
`In response to the fall of row address strobe signal IRAS, X
`decoder ADX (refer to FIG. 25) executes a row selecting
`operation. Here, it is assumed that (unit) X decoder ADXi
`shown in FIG. 27 is selected.
`At time t1 when the potential level of node 9 rises to the
`level of internal power supply voltage Vcc, the output of
`inverter circuit 16 of word line driver WDi attains a L level
`of ground potential, whereby n-FET 12 is turned off from an
`on state. Also, node 15 is charged from node 9 via nvFET 14
`to increase in potential. Between nodes 9 and 15, n—FET 14
`is provided having the gate connected to power supply
`voltage node 8 supplying internal operating power supply
`voltage Vcc. Therefore, the potential level of node 15 rises
`to the potential
`level of Vcc—VTN. Here, VTN is the
`threshold voltage of n—FET 14. Therefore n-FET 11 is turned
`on, and word line 3 is discharged via n-FET 11 and n-FET
`21 to maintain the level of ground potential.
`When the potential level of node 9 is stabilized, control
`signal ¢x0 applied to node 19 rises to the H level at time t2.
`In response to the fall of row address strobe signal IRAS
`control signal ¢x0 rises to the level of internal operating
`power supply voltage Vcc after a predetermined time. The
`rise of control signal ¢x0 to the level of internal operating
`power supply voltage Vcc causes n-FET 24 to be turned on
`and n-FET 21 to be turned ofi‘. As a result, node 25 is
`discharged to the level of ground potential by n-FET 24. In
`response, p-FET 20 is turned on to raise the potential of node
`22. Eventually, when p-FET 23 is turned oif and node 25
`falls to the level of ground potential, the potential level of
`node 22 attains the level of high voltage Vpp applied to node
`17 via p-FET 20. As a result, a word line driving signal (bx
`is generated.
`When word line driving signal ¢x of the level of high
`voltage Vpp is applied to node 10 in word line driver WDi,
`the potential level of node 15 rises by the voltage change of
`node 10 (by high voltage Vpp) due to the self bootstrap
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`function of n-FET 11 (by the capacitive coupling between
`the gate and drain of n-FET). As a result, the potential level
`of node 15 becomes Vcc—VTN+Vpp, i.e. exceeds Vpp+
`VTN. Therefore, there is no loss of the threshold voltage in
`n-FET 11, and the potential level of word line driving signal
`¢xi transmitted on word line 3 rises to the level of high
`voltage Vpp.
`The rise of word line driving signal ¢xi transmitted to
`word line 3 up to the level of high voltage Vpp causes the
`selecting transistor 5 in memory cell 1 to attain a deep on
`seats rapidly. Therefore,
`the charge stored in memory
`capacitor 6 is transmitted on bit line 2 without loss of the
`threshold voltage of selecting transistor (n—FET) 5.
`Then,
`the sensing operation of the sense amplifier is
`carried out, followed by reading or writing of data of a
`selected memory cell.
`When one memory cycle is completed, control signal ¢x0
`falls to the L level and the output of X decoder ADXi also
`fails to the L level at time t3. The potentials of each signal
`and node are restored to the state of time t0.
`i.e. potential
`The charging operation of word line 3,
`increase thereof, will be described in detail hereinafter.
`The charging operation of word line 3 is realized by the
`transfer of charge from stabilizing capacitor 33 in high
`voltage generation circuit HVG to parasitic capacitance 7 of
`word line 3. Therefore, the potential level of output node 27
`of high voltage generation circuit HVG is slightly reduced
`since charge is transferred to word line 3 at the time of word
`line selection. However, if the capacitance value of stabi-
`lizing capacitor 33 is set to a value sufliciently greater than
`the capacitance value of parasitic capacitance 7 of word line
`3, there is almost no decrease in the potential level of output
`node 27. Therefore, the potential level of a selected word
`line can maintain the level of high voltage Vpp.
`Because the potential level V(WL) of word line 3 can be
`obtained by:
`
`V(WL)=C33-Vpp/(633+C7)
`
`the potential level on word line 3 can take the level of high
`voltage Vpp if the capacitance value C7 of parasitic capaci-
`tance 7 is small enough to be neglected in comparison with
`the capacitance value C33 of stabilizing capacitor 33.
`From the standpoint of high density and high integration
`density, stabilizing capacitor 33 must have superior space
`efficiency that can realize a relatively high capacitance value
`with a small occupying area. A MOS capacitor utilizing an
`insulating gate type field effect
`transistor is generally
`employed as such capacitors.
`FIG. 30 is a MOS capacitor wherein (A) shows a sectional
`view thereof,
`(B) shows an electrical connection circuit
`thereof, and (C) shows an electrical equivalent circuit
`thereof.
`
`Referring to FIG. 30 (A), a MOS capacitor includes N
`type impurity regions 102a and 1021; formed at a predeter-
`mined region on a P type semiconductor substrate 101, a
`gate insulating film (capacitor insulating film) 104 formed
`on the surface of semiconductor substrate 101, and a gate
`electrode 103 formed on gate insulating film 104. Impurity
`regions 102a and 1021: provide one electrode leading portion
`of the capacitor (in FIG. 30 (A),
`the electrode leading
`portion connected to ground potential GND,
`i.e. ground
`line). Gate electrode 103 implements the other electrode of
`the capacitor, and is formed of polycrystalline silicon,
`refractory metal silicide such as molybdenum silicide or
`tungsten silicide, or a multilayer structure of polycrystalline
`silicon and refractory metal silicide.
`
`Gate electrode 103 is connected to output node 27 receiv-
`ing high voltage Vpp. The power supply and ground lines
`between gate electrode 103 and output node 27 are formed
`of a low resistance metal such as aluminum. Gate insulating
`film 104 is formed using an insulating film such as silicon
`dioxide (Si02) film. The source and drain electrode 108 is
`formed of a low resistance conductor such as aluminum to
`provide electrical contact with impurity regions 102a and
`102b. Ground potential GND from the ground line is applied
`to impurity regions 102a and 102b.
`An interlayer insulating film 109 is provided to electri—
`cally insulate the electrodes 103 and 108 from each other.
`When a voltage exceeding the threshold voltage is applied
`to gate electrode 103, an inversion layer (N type inversion
`layer) 101 is formed at the surface of semiconductor sub-
`strate 101. This inversion layer 101 forms one electrode of
`the capacitor. More specifically,
`in the MOS capacitor
`shown in FIG. 30 (A), one electrode of the capacitor is
`inversion layer 101, and the other electrode is gate electrode
`103. Ground potential GND is applied to inversion layer 101
`via impurity region 102. When connection of one electrode
`to ground potential GND is realized and high voltage Vpp is
`applied to the other electrode (gate electrode 103),
`this
`capacitor functions as the stabilizing capacitor shown in
`FIG. 27.
`
`A MOS capacitor has a structure identical to a MOS
`transistor (insulating gate type field effect transistor) used
`within a memory chip.
`It can be regarded as a MOS
`transistor having the source electrode and the drain electrode
`connected in common to ground potential GND (refer to
`FIG. 30 (B) and (C)).
`A ca