United States Patent
`
`[19]
`
`[11] Patent Number:
`
`‘
`
`4,499,387
`
`[45] Date of Patent:
`Konishi
`Feb. 12, 1985
`
`[54]
`
`INTEGRATED CIRCUIT FORMED ON A
`SEMICONDUCTOR SUBSTRATE WITH A
`VARIABLE CAPACITOR CIRCUIT
`
`[75]
`
`Inventor:
`
`Satoshi Konishi, Tokyo, Japan
`
`[73] Assignee:
`
`Tokyo Shibaura Denki Kabushiki
`Kaisha, Japan
`
`[21] App]. No.: 446,724
`
`[22] Filed:
`
`Dec. 3, 1982
`
`Foreign Application Priority Data
`[30]
`Dec. 15, 1981 [JP]
`Japan ................................ 56-201837
`Jan. 18, 1932 [JP]
`Japan .................................... 57-5680
`
`Int. C1.3 .......................... H03K 4/94; HO3K 5/01
`[51]
`[52] US. Cl. .................................... 307/443; 307/246;
`307/451; 307/469; 307/585; 307/268; 307/591
`Field of Search ............... 307/443, 448, 451, 468,
`307/469, 246, 574—576, 579, 581, 584, 585, 267,
`268, 591, 594, 601, 603, 605, 263
`
`[58]
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,852,619 12/1974 Carbrey ............................... 307/268
`3,872,321
`3/1975 Matsue
`307/448
`
`3/1976 Heeren ........
`3,944,848
`307/448
`
`307/578 X
`4,130,766 12/1978 Patel et a1.
`..
`8/1982 Carter ............................. 307/578 X
`4,346,310
`
`7/1983 Takahashi et a1.
`............. 307/584 X
`4,393,318
`
`1/ 1984 Shiraki et a1. ............... 307/246 X
`4,424,456
`4,455,495 6/ 1984 Masuhara et a1.
`.............. 307/465 X
`
`OTHER PUBLICATIONS
`
`Kokkonen et al., “Redundancy Techniques for Fast
`Static RAMs”; ISSCC 8l/Wednesday, Feb. 18, 1981,
`IEEE International Solid—State Conference, pp. 80—81.
`
`Primary Examiner—Stanley D. Miller
`Assistant Examiner—David R. Hudspeth
`Attorney, Agent, or Firm—Finnegan, Henderson,
`Farabow, Garrett & Dunner
`
`[57]
`
`ABSTRACT
`
`A MOS type semiconductor integrated circuit compris-
`ing a C-MOS inverter including P- and N-channel MOS
`transistors connected in series between VDD and V33
`power supply terminals, the gates of the MOS transis-
`tors being supplied with an input signal; a variable ca—
`pacitor connected between a node at which the transis-
`tors are interconnected and a reference voltage; and a
`voltage generator for producing an output voltage to
`the variable capacitor, the voltage generator being ca-
`pable of irreversibly changing the level of the output
`voltage, thereby changing a capacitance of the variable
`capacitor.
`
`23 Claims, 89 Drawing Figures
`
`
`
`
`
`AMD EX1021
`
`US. Patent No. 6,239,614
`
`Vin
`
`0001
`
`0001
`
`AMD EX1021
`U.S. Patent No. 6,239,614
`
`

`

`U.S. Patent
`
`Feb. 12,1985
`
`Sheetl on4
`
`4,499,387
`
`FIGJ
`
`_
`
`FIG.2
`
`
`
`F'
`
`|
`
`(3.44%\ V,
`VDD
`oavbD
`
`0.1 VDD
`
`.
`vm
`
`vout
`
`tf
`
`—~—t
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet20f24
`
`4,499,387
`
`
`
`0-9VDD
`VH'VTn
`
`0.1va
`0
`
`Vout
`S
`
`vin
`
`L._____.I
`W
`
`—-t
`
`
`
`F I G. 40. v1
`Vout Vin
`VDD
`
`——————————
`0.9VDD
`————————
`*—
`
`
`
`\4-I-VTn
`
`own
`
`
`0
`FT'4 ——tr
`
`FIG.5A
`
`FIG-SB
`
`VDD
`
`I
`
`QnH
`.
`
`V38
`_
`
`Vout
`
`Qpfi
`Ni
`
`sz
`1
`
`V38
`
`0003
`
`0003
`
`

`

`U.S. Patent
`
`Feb. 12,1985
`
`Sheet3 on4
`
`4,499,387
`
`FIG.5C
`
`FIG.5D
`
`
`
`0004
`
`0004
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet4 of24
`
`4,499,387
`
`FIG.9
`
`
`
`F I G. HA V,“
`
`O
`
`t
`
`F | G. NB ,ng3 _.___vo=VL yew
`
`
`
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet5 of24
`
`4,499,387
`
`FIG. 14A
`
`
`
`0006
`
`0006
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet6of24
`
`4,499,387
`
`F l G. 15A,
`
`Vin
`
`QnH
`
`
`
`FIG.1SB
`
`FIG.1SC
`
`V6=VL
`
`
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet7 of 24
`
`4,499,387
`
`FlG.i8
`
`
`
`0008
`
`
`
`IIIIA
`
`
`
` mV
`
`
`
`0008
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet8 of24
`
`4,499,387
`
` A
`
`Qn34
`
`
`
`
`
`
`
`
`
`xc ‘
`
`
`7!
`
`
`Qn31
`
`.4+
`
`0009
`
`0009
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet9 of24‘
`
`4,499,387
`
`FIG. 28
`
`FIG. 29
`
`2c] +c2+ Cg + ci +Cs
`
`60(vo=vH)
`
`cowo =vL)
`
`2cj+cgz+ 2cm+cs
`
`0010
`
`0010
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 10 on4 4,499,387
`
`F l GBOA
`
`F | 6.308 .
`
`F | G. 30C
`
`
`
`0011
`
`0011
`
`

`

`U.S. Patent
`
`Feb. 12,1985
`
`Sheet 11 of24 4,499,387
`
`
`
`
`
`
`
`31
`
`FIG. 34
`
`J—jCS,
`
`
`
`34fcg35(N)
`7/.W
`
`
`0012
`
`0012
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 12 of24 4,499,387-
`
`
`
`
`50' ( vo =VH)
`
`cj'+ C£'+ Cg'+ ci'+cs'
`
`cj’+ cj+ c m'+Cs’
`Eo’ ( vo =v,_)
`
`0013
`
`0013
`
`

`

`U.S. Patent
`
`Feb. 12,1985
`
`Sheet 13 of 24 4,499,387
`
`
`
`FIG.39B
`
`FIG 39C
`
`111—1:
`
`0014
`
`0014
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 14 of24 4,499,387
`
`FIG. 40
`
`
`
`0015
`
`0015
`
`

`

`U.S. Patent
`
`Feb. 12,1985
`
`Sheet 15 0124 4,499,387
`
`FIG. 44
`
`VDD
`
`1:16.45"
`
`
`
`
`
`
`
`F I6. 478
`
`vo=VL vo=vH
`
`0016 ,
`
`0016
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 16 of24 4,499,387
`
`FIG. 48
`
`
`
`0017
`
`0017
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 17 of24 4,499,387
`
`FIG.
`
`52
`
`
`
`0018
`
`0018
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 18 of24 4,499,387
`
`VOUT
`
`
`0019
`
`0019
`
`

`

`U.S. Patent
`
`Feb. 12,1985
`
`Sheet 19 of 24 4,499,387
`
`FIG. 58
`
`VDD
`
`prB
`
`vout
`
`\om3
`FIG. 59A
`VFIG.598
`
`V'”
`
`0020
`
`0020
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 20 on4 4,499,387
`
`F l Geo
`
`
`
`0021
`
`0021
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet21 on4 4,499,387
`
`
`vin2
`
`vim
`
`0022
`
`0022
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 22 on4 4,499,387
`
`FIG. 66
`
`
`
`0023
`
`0023
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 23 on4 4,499,387
`
`FIG. 68
`
`VOUT
`
`
`0024
`
`0024
`
`

`

`US. Patent
`
`Feb. 12,1985
`
`Sheet 24 on4 4,499,387
`
`FIG. 70
`
`
`
`VOUT
`
`0025
`
`0025
`
`

`

`4,499,387
`
`1
`
`INTEGRATED CIRCUIT FORMED ON A
`SEMICONDUCTOR SUBSTRATE WITH A
`VARIABLE CAPACITOR CIRCUIT
`
`BACKGROUND OF THE INVENTION
`
`2
`FIG. 3 illustrates a circuit arrangement when a MOS
`semiconductor integrated circuit according to the pres-
`ent invention is applied to a C-MOS inverter;
`FIGS. 4A to 4D are graphs, each illustrating input or
`output characteristic of the C—MOS semiconductor
`integrated circuit shown in FIG. 3;
`FIGS. 5A to SD are equivalent circuits, each for
`different operation modes of the C—MOS semiconductor
`integrated circuit of FIG. 3;
`FIG. 6 is a graph illustrating input and output charac—
`teristics of the C-MOS semiconductor integrated circuit
`of FIG. 3;
`FIGS. 7 to 10 are respectively circuit diagrams of
`other embodiments of a C-MOS semiconductor inte-
`grated circuit according to the present invention;
`FIGS. 11A and 11B respectively are graphical repre-
`sentations of input and output characteristics of the
`integrated circuit of FIG. 10;
`FIGS. 12, 13 and 14A are circuit diagrams of other
`embodiments of a C-MOS semiconductor integrated
`circuit according to the present invention;
`FIGS. 14B and 14C are graphical representations of
`the output characteristic of the integrated circuit shown
`in FIG. 14;
`FIG. 15A is a circuit diagram of another embodiment
`of a C-MOS semiconductor integrated circuit accord-
`ing to the present invention;
`FIGS. 15B and 15C are graphical representations of
`output characteristic of the integrated circuit of FIG.
`15A;
`FIGS. 16 to 21 are circuit diagrams of other embodi-
`ments of a semiconductor integrated circuit according
`to the present invention;
`FIGS. 22 to 24 illustrate structures of capacitors as-
`sembled into the embodiments as mentioned above;
`FIG. 25 is a circuit diagram of a variable capacitor
`circuit assembled into a semiconductor integrated cir-
`cuit according to the present invention;
`FIGS. 26 and 27 respectively show cross sectional
`views of the semiconductor integrated circuit of FIG.
`25 in which equivalent circuits for different operation
`modes are depicted;
`FIG. 28 is a graphical representation of a variation of
`a capacitance with respect to a gate-substrate voltage
`V05 of the variable capacitor circuit shown in FIG. 25;
`FIG. 29 illustrates a variation of a capacitance with
`respect to a node voltage VN in the variable capacitor
`circuit shown in FIG. 25;
`FIGS. 30A to 30C are circuit diagrams of other vari-
`able capacitor circuits composed of MOS transistors,
`respectively;
`FIG. 31 is a circuit diagram of another variable ca-
`pacitor circuit composed of a MOS capacitor;
`FIGS. 32A and 32B show a cross sectional View and
`a plan view of the variable capacitor circuit shown in
`FIG. 31;
`FIGS. 33 and 34 respectively show cross sectional
`views of the variable capacitor circuit shown in FIG. 31
`in which equivalent circuits for different operation
`modes are depicted;
`FIG. 35 shows a graph illustrating a variation in ca-
`pacitance of a variable capacitor with respect to a gate—
`substrate voltage of the variable capacitor circuit
`shown in FIG. 31;
`FIG. 36 shows a graphical representation of a varia-
`tion of capacitance of a variable capacitor with respect
`to a node voltage VN of the variable capacitor circuit
`shown in FIG. 31;
`
`The present invention relates to a MOS type semicon-
`ductor integrated circuit requiring little margin for
`signal transmission time.
`Signal transmission time in semiconductor integrated
`circuits co: posed of MOS (metal oxide semiconductor)
`type transistors is determined by transfer conductance
`“gm” of the MOS transistors which controls the volt—
`age at nodes in the circuit and stray capacitance “C” of
`those nodes. Of these two determinants, “gm” can be
`accurately estimated on the basis of the electrical per-
`formance of the transistors. Accurate estimation of the
`capacitance “C”, however,
`is difficult. Further,
`the
`capacitance “C” changes more than the conductance
`“gm” does when process parameters are changed in
`their manufacturing stage. This also makes it difficult to
`estimate, the precise capacitance values.
`Difficult estimation of the stray capacitance “C”
`results in an inexact estimation of the signal transmission
`time. It is for this reason that the prior circuit of this
`type must be designed with a relatively large margin for
`signal
`transmission time. Simultaneously, however,
`there have been technical tendencies in this field, such
`as increasing integration density and shrinkage by scal-
`ing down, towards more complicated construction of
`the semiconductor circuit and increasing operating
`speed of the circuit. To satisfy these tendencies, large
`margins in the circuit operating time must be avoided.
`In particular, the overall operating :peed of the inte-
`grated circuit is considerably limited when there is such
`a large margin in operating speed.
`SUMMARY OF THE INVENTION
`
`Accordingly, an object of the present invention is to
`provide a MOS type semiconduc..or integrated circuit
`requiring little margin for circuiv‘: operating time.
`According to the invention, there is provided a semi-
`conductor integrated circuit comprising:
`a first terminal for receiving a first power supply
`voltage;
`a second terminal for receiving a second power sup-
`ply voltage;
`a transistor circuit comprising a plurality of transis-
`tors connected in series between said first and sec-
`ond terminals, at least one of the transistors being
`supplied with an input signal at the gate thereof;
`a variable capacitor circuit connected between a
`node at which two of said transistors are intercon-
`nected and a reference voltage; and
`a voltage generator for producing an output voltage
`signal to said variable capacitor circuit, the voltage
`generator being capable of irreversibly changing
`the level of the output voltage signal
`thereby
`changing a capacitance of said variable capacitor
`circuit.
`'
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 a circuit diagram of a voltage generator incor-
`porated into a C-MOS semiconductor integrated circuit
`according to the present invention;
`FIG. 2 is a circuit diagram of another voltage genera—
`tor;
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`4o
`
`45
`
`50
`
`55
`
`6O
`
`65
`
`0026
`
`0026
`
`

`

`3
`FIG. 37 shows a plan view of an example of the vari-
`able capacitor circuit shown in FIG. 31;
`FIG. 38 shows a plan view of another example of the
`variable capacitor circuit shown in FIG. 31;
`FIGS. 39A to 39C are circuit diagrams of other ex-
`amples of the variable capacitor circuit composed of a
`MOS capacitor;
`FIG. 40 is a circuit diagram of an embodiment of a
`C-MOS semiconductor integrated circuit according to
`the present invention;
`FIG. 41 is a graphical representation of an input/out-
`put characteristic of the integrated circuit of FIG. 40;
`FIGS. 42 to 46 are circuit diagrams of other embodi-
`ments of the integrated circuit incorporating a variable
`capacitor circuit composed of a MOS transistor;
`FIGS. 47A and 47B respectively show input and
`output characteristics of the integrated circuit shown in
`FIG. 46;
`FIGS. 48 to 51 are circuit diagrams of other embodi-
`ments of the integrated circuit incorporating a variable
`capacitor circuit composed of a MOS transistor;
`FIG. 52 is a circuit diagram of a C-MOS integrated
`circuit incorporating a variable capacitor circuit com-
`posed of a MOS capacitor;
`FIG. 53 is a graph illustrating input and output char-
`acteristics of the C-MOS semiconductor integrated
`circuit of FIG. 52;
`FIGS. 54 to 58 are circuit diagrams of the integrated
`circuit incorporating a variable capacitor circuit com-
`posed of a MOS capacitor;
`FIGS. 59A and 593 respectively show input and
`output characteristics of the integrated circuit shown in
`FIG. 58;
`FIGS. 60 to 63 show circuit diagrams of other em-
`bodiments of the integrated circuit incorporating a vari-
`able capacitor circuit composed of a MOS transistor,
`respectively; and
`FIGS. 64 to 71 show circuit diagrams of other em-
`bodiments of the integrated circuit, respectively.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS ,
`
`Reference is made to FIGS. 1 and 2 illustrating volt-
`age generators incorporated into a MOS semiconductor
`integrated circuit according to the present invention. In
`the voltage generator, a P—channel MOS transistor Qpl
`and a fuse F composed of a polysilicon interconnection
`layer or a metal interconnection layer are arranged in
`series fashion between a power supply terminal
`to
`which a power supply voltage VDD with positive or
`high voltage is applied and a power supply terminal to
`which a power supply voltage V55 with negative or low
`voltage (ground level in the embodiment) is applied.
`The MOS transistor Qpl is connected at the source to
`the positive power supply voltage VDD and at the drain
`to the negative power supply voltage V55 via the fuse F.
`The gate of the MOS transistor Qpl is connected to the
`negative power supply voltage V55.
`Two MOS transistors Qp2 and in are inserted in
`series between the power supply voltages VDD and V55.
`The transistor Qp2 is of a P-channel type and the tran-
`sistor in is of an N-channel type. The source of the
`P~channel MOS transistor Qp2 is connected to the
`power supply voltage VDD- The source of the P-chan-
`nel MOS transistor Qp2 is connected to the positive
`power supply voltage VDD. The source of the N-chan-
`nel MOS transistor in is connected to the negative
`power supply voltage V55. The MOS transistors Qp2
`
`4,499,387
`
`4
`
`
`
`and in are interconnected at both drains and the inter-
`connecting point (i.e. junction node) provides an output
`voltage V0. The drain of the transistor Qpl is con-
`nected to both gates of the transistors Qp2 and in. The
`transistors Qp2 and in constitute a C-MOS (Comple-
`mentary MOS) inverter.
`In this arrangement of the voltage generator, when
`the fuse F is not blown out, the drain voltage of the
`transistor Qpl is nearly V55, and the transistor Qp2 is
`ON and the transistor in is OFF. Thus the output
`voltage Vo becomes high voltage V}; and is substan-
`tially equal to the positive power supply voltage VDD-
`On the contrary, when the fuse F is blown out, the drain
`voltage of the transistor Qpl is nearly VDD, and the
`transistor Qp2 is OFF and the transistor in is ON.
`Thus the output voltage V0 is low voltage V; and is
`substantially equal to the negative power supply volt-
`age V55. The fuse F is melted by irradiation with laser
`beams or flowing a large current into the fuse. Once the
`fuse F is blown out, the current path between the drain
`of the transistor Qpl and the negative power supply
`voltage V55 is open and left as is. Under this condition,
`once the output voltage V0 is changed to low voltage
`VL, it can not be returned to the original voltage, that is,
`to high voltage VH. In other words,
`the change, of
`voltage state is irreversible. Conversely, the change of
`voltage state low to high voltage is likewise irreversible
`when another C-MOS inverter is inserted between the
`output terminal for the output voltage V0 and the junc-
`tion node between the transistors Qp2 and in, the
`input of the inserted C-MOS inverter being connected
`to the junction node and the output to the output termi-
`n 11. Therefore, either change of voltage state from high
`to low or vice versa may be irreversible.
`A voltage generator shown in FIG. 2 is an E/D type
`voltage generator constructed by an enhancement type
`MOS transistor and two depletion type MOS transis~
`tors. The voltage generator has a series circuit of a
`depletion type MOS transistor Qpl and a fuse F be-
`tween the power supply voltages VDD and V55. The
`depletion type MOS transistor Q01 is connected at the
`drain to the positive power supply voltage VDD and at
`the source to the negative power source V55 through
`the fuse F. The gate of the transistor Q01 is connected to
`the source thereof. A depletion type MOS transistor
`QD2 serving as a load transistor and an enhancement
`type MOS transistor Q51 are further connected in series
`between the power supply voltages VDD and V55. A
`junction node between MOS transistor QD1 and the fuse
`F is connected to the gate of the MOS transistor Q51.
`The gate of the transistor QD2 is further connected to
`the junction node between the transistors QD2 and Q51.
`The output voltage V0 is derived from the junction
`node. Also in this circuit, when the fuse F is intact, the
`gate voltage of the transistor Q51 is low voltage level
`and the transistor Q51 is OFF, and the output voltage
`V0 is high (VH). Conversely, when the fuse F is blown
`out, the gate voltage of the transistor Q51 is at high
`voltage VDD and the transistor Q51 is ON. The output
`voltage V0 is thus low (VL). As in the FIG. 1 circuit,
`after the fuse F is blown out to open the path from the
`source of the transistor QD1 to the power supply voltage
`V55, the FIG. 2 circuit can not return to its original
`state, i.e. the conductive state of the fuse F. Thus, once
`the output voltage V0 is changed from the high voltage
`VH to the low voltage V; by blowing out the fuse F, the
`changed low voltage state can not be returned to the
`high voltage state. The change of voltage state from
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`4O
`
`45
`
`50
`
`55
`
`60
`
`65
`
`'
`
`0027
`
`0027
`
`

`

`5
`high to low voltage is irreversible. Similarly, the change
`of voltage state from low to high voltage is also made
`irreversible when another E/D inverter is inserted be-
`tween the output terminal for the output voltage V0
`and the junction node between the transistors Q02 and
`Q5], where the input of the inserted E/D inverter is
`connected to the junction node and the output to the
`output terminal. Therefore, either change of voltage
`state from high to low voltage or vice versa may be
`rendered irreversible.
`Turning now to FIG. 3, there is shown a circuit ar-
`rangement according to the present invention in which
`a MOS semiconductor integrated circuit is utilized as a
`C—MOS inverter.
`In the circuit shown in FIG. 3, P— and N-channel
`MOS transistors Qpll and inl make up a C-MOS
`inverter I]. The source of the P-channel MOS transistor
`Qpn is connected to the power supply voltage VDD and
`the drain to a node N1. The drain of the N-channel
`MOS transistor inl is connected to the node N1 and
`the source to the power supply voltage V55. The tran-
`sistors Qpll and Q1111 are interconnected at the gates
`and the interconnecting point,
`i.e. junction node,
`is
`impressed with an input voltage Vin. The output node
`N1 of the C-MOS inverter 11 thus arranged is connected
`to the drain of the N-channel MOS transistor Qn12. The
`source of the same transistor is connected through a
`capacitor element C1 to the power supply voltage V55.
`The gate of the transistor Qn12 is impressed with the
`output voltage Vo from the circuit as shown in FIG. 1
`or 2. In the circuit as shown in FIG. 3, a series circuit
`composed of a capacitor C1 and a MOS transistor Qn12,
`with a gate input being the output voltage Vo from the
`voltage generator as shown in FIG. 1 or 2, is inserted
`between the node N1 and the power supply voltage
`V55. A capacitor Cs inserted between the node N1 and
`the power supply voltage V55 characterizes the stray
`capacitance parasitically associated with the output
`node N1. In the FIG. 3 circuit, when tle voltage V0 is
`low (VL), the MOS transistor Qn12 is OFF. Under this
`condition, when the level of the input voltage Vin to the
`C-MOS inverter I1 is V55 voltage to VDD voltage (in
`this embodiment, V55=0(V)), as shown in FIG. 4A, the
`FIG. 3 circuit may equivalently be depicted as shown in
`FIG. 5A. The falling state of the output voltage Vout at
`node N1 corresponds to a discharging state of the ca-
`pacitor Cs when it
`is discharged through the MOS
`transistor inl, as shown in FIG. 4A. When the level
`of the input voltage Vin changes from VDD voltage to
`V55 voltage, as shown in FIG. 4B, the equivalent circuit
`of the FIG. 3 circuit is as shown in FIG. 5B. As shown,
`a rising state of the output voltage Vout at the node N1
`corresponds to a charging state of the capacitor Cs
`through the MOS transistor Qpl. Arrows in FIGS. 5A
`and 5B indicate the flows of discharging and charging
`currents, respectively. Incidentally, in FIGS. 4A and
`4B, tfand t, are respectively rise and fall times which are
`defined by the time duration between 10% and 90% of
`the power supply voltage VDD to the power supply
`voltage V55. When the output voltage V0 is high (VH),
`the transistor Qn12 is ON. In the ON state, between the
`node N1 and the power supply voltage V55, the capaci-
`tor Cl is added to the stray capacitor Cs via the transis-
`tor Qn12. The result is an increase in effective capaci-
`tance of the node N1. When the input voltage Vin is
`changed from V55 to VDD, the falling state is as shown
`in FIG. 4C and the equivalent circuit of the FIG. 3
`circuit is as shown in FIG. 5C. The falling state of the
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`output voltage Vout at node N1 changes as indicated by
`a waveform shown in FIG. 4C, because discharge cur-
`rents from the capacitors Cs and C1 additively flow at
`node N1. Next, when the input voltage Vin changes
`from VDD to V55, as shown in FIG. 4D, the FIG. 3
`circuit may equivalently be depicted as shown in FIG.
`5D. The rising state of the voltage Vout at node N1 on
`takes a time-dependence as shown in FIG. 4D, because
`the charge currents to the capacitors Cs and C1 flow
`additively together. Arrows in FIGS. 5C and 5D indi-
`cate the flows of the discharge and charge currents,
`respectively.
`The rising time t’, and falling time t'fin the voltage
`changing states shown in FIGS. 4C and 4D are larger
`than those in the potential changing states in FIGS. 4A
`and 4B, respectively. The reason for this is that the
`output voltage Vo of the voltage generator is changed
`from low to high and hence the effective electrical
`capacitance at the node is changed. Exact definitions of
`the relationships of the rising time t, and t'r and the
`falling time tfand t’fwith respect to the circuit parame—
`ter are difficult to obtain, but approximate relationships
`may be given as follows, with the assumption that the
`capacitor C1 has a linear capacitance and also includes
`the gate capacitance of the transistor Qn12, and
`Bull < <Bn12, Bp11< <Bn12, Cs/Bn11> >Cl/,Bn12,
`Cs/Bp11> >C1/fin11 and VH=VDD,
`
`tf=[
`
`C5 + Cl
`
`C:
`
`A!
`
`— t, ) tfi
`
`1r, _ Cs 2:5 Cl
`
`[r _ A1,
`
`(1)
`
`(2)
`
`where ,Bpll, Brill and [3an are [3 Ge. gain coefficient
`of transconductance) of the MOS transistors Qpll,
`inl and Qn12, respectively, and At is expressed by
`
`A‘ =
`
`(3)
`
`C]
`c:
`B"11(VDD— VT)
`
`1
`
`0.1VDD
`20/013 - VT) — V7
`" ——___2VT—0.1pr “T .
`
`In the erration (3), VTis a threshold voltage of each
`of the transstors in and Qn2. The equations (1) and
`(2) show that an effective capacitance at node N1 when
`the voltage V0 is high (VH),
`is approximately,
`(Cs+C1)/Cs times that when it is low (VL). Thus the
`rate of change of the output voltage Vout of the node
`N1 at Vo=VH is slower than that at V0=VL as shown
`in FIG. 6. In other words, the former needs a longer
`time than the latter until the voltage reaches a given
`level. This indicates that the operating speed of the
`C-MOS inverter I] can be adjusted by changing the
`voltage of V0. Accordingly, the electrical characteris-
`tics of the C—MOS inverter 11 can be changed by chang-
`ing the voltage of V0.
`Other circuit arrangements when a MOS type semi-
`conductor integrated circuit according to the present
`invention is applied to the C-MOS inverter 11 are shown
`in FIGS. 7 to 15.
`The FIG. 7 embodiment has a series circuit composed
`of a capacitor C2 and a P-channel MOS transistor Qp12,
`which is laid between the output node N1 and the
`power supply voltage VDD, while the FIG. 3 embodi-
`
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`

`7
`ment has a series circuit composed of the transistor
`Qn12 and the capacitor C1 and which13 laid between
`the node N1 and the power supply voltage V55. The
`inverted voltage V—o1s applied to the gate of the transis-
`tor Qp12.
`In the FIG 7 circuit, when the voltage V0 is high
`(VH) the transistor Qp1215 OFF. At this time, its equiv-
`alent circuit is as shown1n FIG. 5A or 5B The equiva-
`lent circuit shows that when the voltage V_o is high
`(V11),
`the capacitance Cs alone is ch__arged or dis-
`charged. Conversely, when the voltage V015 low (VL),
`the transistor Qp12 is ON and the node N1 is coupled
`with the capacitor C2 via the MOS transistor Q12, in
`addition to the capacitor Cs. Both the capacitors are
`also grounded When the output voltage Vout at node
`N1 falls, the capacitor Csis discharged and the capaci—
`tor C21s charged On the other hand when the voltage
`Vout rises, the capacitor Cs is charged and the capaci-
`tor C2 is discharged. In this embodiment, as in the FIG.
`3 embodiment, when the output voltage V0 is high
`(VH) and low (VL), the effective capacitance at node
`N1 differs. The changing time of the Loltage Vout
`under V_o=VL is larger than that under Vo=VH.
`The FIG. 8 embodiment results from combining the
`FIGS. 3 and 7 embodiments. As shown, a series circuit
`composed of the capacitor C1 and the N-channel MOS
`transistor Qn12 with the gate input of V0 is inserted
`between the output node N1 and the power supply
`voltage V55. Another series circuit composed of the
`capacitor C2 and the P-channel MOS transistor Qp12
`with a gate input of V015 inserted between the node N1
`and the power supply voltage VDD
`The FIG. 9 circuit is arranged similarly as in the FIG.
`3 embodiment where the capacitor C1 and the MOS-
`transistor Q12 are interchanged between the node N1
`and the power supply voltage V55. This embodiment
`also attains effects similar to those of the FIG. 3 em-
`bodiment.
`The FIG. 10 embodiment, serving as a delay circuit,
`is equivalent to the FIG. 3 embodiment additionally
`having a C-MOS inverter 12. As shown, the inverter 12,
`comprised of a P-channel MOS transistor Qp13 and an
`N-channel MOS transistor Qn13 coupled at their gates
`with the node N1. In more particular, the input terminal
`comprising the gates of these transistors is routed to the
`node N1. The output terminal of the inverter 12 as the
`conjunction of these transistors provides an output volt-
`age Vout. When receiving a rectangular input voltage
`Vin as shown in FIG. 11A, the delay circuit of FIG. 10
`exhibits different delay characteristics for Vo=VH and
`Vo=VL, as shown in FIG. 11B. The delay time at
`Vo=VH is longer than that at Vo=VL.
`The FIG. 12 embodiment circuit is equivalent to the
`FIG. 3 circuit modified such that a P-channel MOS
`transistor Qp14 with a gate input of V_o is coupled in
`parallel with an. N-channel MOS transistor Qn12. A
`distinctive characteristic of the FIG. 12 embodiment is
`tt'it a plurality of MOS transistors are parallel con—
`nected to a single capacitor C1. With such a construc-
`tion, the capacitor C1 is charged up to the power supply
`voltage VDD. Therefore, the effective capacitance at
`the output node N1 during a transient time is larger than
`that as in FIG. 3 circuit.
`The FIG. 13 embodiment has a series circuit com-
`posed of an N-channel MOS transistor Qn12 with a gate
`voltage of V0 as the input voltage, an N-channel MOS
`transistor Qn15 with a gate input of Vin2 as the input
`voltage, and two capacitors C3 and C4 coupled in paral-
`
`
`
`the drain of a depletion type (simply
`In FIG. 16,
`referred to as a D type) MOS transistor QD11 is con-
`nected to the power supply voltage VDD and its source
`
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`lel. This series circuit is interposed between the output
`node N1 of the inverter 11 and the power supply voltage
`V55. The parallel capacitor arrangement may be com-
`posed of more than two capacitors The FIG 13 em-
`bodiment operates as an inverter with a variable delay
`time according to the input voltage Vin2 when the
`potential V0 is set to a proper value.
`Another C-MOS inverter of the type as mentioned
`above is illustrated in FIG. 14A and its characteristics
`shown in FIG. 14B. This embodiment also has a series
`circuit including an N-channel MOS transistor in4
`with the voltage V0 for its gate input, another N—chan-
`nel MOS transistor in6 with the input voltage for its
`gate input, and a capacitor C1. This series circuit is
`inserted between the output node N1 and the power
`supply voltage V55. The present embodiment further
`includes a P-channel MOS transistor Qp15 with the
`input voltage Vin for the gate input. The transistor
`Qp15 is connected between the power supply voltage
`VDD and the conjunction node between the MOS tran—
`sistor Qn16 and the capacitor C1.
`the
`In the present embodiment, under Vo=VH,
`charging operation to the capacitor C1 when the volt-
`age Vout rises is performed through two current paths
`from the power supply voltage VDD: one composed of
`the transistor Qpll and the other composed of the tran-
`sistor Qp15. Therefore, the output voltage Vout when
`V0=VH,
`less sharply falls than, when Vo=VL, as
`shown in FIG. 14B. When the output voltage Vout
`falls, the capacitor C1 discharges through the current
`path including the MOS transistors inl, in4 and
`Qn16. The fall
`time of the output voltage Vout at
`Vo=VH is larger than that at Vo=VL, as shown in
`FIG. 14C. FIGS. 14B and 14C respectively show the
`fall characteristic curves at V0: VL and V0: VH
`An arrangement in which a delayIn the rise time of ~
`the voltage Vout15 adjusted by the inversed voltage V0,
`is illustratedin FIG. 15A. This arrangement has also a
`series circuit comprising a P-channel MOS transistor
`Qp14 with the voltage V5 for the gate input, a P-chan-
`‘ nel MOS transistor Qp16 with the input voltage Vin for
`the gate input, and a capacitor C2. This series circuit is
`inserted between the node N1 of the C-MOS inverter 11
`and the power supply voltage VDD. Further, an N-
`channel MOS transistor Qn15 receiving the input volt-
`age Vin at the gate is connected between the power
`supply voltage V55 and a junction node between the
`transistor Qp16 and the capacitor C2.
`In the present embodiment, when V—o= VL, the dis-
`charge from the capacitor is done nOt only through the
`current paths of the MOS transistors inl and in4
`but also through the current path of the transistor Qn15.
`At the fall of the output voltage Vout, the time delay
`when V5=VL is smaller than when V_o=VH. The
`charge to the capacitor C2 at the rise of the voltage
`Vout is done only through the current path including
`the transist9_r_Qp11. In this case, the time delay is larger
`than when Vo=VH (FIG. 15B). This rise characteristic
`is illustrated inFIG. 15C.
`Turning now to FIGS. 16 to 20, there are shown
`circuit arrangements when a MOS semiconductor inte-
`grated circuit according to the present
`invention is
`applied to an E/D inverter composed of a depletion
`type MOS transistor and an enhancement type MOS
`transistor.
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`9
`and gate to a node N2. The drain of an enhancement
`type MOS transistor Q1511 is connected to the node N2
`and its source to the power supply voltage V55. The
`input voltage is applied to the gate of the MOS transis-
`tor Q1311. Connected between the node N2 and the
`power supply voltage V55 is a series circuit made up of
`a capacitor C5 and an E type MOS transistor Q51 re
`ceiving the voltage Vo at the gate. Incidentaly, a stray
`capacitor Cs interposed between the node N2 and the
`power supply voltage V55 is equivalent to a capacitor
`parasitically attached to the node N2, as in the case of
`C-MOS inverters as mentioned above.
`Also in the FIG. 16 embodiment, the change time of
`the output voltage Vout when Vo=VH is larger than
`when Vo=VL, similar to the circuit of FIG. 3.
`The FIG. 17 embodiment is equivalent to the FIG. 16
`embodiment, which is modified such that the capacitor
`C5 and the MOS transistor Q1512 are interchanged with
`each other between the node N2 and the power supply
`voltage V55. The present embodiment can also attain
`the effects equivalent to those in the FIG. 16 circuit.
`An embodiment of the integrated circuit shown in
`FIG. 18 employs two series circuits each incl