`
`(19) [Issuing Country] Japan Patent Office (JP)
`(12) [Publication Name] Gazette of Unexamined Patent Applications (A)
`(11) [Publication Number] H08-018021
`(43) [Publication Date] January 19, 1996
`
`JP H08-018021 A
`
`
`
`
`
`
`
`(51) [Int.Cl.6]
`
`
`
`9199-5K
`
`M
`
`B
`
`[FI]
`
`
`
`H01L 27/118
`H03K 19/0948
`19/173
`H01L 21/82
`H03K 19/094
`[Examination Request] Not Yet Received
`[Number of Claims] 3
`[Application Format] Floppy Disk (FD)
`[Total Number of Pages] 8
`
`(21) [Application Number] H06-174730
`(22) [Filing Date] July 4, 1994
`(71) [Applicant]
`[Identification Number] 000004226
`[Name] Nippon Telegraph & Telephone Corporation
`[Address] 3-19-2, Nishishinjuku, Shinjuku-ku, Tokyo
`(72) [Inventor]
`[Name] Shin’ichiro MUTOH
`[Address] Nippon Telegraph & Telephone Corporation, 1-1-6, Uchisaiwai-cho, Chiyoda-ku,
`Tokyo
`(72) [Inventor]
`[Name] Yasuyuki MATSUYA
`[Address] Nippon Telegraph & Telephone Corporation, 1-1-6, Uchisaiwai-cho, Chiyoda-ku,
`Tokyo
`(72) [Inventor]
`[Name] Satoshi SHIGEMATSU
`[Address] Nippon Telegraph & Telephone Corporation, 1-1-6, Uchisaiwai-cho, Chiyoda-ku,
`Tokyo
`(74) [Agent]
`[Attorney]
`[Name] Tsuneaki NAGAO
`
`
`
`
`
`
`
`1
`
`AMD EX1013
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`
`
`JP H08-018021 A
`
`(54) [Title of the Invention]
`
`Gate Array-Type Integrated Circuit
`
`(57) [Abstract]
`
`[Purpose]
`
`To enable a MT-CMOS circuit to be realized using a gate array integrated circuit.
`
`[Constitution]
`
` A
`
` gate array is configured by arranging a second basic cell 3 composed of MOS transistors
`with a high threshold voltage adjacent to a first basic cell 2 composed of MOS transistors
`with a low threshold voltage.
`
`
`
`
`
`2
`
`0002
`
`

`

`JP H08-018021 A
`
`
`
`[Claims]
`
`[Claim 1]
`
` A
`
` gate array-type integrated circuit comprising a first basic cell composed of a field effect
`transistor and a second basic cell composed of a field effect transistor having an absolute
`value of the threshold voltage that is greater than that of the field effect transistor
`constituting the first basic cell, at least one cell array being formed using the first basic cell
`and another cell array being formed using the second basic cell, and the cell array
`composed of the second basic cell being arranged adjacent to the cell array composed of
`the first basic cell, at any end vertically or horizontally, at both ends horizontally, at both
`ends vertically, at all ends vertically and horizontally, or inside the first basic cell.
`
`[Claim 2]
`
` A
`
` gate array-type integrated circuit according to claim 1, wherein a group of logic circuits is
`formed in the first basic cell, and a power supply control circuit is formed in the second
`basic cell to control the supply of power to the group of logic circuits.
`
`[Claim 3]
`
` A
`
` gate array-type integrated circuit according to claim 1, wherein the integrated circuit
`comprises a group of logic circuits formed using transistors constituting the first basic cell
`and having a first and second power supply terminal, a first and/or second power supply
`control circuit formed using transistors constituting the second basic cell for controlling the
`supply of power to the group of logic circuits, first and second actual power supply lines
`constituting the power supply source to the group of logic circuits, and a first and/or second
`pseudo-power supply line, the first actual pseudo power supply line being connected to the
`first power supply terminal of the group of logic circuits, the first power supply control
`circuit being connected between the first pseudo power supply line and the first actual
`power supply line, and a second power supply line being connected directly to the second
`power supply terminal of the group of logic circuits, or a second power supply control circuit
`being connected to the second pseudo power supply line and between the second pseudo
`power supply line and the second actual power supply line.
`
`[Detailed Description of the Invention]
`
`[0001]
`
`[Technical Field of the Invention]
`
`The present invention relates to a semiconductor integrated circuit configured in gate array
`style and, more specifically, to a gate array-type integrated circuit compatible with CMOS
`circuits for low-voltage/high-speed operation composed of a transistor with a high threshold
`voltage and a transistor with a low threshold voltage.
`
`[0002]
`
`[Prior Art]
`
` A
`
` gate array-type semiconductor integrated circuit realizes the desired circuit function by
`arranging a plurality of basic cells made of a plurality of transistor elements in matrix
`
`
`
`3
`
`0003
`
`

`

`
`
`JP H08-018021 A
`
`fashion on a semiconductor wafer and wiring the basic cells together. In this way, an
`integrated circuit can be obtained in a short period of time.
`
`[0003]
`
`FIG. 10 is a schematic diagram of an LSI chip with a gate array in the prior art (Reference
`Document: “ULSI Design Technology,” Takuo OGINO, supervisor, The Institute of
`Electronics, Information and Communication Engineers). Basic cells 12 are arranged in
`matrix fashion in the central portion of the LSI chip 11 to form a cell array 12A.
`Input/output cell arrays 13 are arranged on the outer periphery to form an interface with
`outside components.
`
`[0004]
`
`FIG. 11 is a diagram used to explain a CMOS gate array-type basic cell 12 used in the prior
`art. Q11 and Q12 are P channel-type MOS field effect transistors (referred to simply as MOS
`transistors below), Q13 and Q14 are N channel-type MOS transistors, and both are used as
`transistors forming logic gates.
`
`[0005]
`
`In order to explain an example in which transistors are formed on a P type substrate, P
`channel MOS transistors Q11 and Q12 are formed in n well 121. Here, 122 is a p+ region
`functioning as a source or drain for a P channel MOS transistor, 123 is an n+ region
`functioning as a source or drain for an N channel MOS transistor, and 124 is a gate
`electrode.
`
`[0006]
`
`Although the transistors Q11 and Q12 may vary in size, the threshold voltages are set to
`the same value because it has a significant effect on device characteristics. The same
`applies to transistors Q13 and Q14.
`
`[0007]
`
`FIG. 12 shows a connection example realizing a two-input NAND gate, and FIG. 13 shows
`the equivalent circuit in this example. The black circles in FIG. 12 indicate the contact
`positions for a source, drain, or gate electrode in a MOS transistor. Also, A1 and A2 are
`input terminals, Y is an output terminal, VDD is a high potential actual power supply line,
`and VSS is a low potential actual power supply line.
`
`[0008]
`
`In order to meet demand for portable electronic devices, progress has been made in recent
`years on low-voltage operation of semiconductor integrated circuits. An example of this
`technology is the multi-threshold CMOS (MT-CMOS) circuit described in the Spring 1994
`Conference Proceedings of the Institute of Electronics, Information and Communication
`Engineers, Vol. 5, pp. 5-195 shown in FIG. 14.
`
`[0009]
`
`In FIG. 14, the transistors Q21 to Q24 constituting the logic circuit (two-input NAND gate)
`14 are low threshold voltage transistors. The power supply terminal on the high potential
`
`
`
`4
`
`0004
`
`

`

`
`
`JP H08-018021 A
`
`side of the logic circuit 14 is connected to a high potential pseudo power supply line VDDV,
`and the power supply terminal on the low potential side is connected to a low potential
`actual power supply line VSS. A MOS transistor for controlling the high threshold voltage
`power QH11 is connected between the high potential pseudo power supply line VDDV and
`the high potential actual power supply line VDD. A sleep signal SL for the power control is
`inputted to the gate of MOS transistor QH11.
`
`[0010]
`
`During operation, the sleep signal SL is set to a low potential. As a result, the PMOS
`transistor QH11 becomes conductive, and the high potential pseudo power supply line VDDV
`can be regarded as a high potential actual power supply line VDD. At this time, because the
`logic circuit 14 connected to the high potential pseudo power supply line VDDV is composed
`of MOS transistors Q21 to Q24 with low threshold voltage, it operates at high speed even at
`an extremely low voltage of 1 V or less.
`
`[0011]
`
`In general, a MOS transistor experiences a problem in which leakage current blocking
`capacity is reduced when the absolute value of the threshold voltage is lowered and the
`current is increased during standby (during cutoff). In MT-CMOS circuit technology, a power
`control function known as sleep control is introduced to avoid this problem. In other words,
`the circuit is put to sleep when the circuit is not in operation. Specifically, the sleep signal
`SL is set to a high potential, and the P channel MOS transistor QH11 is cut off. Because the
`cut off high threshold voltage P channel MOS transistor QH11 is interposed between the
`high potential actual power supply line VDD and the low potential actual power supply line
`VSS, the standby leakage current that occurs in low threshold voltage MOS transistors Q21
`to Q24 can be cut off and ultra-low power characteristics can be realized.
`
`[0012]
`
`As a result, MT-CMOS circuit technology shows promise as a low-voltage/high-speed circuit
`technology. However, transistors with a high threshold voltage and transistors with a low
`threshold voltage have to be combined on a single LSI chip in order to realize this circuit in
`an actual LSI.
`
`[0013]
`
`[Problem to be Solved by the Invention]
`
`However, in the conventional gate array used widely in simple LSI implementation methods,
`both P channel MOS transistors and N channel MOS transistors are simply arrayed and
`configured in basic cells consisting of MOS transistors, each having a single threshold
`voltage.
`
`[0014]
`
`It is an object of the present invention to enable the MT-CMOS circuit technology using field
`effect transistors with different threshold voltages to be realized using a gate array
`integrated circuit.
`
`[0015]
`
`
`
`
`5
`
`0005
`
`

`

`
`
`JP H08-018021 A
`
`[Means for Solving the Problem]
`
`In order to achieve this object, the present invention is a gate array-type integrated circuit
`comprising a first basic cell composed of a field effect transistor and a second basic cell
`composed of a field effect transistor having an absolute value of the threshold voltage that
`is greater than that of the field effect transistor constituting the first basic cell, at least one
`cell array being formed using the first basic cell and another cell array being formed using
`the second basic cell, and the cell array composed of the second basic cell being arranged
`adjacent to the cell array composed of the first basic cell, at any end vertically or
`horizontally, at both ends horizontally, at both ends vertically, at all ends vertically and
`horizontally, or inside the first basic cell.
`
`[0016]
`
`In the present invention, preferably a group of logic circuits is formed in the first basic cell,
`and a power supply control circuit is formed in the second basic cell to control the supply of
`power to the group of logic circuits.
`
`[0017]
`
`In the present invention, preferably the integrated circuit comprises a group of logic circuits
`formed using transistors constituting the first basic cell and having a first and second power
`supply terminal, a first and/or second power supply control circuit formed using transistors
`constituting the second basic cell for controlling the supply of power to the group of logic
`circuits, first and second actual power supply lines constituting the power supply source to
`the group of logic circuits, and a first and/or second pseudo-power supply line, the first
`actual pseudo power supply line being connected to the first power supply terminal of the
`group of logic circuits, the first power supply control circuit being connected between the
`first pseudo power supply line and the first actual power supply line, and a second power
`supply line being connected directly to the second power supply terminal of the group of
`logic circuits, or a second power supply control circuit being connected to the second pseudo
`power supply line and between the second pseudo power supply line and the second actual
`power supply line.
`
`[0018]
`
`[Operation]
`
`The present invention can realize a MT-CMOS circuit using high threshold voltage transistors
`and low threshold voltage transistors without reducing cell utilization in a gate cell array by
`arranging a cell array composed of a second basic cell having a field effect transistor with a
`high threshold voltage adjacent to a cell array composed of a first basic cell having a field
`effect transistor with a low threshold voltage.
`
`[0019]
`
`[Examples]
`
`The following is a description of examples of the present invention. FIG. 1 is a schematic
`diagram of an LSI chip 1 with the gate array integrated circuit in the first example. Here, 2
`denotes a first basic cell composed of low threshold voltage MOS transistors, and 3 denotes
`a second basic cell composed of high threshold voltage MOS transistors. The first basic cells
`2 are arranged in a matrix fashion to form cell arrays 2A, 2B, and 2C. In each of cell arrays
`
`
`
`6
`
`0006
`
`

`

`
`
`JP H08-018021 A
`
`2A, 2B, and 2C, cell columns (cell arrays) 3A, 3B, 3C, 3D consisting of second basic cells 3
`are arranged adjacent to each other. Input/output cell arrays 4 are arranged on the outer
`periphery to form an interface with outside components.
`
`[0020]
`
`FIG. 2 is a diagram showing the first basic cell 2. Q1 and Q2 are P channel-type MOS
`transistors, Q3 and Q4 are N channel-type MOS transistors, and both threshold voltages are
`at low level. For example, PMOS transistors Q1 and Q2 may be set to about -0.2 V, and
`NMOS transistors Q3 and Q4 may be set to about 0.2 V.
`
`[0021]
`
`In order to explain an example in which transistors are formed on a P type substrate, P
`channel MOS transistors Q1 and Q2 are formed in n well 201. Here, 202 is a p+ region
`functioning as a source or drain for a P channel MOS transistor, 203 is an n+ region
`functioning as a source or drain for an N channel MOS transistor, and 204 is a gate
`electrode.
`
`[0022]
`
`FIG. 3 is a diagram showing the second basic cell 3. QH1 and QH2 are P channel MOS
`transistors, and the threshold voltages are at a high level, set, for example, to about -0.7 V.
`
`[0023]
`
`In order to explain an example in which transistors are formed on a P type substrate, P
`channel MOS transistors QH1 and QH2 are formed in n well 301. Here, 302 is a p+ region
`functioning as a source or drain for a P channel MOS transistor, and 303 is a gate electrode.
`
`[0024]
`
`By forming low threshold voltage transistor portions and high threshold voltage transistor
`portions on a single LSI chip 1, a gate array-type integrated circuit can be realized that is
`compatible with MT-CMOS circuit technology using high threshold voltage transistors and
`low threshold voltage transistors.
`
`[0025]
`
`FIG. 4 shows a connection example in portion A surrounded by a circle in FIG. 1. Here, the
`first basic cells 2 are used to create NAND gates and form an MT-CMOS circuit. In FIG. 4,
`A1' and A2' are input terminals to a first logic circuit (NAND gate), Y 'is an output terminal,
`A1 and A2 are input terminals to a second logic circuit (NAND gate), Y is an output terminal.
`Q1', Q2', Q1, and Q2 are P-channel MOS transistors in a first basic cell 2, Q3', Q4', Q3, and
`Q4 are N-channel MOS transistors in a first basic cell 2, and these transistors have a low
`threshold voltage. QH1 and QH2 are P channel MOS transistors in a second basic cell 3, and
`these transistors have a high threshold voltage. Black circles indicate contact positions to a
`source, drain, or gate electrode. The thick solid lines indicate first layer wiring. Here, 5
`denotes second layer wiring (indicated by dotted lines) for the high potential actual power
`supply line VDD, and 6 denotes a through-hole between second layer wiring 5 and first layer
`wiring.
`
`[0026]
`
`
`
`7
`
`0007
`
`

`

`
`
`JP H08-018021 A
`
`
`FIG. 5 is a circuit diagram of the equivalent circuit in the configuration shown in FIG. 6. The
`first and second logic circuits 7, 7' configured using the first basic cell 2 are connected
`between the high potential pseudo power supply line VDDV and the low potential actual
`power supply line VSS, and the power supply control circuit 8 configured using the second
`basic cell 3 is connected between the high potential pseudo power supply line VDDV and the
`high potential actual power supply line VDD. Here, the power supply control circuit 8 is a
`transfer gate created by connecting P channel MOS transistors QH1 and QH2 in parallel, and
`conduction/cutoff of the gate is controlled by a sleep signal SL. When the sleep signal SL is
`at low potential, the gate is rendered conductive and power is supplied. When it is at high
`potential, the gate is cut off and the supply of power is stopped. As described above, the
`portions of the first and second logic circuits 7 and 7′ are composed of the first basic cell 2,
`and a portion of the power supply control circuit 8 is composed of the second basic cell 3.
`
`[0027]
`
`FIG. 6 is a circuit diagram of the LSI chip 1 in the second example. In this example, a single
`cell array 2D composed of the first basic cell 2 is arranged in the center, and cell columns
`(cell arrays) 3A, 3D composed of the second basic cell 3 are provided on the left and right
`ends. The rest of the configuration is identical to that of the first example.
`
`[0028]
`
`FIG. 7 is a circuit diagram of the LSI chip 1 in the third example. In this example, a single
`cell array 2E composed of the first basic cell 2 is arranged in the center as in FIG. 6, and
`two cell columns (cell arrays) 3E, 3F composed of the second basic cell 3 are provided at on
`the left and right ends. The rest of the configuration is identical to that of the first example.
`The number of cell columns 3E, 3F may be three or more.
`
`[0029]
`
`In this example, higher threshold voltage transistors can be used. Specifically, in the circuit
`shown in FIG. 5, the size of the transistors can be effectively increased because three or
`more P-channel transistors QH1 and QH2 of high threshold voltage can be connected in
`parallel. If the size of the high threshold voltage transistors QH1 and QH2 is increased in
`this way, the ability to supply current to the high potential pseudo power supply line VDDV
`is improved, enabling higher speed operation of the MT-CMOS circuit.
`
`[0030]
`
`FIG. 8 is a circuit diagram of the LSI chip 1 in the fourth example. Here, the cell columns
`(cell arrays) 3G and 3H composed of second basic cell 3 comprising high threshold voltage
`transistors are arranged adjacent to the upper and lower end portions of a cell array 2F
`composed of the first basic cell 2.
`
`[0031]
`
`FIG. 9 is an equivalent circuit diagram of portion B surrounded by a circle in FIG. 8. A MT-
`CMOS circuit can be configured even when a cell row 3G composed of the second basic cell
`3 is arranged adjacent to the upper portion of a cell array 2F composed of the first basic cell
`2 as shown in FIG. 9. The same is true when arranged adjacent to the lower portion.
`Although not depicted, the second basic cells 3 can be arranged adjacent to the center
`portion as well as the end portions.
`
`
`
`8
`
`0008
`
`

`

`
`
`JP H08-018021 A
`
`
`[0032]
`
`In the embodiments described above, the second basic cells 3 are composed of P channel
`MOS transistors. However, they may also be used to constitute N channel MOS transistors
`with a high threshold voltage. In this case, a low potential pseudo power supply is provided
`instead of the high potential pseudo power supply line VDDV, the power supply terminal on
`the high potential side of the group of logic circuits composed of transistors of the first basic
`cell 2 is connected to the high potential actual power supply line VDD, the power supply
`terminal on the low potential side is connected to the low potential pseudo power supply
`line, and a power supply control circuit comprising N channel MOS transistors with a high
`threshold voltage constituting the second basic cells is connected between the low potential
`pseudo power supply line and the low potential actual power supply line VSS. A signal
`obtained by inverting the sleep signal SL mentioned above is then applied to the gate of the
`N channel MOS transistor in the power supply control circuit.
`
`[0033]
`
`The second basic cell 3 can be configured as a mixture of a high threshold voltage P-channel
`MOS transistors and high threshold voltage N-channel MOS transistors (a configuration
`similar to the first basic cell 2). In this case, a high potential pseudo power supply line
`VDDV and a low potential pseudo power supply are provided, the power supply terminal on
`the high potential side of the group of logic circuits composed of transistors of the first basic
`cell 2 is connected to the high potential pseudo power supply line VDDV, the power supply
`terminal on the low potential side is connected to the low potential side pseudo power
`supply line, a power control circuit composed of high threshold voltage P channel MOS
`transistors in the second basic cells is connected between the high potential real power
`supply line VDD and the high potential pseudo power supply line VDDV, and a power supply
`control circuit consisting composed of high threshold voltage N channel MOS transistors in
`the second basic cells is connected between the low potential actual power supply line VSS
`and the low potential pseudo power supply line. The sleep signal SL is applied to the gate of
`the P channel MOS transistor of the power supply control circuit composed of a P channel
`MOS transistor, and an inverted sleep signal SL is applied to the gate of the N channel MOS
`transistor of the power supply control circuit composed of an N channel MOS transistor.
`
`[0034]
`
`The power supply control circuit is a transfer gate-type circuit in the embodiments.
`However, the present invention is not limited to this type of circuit. The power supply
`control circuit can be any conceivable circuit type in existing circuit design methods.
`
`[0035]
`
`[Effects of the Invention]
`
`In the present invention, a cell array composed of second basic cells having high threshold
`voltage field effect transistors is arranged adjacent to a cell array composed of first basic
`cells having low threshold voltage field effect transistors. As a result, a MT-CMOS circuit
`using high threshold voltage transistors and low threshold voltage transistors can be
`realized on a single LSI chip without reducing the cell utilization rate.
`
`[0036]
`
`
`
`
`9
`
`0009
`
`

`

`
`
`JP H08-018021 A
`
`This MT-CMOS circuit can be realized using the first basic cell in a group of logic circuits and
`the second basic cell in a power supply control circuit.
`
`[Brief Description of the Drawings]
`
`[FIG. 1]
`
`FIG. 1 is a schematic diagram of an LSI chip with the gate array in the first example of the
`present invention.
`
`[FIG. 2]
`
`FIG. 2 is a diagram used to explain the first basic cell in the first example.
`
`[FIG. 3]
`
`FIG. 3 is a diagram used to explain the second basic cell in the first example.
`
`[FIG. 4]
`
`FIG. 4 is a diagram used to explain the cells in the connection example shown in portion A
`of FIG. 1.
`
`[FIG. 5]
`
`FIG. 5 is a circuit diagram of the equivalent circuit for the cell shown in FIG. 4.
`
`[FIG. 6]
`
`FIG. 6 is a circuit diagram of the LSI chip with the gate array in the second example.
`
`[FIG. 7]
`
`FIG. 7 is a circuit diagram of the LSI chip with the gate array in the third example.
`
`[FIG. 8]
`
`FIG. 8 is a circuit diagram of the LSI chip with the gate array in the fourth example.
`
`[FIG. 9]
`
`FIG. 9 is a circuit diagram of the equivalent circuit in portion B of FIG. 8.
`
`[FIG. 10]
`
`FIG. 10 is a schematic diagram of an LSI chip with a gate array in the prior art.
`
`[FIG. 11]
`
`FIG. 11 is a diagram used to explain the basic cell in FIG. 10.
`
`[FIG. 12]
`
`
`
`
`10
`
`0010
`
`

`

`
`
`JP H08-018021 A
`
`FIG. 12 is a diagram used to explain a connection example for a two-input NAND gate using
`the basic cell in FIG. 11.
`
`[FIG. 13]
`
`FIG. 13 is a circuit diagram of the equivalent circuit in FIG. 12.
`
`[FIG. 14]
`
`FIG. 14 is a circuit diagram of the MT-CMOS circuit technology.
`
`[Key to the Drawings]
`
`1: LSI chip
`2: 1st basic cell
`2A, 2B, 2C, 2D, 2E, 2F: Cell arrays
`201: n well
`202: p+ region
`203: n+ region
`204: Gate electrode
`3: 2nd basic cell
`3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H: Cell arrays
`301: n well
`302: p+ region
`303: Gate electrode
`4: Cell array for input-output buffer
`5: 2nd layer wiring
`6: Through-hole
`7, 7′: Logic circuit
`8: Power supply control circuit
`11: LSI chip
`12: Basic cell
`121: n well
`122: p+ region
`123: n+ region
`124: Gate electrode
`12A: Cell array
`13: Cell array for input-output buffer
`14: Logic circuit
`Q1-Q4, Q1′-Q4′, Q11-Q14, Q21-Q24: MOS transistors with low threshold voltage
`QH1, QH2, QH11: MOS transistors with high threshold P channel
`VDD: High potential actual power supply line
`VDDV: High potential pseudo power supply line
`VSS: Low potential actual power supply line
`
`
`
`
`
`
`
`11
`
`0011
`
`

`

`
`
`[FIG. 1]
`[FIG. 1]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
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`JP HOS-018021 A
`JP H08-018021 A
`
`
`
`[FIG. 2]
`[FIG. 2]
`
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`
`
`
`
`204
`
`
`
`
`
`13
`13
`
`0013
`
`0013
`
`

`

`
`
`[FIG. 3]
`[FIG. 3]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`301 _,
`
`
`
`
`
`14
`14
`
`0014
`
`HD.
`
`
`
`
`
`
`0014
`
`

`

`
`
`[FIG. 4]
`[FIG. 4]
`
`
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`.JuwW/IIV.
`
`w
`1...?
`5.6%?!“
`.,
`
`1rA
`
`A
`
`'IA
`
`Q4
`
`A2
`
`SL VDD SL
`
`
`
`
`
`15
`15
`
`0015
`
`
`
`
`
`
`0015
`
`

`

`JP HOS-018021 A
`JP H08-018021 A
`
`
`
`[FIG. 5]
`[FIG. 5]
`
`
`20
`—m_—A___—-_————-—l
`
`3 D
`
`V D D
`
`S L
`
`m7.31;?fiéfiéfi'fififfim"Tm—1;?EEEEEEEFEKIGEH 3 _ F __
`
`m!
`
`
`
`
`
`
`
`
`
`
`
`
`16
`16
`
`0016
`
`0016
`
`

`

`
`
`[FIG. 6]
`[FIG. 6]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`.f}?
`
`in?
`
`
`
`
`
`
`
`
`
`
`17
`17
`
`0017
`
`0017
`
`

`

`
`
`[FIG. 7]
`[FIG. 7]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`i.
`
`J.
`
`airI
`
`I2...}
`fiffifl?
`I...47.....-...ra.I
`
`41.2.5.3...
`fifim%wflfl.x
`gnu-(1....
`
`
`
`
`
`
`
`
`
`
`18
`18
`
`0018
`
`0018
`
`

`

`
`
`[FIG. 8]
`[FIG. 8]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`./._rW?
`
`
`
`
`
`
`
`
`
`
`19
`19
`
`0019
`
`0019
`
`

`

`JP HOS-018021 A
`JP H08-018021 A
`
`
`
`[FIG. 9]
`[FIG. 9]
`
`
`Power Supply Cuntrcl Circuit
`
`VDD I
`
`i
`
`!
`
`[VDD
`
`
`
`
`
`
`
`
`chic Circuit
`
`
`
`
`
`20
`20
`
`0020
`
`0020
`
`

`

`
`
`[FIG. 10]
`[FIG. 10]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`1
`
`
`
`
`
`
`
`
`1 2
`
`
`
`002 1
`
`1
`21
`
`0021
`
`

`

`
`
`[FIG. 11]
`[FIG. 11]
`
`
`12
`
`JP HOS-018021 A
`JP H08-018021 A
`
`011‘
`
`013”“—
`
`
`
`
`
`
`
`
`
`22
`22
`
`0022
`
`0022
`
`

`

`JP HOS-018021 A
`JP H08-018021 A
`
`
`
`[FIG. 12]
`[FIG. 12]
`
`
`
`
`
`
`
`
`
`
`
`
`
`23
`23
`
`0023
`
`0023
`
`

`

`JP HOS-018021 A
`JP H08-018021 A
`
`V00
`
`
`
`[FIG. 13]
`[FIG. 13]
`
`
`
`
`
`
`
`
`
`V83
`
`
`
`
`
`24
`24
`
`0024
`
`0024
`
`

`

`
`
`[FIG. 14]
`[FIG. 14]
`
`
`JP HOS-018021 A
`JP H08-018021 A
`
`L_S
`
`HG
`
`VDDV
`
`
`
`
`
`
`
`25
`25
`
`0025
`
`0025
`
`