United States Patent [19]
`Douseki et al.
`
`111111111111111111111111111111111111111111111111111111111111111111111111111
`US005486774A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,486,774
`Jan.23, 1996
`
`[54] CMOS LOGIC CIRCUITS HAVING LOW
`AND IDGH-THRESHOLD VOLTAGE
`TRANSISTORS
`
`[75}
`
`Inventors: Takakuni Douseki; Junzo Yamada;
`Yasuyuki Matsuya; Shinichirou
`Mutou, all of Kanagawa, Japan
`
`[731 Assignee: Nippon Telegraph and Telephone
`Corporation, Tokyo, Japan
`
`[21} Appl. No.: 333,235
`
`[22}
`
`Filed:
`
`Nov. 2, 1994
`
`Related U.S. Application Data
`
`[63]
`
`[30]
`
`Continuation of Ser. No. 981,183, Nov. 24, 1992, aban(cid:173)
`doned.
`Foreign Application Priority Data
`
`5,151,621
`5,164,621
`5,180,938
`5,187,386
`5,200,921
`5,223,751
`
`911992 Gato ........................................ 307/443
`11/1992 Miyamoto ............................ 307/296.8
`1/1993 Sin .......................................... 307/443
`211993 Chang et al ......................... 307/296.8
`411993 Okajirna .................................. 307/451
`611993 Simmon et al ......................... 307/451
`
`FOREIGN PATENT DOCUMENTS
`
`62-194635
`62-194634
`62-194636
`
`811981
`811987
`811987
`
`Japan .
`Japan .
`Japan .
`
`OTHER PUBLICATIONS
`
`Chen, John Y.; CMOS Devices and Technology For VLSI;
`©1990 by Prentice Hall, Inc.; p. 98.
`Clocked CMOS Calculator Circuitry by Y. Suzuki et al.,
`IEEE Journal of Solid-State Circuits, vol. SC-8, No. 6, Dec.
`1973; pp. 462-469.
`Zipper CMOS by C. M. Lee et al., IEEE Ciruits and Devices
`Magazines May 1986; pp. 10-16.
`
`Nov. 26, 1991
`Dec. 6, 1991
`Dec. 9, 1991
`Feb. 3, 1992
`
`[JP]
`[JP]
`[JP]
`[JP]
`
`Japan .................................... 3-311007
`Japan .................................... 3-323382
`Japan .................................... 3-324512
`Japan .................................... 4-017537
`
`Primary Examiner-Edward P. Westin
`Assistant Examiner-Benjamin D. Driscoll
`Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor & Zaf(cid:173)
`man
`
`[51]
`[52]
`[58]
`
`[56]
`
`Int. Cl.6
`................................................ H03K 19/0948
`U.S. CI •................................ 326/33; 326/81; 327/541
`Field of Search ..................................... 307/443, 451,
`307/475, 473, 296.8; 326133, 81, 58; 327/541
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,103,188
`4,320,509
`4,435,658
`4,473,762
`4,714,840
`4,791,323
`4,956,691
`4,999,529
`
`711978 Morton .................................... 307/451
`311982 Davidson et al ......................... 371125
`311984 Murray et al ........................... 307/450
`911984 Iwahashi et al ........................ 307/443
`1211987 Proebsting .............................. 307/443
`1211988 Austin ..................................... 307/443
`911990 Culley et al ............................ 307/475
`311991 Morgan, Jr. et al .................... 307/475
`
`[57]
`
`ABSTRACT
`
`A logic circuit includes a low-threshold logic circuit, a pair
`of first and second power lines, a first dummy power line,
`and a first high-frequency logic circuit. The low-threshold
`logic circuit has a logic circuit element constituted by a
`plurality of low-threshold field effect transistors. The pair of
`first and second power lines supply power to the low(cid:173)
`threshold logic circuit. The first dummy power line is
`connected to one of power source terminals of the low(cid:173)
`threshold logic circuit. The first high-threshold control tran(cid:173)
`sistor is arranged between the first dummy power line and
`the first power line.
`
`11 Claims, 9 Drawing Sheets
`
`Pll
`
`CSB
`
`QL1
`
`INV2
`
`I OL2
`
`cs
`PL2
`
`CKB
`
`CK
`
`:oUTPUT
`I
`I
`I
`I
`I
`1----1-----11--' I
`I
`I
`I
`--"
`
`INVS
`HIGH-THRESHOLD
`LOGIC CIRCUIT 30...-r'~-------------
`
`AMD EX1010
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`(""")
`
`0 :z
`--t
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`0 r
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`
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`
`CSB
`au
`_
`LOW-THRESHOLD
`Y LOGIC CIRCUIT 20
`
`r------------
`
`CK
`
`CKB
`
`CK
`
`INV2
`
`I OL2
`
`cs
`PL2
`
`LC2
`
`I NV5
`H I GH-THRESHOLD
`LOGIC CIRCUIT 30__.,ri._ ____________ _
`
`Lj
`•
`00. •
`
`------,
`
`I
`I
`I
`I
`I
`I
`I
`I
`,OUTPUT
`I
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`I
`I
`I
`- - . J
`
`Tss
`
`FIG. I
`
`0002
`
`

`

`U.S. Patent
`
`Jan. 23, 1996
`
`Sheet 2 of 9
`
`5,486,774
`
`C)
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`

`

`U.S. Patent
`
`Jan. 23, 1996
`
`Sheet 3 of 9
`
`5,486,774
`
`Voo
`
`C1__,..
`
`N2
`
`LOW-Vth LOGIC
`CIRCUIT
`
`20
`
`N1
`
`C2--------
`
`PL1
`
`OL1
`
`OL2
`
`PL2
`
`F I G.4
`
`------~~----------~----~-----
`INV4
`
`INV5
`
`CKB
`
`CK
`
`--------~----------~----4------
`
`F I G.S
`
`0004
`
`

`

`Voo
`
`Pll
`
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`
`au
`LOW-THRESHOLD
`~LOGIC CIRCUIT 20
`
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`~
`~
`
`~ = ~
`
`r------------
`
`1
`I
`I
`
`LC2
`
`INVS
`HIGH-THRESHOLD
`LOGIC CIRCUIT 30___/1 .... ____________ _
`
`: OUTPUT
`I
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`I
`I
`I
`I
`__..J
`
`CKB
`
`CK
`
`INV2
`
`OL2
`
`PL2
`
`F I G.6
`
`r--------
`l INV1
` ;--- __}- T21
`1
`I
`I I
`I
`CK---1.~
`I
`
`II
`
`10
`
`0005
`
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`1LOW-Vth
`NANDl
`I
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`12
`
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`:
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`TO OL2
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`jVth
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`
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`Vth
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`
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`
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`
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`
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`
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`
`Wll
`
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`LOW-
`Vth
`
`WLn
`
`BIT LINE PAIR
`BL1 BLm
`
`BLm
`
`WORD LINE
`
`HIGH-Vth
`MEMORY
`CELL(l, 1 )
`
`HIGH-Vth
`MEMORY
`CELL(n, 1)
`
`HIGH-Vth
`MEMORY
`CELL( 1, m)
`
`HIGH-Vth
`MEMORY
`CELL(n, m)
`
`MUX
`(MULTIPLEXER)
`
`WRITE SIGNAL
`HIGH-Vth MEMORY ARRAY 70
`
`"V"
`
`\....
`
`PL2
`
`DO
`
`DQ
`
`./
`
`GND
`
`SELECTOR LOGIC CIRCUIT 60
`
`F I G.7
`
`READ CIRCUIT 80
`
`0006
`
`

`

`U.S. Patent
`
`Jan. 23, 1996
`
`Sheet 6 of 9
`
`5,486,774
`
`- - - - - - - - -+ - - - - - - - - -Voo
`BL
`BL
`r---------- ----------,
`
`WL-+-+---~----~-------.--+----+--
`
`I
`I
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`~---------- ----------~
`-----~~--------1---GND
`
`B IT Ll NE PA I R
`
`PL 1
`
`CSB o---1 ~ Ts1
`N2
`
`INVSO
`--------
`
`----
`
`Nt
`
`cs o---1
`
`Vdd
`
`QL1
`
`QL2
`
`PL2
`
`F I G.8
`
`100
`
`LOGIC
`CIRCUIT
`BLOCK
`
`F I G.9
`
`0007
`
`

`

`STANDARD CELL SL1
`
`STANDARD CELL SLn
`
`STANDARD CELL SL<n+l)
`
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`
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`
`CONTROL CIRCUIT BLOCK 110
`
`D DIFFUSION LAYER
`-·-WIRING LAYER
`
`124
`
`-··-POLY-GATE
`
`X
`
`CONTACT
`f:X\
`SUBSTRATE POTENTIAL
`\CJ FIXING
`r--l THRESHOLD CONTROL
`L_ _ _: MASK
`
`F I G.IO
`
`0008
`
`

`

`U.S. Patent
`
`Jan. 23, 1996
`
`Sheet 8 of 9
`
`5,486,774
`
`100 r-------------~
`
`:::..::::
`c...,
`C>
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`
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`
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`1 0
`100
`1000
`
`NUMBER OF STANDARD CELLS
`
`F I G.ll
`
`0009
`
`

`

`U.S. Patent
`
`Jan. 23, 1996
`
`Sheet 9 of 9
`
`5,486,774
`
`,--·-·-·-·
`
`CSB~ -M1 ~
`CSB
`I
`
`INV1
`
`NAND1
`
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`
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`
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`
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`
`F I G.l2
`PRIOR ART
`
`0010
`
`

`

`5,486,774
`
`1
`CM OS LOGIC CIRCUITS HAVING LOW
`AND IDGH-THRESHOLD VOLTAGE
`TRANSISTORS
`
`This is a continuation of application Ser. No. 07/981,183 5
`filed Nov. 24, 1992, now abandoned.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`2
`FIG. 3 is a graph showing maximum toggle frequencies as
`a function of power supply voltages in the conventional
`example and the logic circuit of the embodiment shown in
`FIG. 1;
`FIG. 4 is a system diagram showing a modification of the
`present invention;
`FIG. 5 is a system diagram showing another modification
`BACKGROUND OF THE INVENTION
`of the present invention;
`The present invention relates to a logic circuit and, more 10
`FIG. 6 is a system diagram showing another embodiment
`particularly, to a logic circuit used in a latch circuit operative
`of the present invention;
`FIG. 7 is a system diagram showing still another embodi-
`at a low power supply voltage of 1 v or less.
`ment of the present invention;
`A conventional logic circuit of this type is generally
`FIG. 8 is a circuit diagram showing a detailed arrange-
`constituted by a CMOS logic block circuit, and an example
`is shown in FIG. 12. In this example, logic elements such as 15 ment of memory cells shown in FIG. 7;
`an inverter INV1, NAND gates NAND1, · · · ' and an
`FIG. 9 is a system diagram showing still another embodi-
`inverter INV2 are connected to power lines V DD and V ss
`ment of the present invention;
`through switching transistors M1, M2, . . . , M3 and
`switching transistors M4, MS, ... , M6. With this arrange-
`FIG. 10 is a view showing still another embodiment in
`ment, a control signal CSB of high level and a control signal 20 which the arrangement in FIG. 9 is applied to an actual
`CS oflow level are supplied to the switching transistors M1,
`memory cell structure;
`M2, ... , M3 and the switching transistors M4, MS, ... , M6,
`FIG. 11 is a graph showing the areas of logic circuit
`respectively, to control the operations of the respective logic
`blocks as a function of the numbers of standard cells in the
`elements.
`conventional example and the embodiment shown in FIG.
`Since the switching transistors used in this arrangement, 25 10; and
`however, are arranged as transistors having a single thresh-
`FIG. 12 is a system diagram showing a conventional logic
`old voltage, the following problems are posed.
`circuit.
`For example, assume an operation using a dry cell. When
`the power supply voltage of this logic circuit is decreased
`from 5 V (conventional case) to 1 V, the threshold voltage of 30
`each transistor comes close to the power supply voltage in
`an ON state (CS=illGH and CSB=LOW), and the transcon(cid:173)
`ductance of each transistor becomes extremely small to
`undesirably prolong the delay time of each logic circuit
`element. When the threshold voltage of each transistor 35
`constituting the logic circuit is decreased, a leakage current
`is increased in an OFF state (CS=LOW and CSB=illGH),
`and the endurance of the dry cell is greatly shortened. In
`addition, the control transistors are rendered nonconductive,
`and therefore storage information is destroyed.
`
`FIG. 1 shows a logic circuit according to an embodiment
`of the present invention. More specifically, FIG. 1 shows the
`arrangement of a low-threshold logic circuit for receiving a
`clock signal CK and generating the clock signal CK and its
`inverted clock signal CKB and a high-threshold logic circuit
`driven by the clock signals output from the low-threshold
`logic circuit. Referring to FIG. 1, reference numeral 10
`denotes a control circuit for outputting control signals CS
`40 and CSB for turning on/off control transistors (to be
`described later). The control signal CSB is a signal obtained
`by inverting the control signal CS. Reference symbols T81
`and T82 denote field effect MOS control transistors. The
`transistor T 81 is a p-channel transistor for connecting or
`disconnecting a power line PL1 for receiving a power supply
`voltage V DD to or from a dummy power line QL1. The
`transistor T52 is an n-channel transistor for connecting or
`disconnecting a grounded power line PL2 to or from a
`dummy power line QL2. Reference symbol 20 denotes a
`low-threshold (low-V,h) CMOS logic circuit. This low(cid:173)
`threshold logic circuit 20 comprises two inverters INV1 and
`INV2 for generating the inverted clock signal CKB from the
`clock signal CK. For example, the inverter INV1 is consti(cid:173)
`tuted by two low-threshold MOS transistors T21 and T22
`55 having cascade-connected output electrodes and commonly
`connected input electrodes. The transistorT21 is a p-channel
`transistor, while the transistor T22 is an n-channel transistor.
`One of the output electrodes of the transistor T21 is con(cid:173)
`nected to the dummy power line QL1, and one of the output
`60 electrodes of the transistor T22 is connected to the dummy
`power line QL2. The inverter INV2 is arranged in the same
`manner as the inverter INV1 except that the inverter INV2
`receives an output from the inverter INV1, so that the
`inverter INV2 is represented by an abbreviated symbol. In
`this case, according to the present invention, it should be
`noted that the common dummy power lines QL1 and QL2
`are connected to all the logic elements constituting the
`
`SUMMARY OF THE INVENTION
`
`It is a principal object of the present invention to provide
`a logic circuit capable of performing a high-speed operation 45
`even if a power supply voltage is decreased.
`It is another object of the present invention to provide a
`logic circuit capable of reducing power consumption even if
`the power supply voltage is decreased.
`In order to achieve the above objects of the present
`invention, there is provided a logic circuit comprising a
`low-threshold logic circuit having a logic circuit element
`constituted by a plurality of low-threshold field effect tran(cid:173)
`sistors, a pair of first and second power lines for supplying
`power to the low-threshold logic circuit, a first dummy
`power line connected to one of power source terminals of the
`low-threshold logic circuit, and a first high-threshold control
`transistor arranged between the first dummy power line and
`the first power line.
`
`50
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a system diagram showing a logic circuit
`according to an embodiment of the present invention;
`FIG. 2 is a graph showing delay times as a function of
`power supply voltages in a conventional example and the
`logic circuit of the embodiment shown in FIG. 1;
`
`65
`
`0011
`
`

`

`5,486,774
`
`15
`
`20
`
`3
`low-threshold logic circuit 20. The dummy power line QLl
`is connected to the power line PL1 (e.g., a V vv potential)
`through the output electrode of the transistor T s1 , and the
`dummy power line QL2 is connected to the power line (e.g.,
`a ground potential) through the output electrode of the
`transistor Tsz· The low-threshold logic circuit can be arbi(cid:173)
`trarily arranged in a variety of circuits using AND, OR, and
`NAND gates in consideration of application purposes and
`other factors. The low-threshold logic circuit 20 is not
`limited to the circuit of this embodiment. The control signals 10
`CSB and CS are input to the input electrodes of the tran(cid:173)
`sistors Ts1 and Tsz·
`Reference numeral30 denotes a high-threshold (high-V,h)
`CMOS logic circuit constituted by a latch circuit consisting
`of two transfer gates LC1 and LC2 and three inverters INV3,
`INV4, and INVS. Power supply of this latch circuit is
`controlled through two high-threshold MOS field effect
`transistors T ss and T s6 • In this case, the transistor T ss is a
`p-channel transistor, while the transistor T s6 is an n-channel
`transistor. The transfer gate LC1 is constituted by two
`low-threshold field effect MOS transistors T31 and T32. The
`output electrodes of these transistors are commonly con(cid:173)
`nected. One of the output electrodes is connected to a
`terminal for receiving data D, and the other is connected to
`the input of the inverter INV3. The input electrode of the 25
`transistor T31 receives the clock signal CK, and the input
`terminal of the transistor T32 receives the inverted clock
`signal (CL) CKB. The transfer gate LC2 is arranged in the
`same manner as the transfer gate LCl. One of the output
`electrodes is connected to the output of the transfer gate 30
`LC1, and the other is connected to the input of the inverter
`INV3. Each of the inverters INV3, INV4, and INVS is
`arranged in the same manner as the inverter INVl. It should
`be noted that transistors of the inverters INV4 and INVS are
`constituted by high-threshold MOS
`transistors while 35
`transistors of the inverter INV3 are constituted by low(cid:173)
`threshold MOS transistors. Each transistor constituting the
`transfer gate LC2 may be a low- or high-threshold transistor.
`One of the output electrodes of the inverter INV3 is
`connected to the power line PL1 through a high-threshold 40
`transistor Ts5 , and the other output electrode of the inverter
`INV3 is connected to the power line PL2 through the
`transistor T s6 . The control signal CSB is supplied to the
`input electrode of the transistor Ts5 , and the control signal
`CS is supplied to the input electrode of the transistor T s6 •
`The inverter INV4 is connected in parallel with the
`inverter INV3. The inverter INV4 is different from the
`inverter INV3 in that the output electrodes of the series(cid:173)
`connected transistors are directly connected to the power 50
`lines PL1 and PL2 without going through the transistors T ss
`and Ts6 • The outputs of the inverters INV3 and INV4 are
`commonly connected to supply an output of the latch circuit
`to the next stage. In this latch circuit, an inverter INVS is
`connected between the outputs of the inverters INV3 and 55
`INV 4 and one of the output electrodes of the transfer gate
`LC2.
`The inverter INVS is constituted by two high-threshold
`transistors. These transistors are directly connected to the
`power lines PL1 and PL2 in the same manner as the inverter
`INV4.
`With the above arrangement, when the control signals CS
`and CBS are output from the control circuit 10, and more
`specifically, when the selection control signal CSB of low
`level is supplied to the control or input electrode, and the
`selection control signal CS of high level is supplied to the
`control or input electrode, the high-threshold control
`
`4
`transistors T s1 and T sz are turned on, and a potential appears
`across the dummy power lines QL1 and QL2. For this
`reason, each logic element constituting the low-threshold
`logic circuit 20 is set in a state applied with the power supply
`5 voltage and performs a logic operation in accordance with
`the clock signals CK and CKB. At this time, since each logic
`element constituting the low-threshold logic circuit 20 has a
`low threshold voltage, a high-speed operation can be
`performed even if the power supply voltage is decreased.
`When the control signals CS and CSB are not selected,
`i.e., when these signals are not supplied to the transistors T s1
`and T sz and the transistors T s1 and T sz are kept off, no power
`supply voltage appears across the dummy power lines QLl
`and QL2, and the power supply voltage is not applied to the
`low-threshold logic circuit 20. In other words, the low(cid:173)
`threshold logic circuit 20 is rendered inoperative. At this
`time, since the control transistors Ts1 and Ts2 have a high
`threshold voltage, an increase in power consumption in an
`OFF state does not occur even if the circuit 20 connected to
`the outputs of the transistors T s 1 and T sz is constituted by
`low-threshold logic elements. Therefore, the operation delay
`time of this logic circuit can be suppressed.
`The operation of the latch circuit driven by the low(cid:173)
`threshold logic circuit 20 will be described below.
`A signal of the input data D is supplied to the transfer gate
`LC1 at timings of the clock signals CK and CKB input to the
`transfer gate LC1 and is supplied to the inverters INV3 and
`INV4. The inverter INV3 receives the output from the
`transfer gate LCl upon reception of the power supply
`voltage input in synchronism with the control signals CSB
`and CS output from the control circuit 10. Outputs from the
`inverters INV3 and INV 4 are supplied as an output from the
`latch circuit to the next stage, and at the same time are
`supplied to the inverter INVS. An output from the inverter
`INVS is supplied to the transfer gate LC2. The transfer gate
`LC2 supplies this output to the input of the inverter INV3 at
`the timings of the clock signals CK and CKB, thereby
`latching the received signal.
`In this case, when the control signal CS of high level and
`the control signal CSB oflow level are output, the transistors
`Ts6 and Tss are turned on. This section serves as a high(cid:173)
`speed D flip-flop master portion in accordance with
`operations of the transistors constituting the inverters INV3,
`INV4, and INVS and the transistors constituting the transfer
`gates LC1 and LC2.
`When the control signals CS and CSB are not selected, the
`NMOS transistors Ts6 and Tss are kept off, and the CMOS
`inverter INV3 constituted by the low-threshold transistors is
`kept off. However, since the inverters INV4 and INVS
`constituted by the high-threshold transistors connected in
`parallel with the inverter INV3 and the transfer gate LC2
`hold the data, the data in the latch circuit is not destroyed.
`In addition, since this latch circuit is connected to the power
`lines PLl and PL2 through the high-threshold transistors Ts6
`and T ss, no increase in power consumption in the OFF state
`occurs.
`FIG. 2 is a graph showing effects of the logic circuit of the
`present invention and the conventional logic circuit. The
`60 power supply voltage V vv is plotted along the abscissa, and
`the delay time tpd is plotted along the ordinate. A
`characteristic curve a represents a relationship between the
`delay time and the power supply voltage when the logic
`circuit shown in FIG. 12 is used. A characteristic curve b
`65 represents a relationship between the delay time and the
`power supply voltage when the logic circuit according to the
`present invention is used. When the logic circuit according
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`to the present invention is used at the power supply voltage
`of 1 V, an increase in power consumption in the OFF state
`does not occur. As compared with the conventional logic
`circuit, the delay time can be shortened by 50%.
`As described above, when the logic circuit of the present
`invention is used, a high-speed operation can be performed
`even with a decrease in power supply voltage since a
`transistor having a low-threshold voltage is used. In
`addition, in the OFF state, since the logic circuit can be kept
`off by a transistor having a high threshold voltage, thereby
`reducing the power consumption.
`FIG. 3 shows frequency characteristics of the logic circuit
`of the present invention, and particularly, the latch circuit as
`the latter stage of the logic circuit. The maximum toggle
`frequency serving as the maximum frequency of the clock
`signal (CK) for normally operating the latch circuit is plotted
`along the ordinate, and the power supply voltage is plotted
`along the abscissa. In FIG. 3, a characteristic line P
`represents the frequency characteristics in use of the logic
`circuit of the present invention, and a characteristic line Q 20
`represents the frequency characteristics in use of the
`conventional logic circuit.
`Referring to FIG. 3, the maximum toggle frequency of the
`logic circuit of the present invention is 500 MHz at the
`power supply voltage of 1 V, while the maximum toggle
`frequency of the conventional logic circuit is 100 MHz at the
`same power supply voltage. When the logic circuit of the
`present invention is used, the maximum toggle frequency of
`the D flip-flop can be increased five times that of the
`conventional logic circuit without increasing the power
`consumption in the OFF state.
`FIG. 4 shows another embodiment of the present
`invention. Most of the circuit of this embodiment is
`substantially the same as that of the embodiment in FIG. 1, 35
`so that only a portion required to explain the embodiment of
`FIG. 4 is accurately illustrated. That is, in the embodiment
`of FIG. 4, capacitors Cl and C2 are connected between a
`dummy power line QLl and a power line PLl and between
`a dummy power line QL2 and a power line PL2, 40
`respectively, thereby reducing the power supply voltage
`variations at nodes N2 and Nl between the dummy power
`lines and the power lines of a low-V,h logic circuit 20. When
`the capacitances of these capacitors are increased, the delay
`time of the operation of this circuit can be shortened, and a 45
`higher-speed operation than that in the embodiment of FIG.
`1 can be achieved. In this case, the capacitors Cl and C2 are
`connected between the substrate and the drain of a transistor
`T si and between the substrate and the drain of a transistor
`Ts2 in a practical device. With this arrangement, an increase 50
`in capacitance can be achieved by increasing the width of the
`dummy power lines, and no special capacitance increase
`process is required.
`FIG. 5 shows still another object of the present invention
`and, more particularly, a modification of the latch circuit. 55
`The same reference numerals as in FIG. 1 denote the same
`functions in FIG. 5 since only the layout is modified. More
`specifically, in FIG. 5, a series-connected arrangement of an
`inverter INV3 and control transistors T ss and T s6
`is
`connected to the input of a transfer gate LCl. With this
`arrangement, the same operation as in FIG. 1 can be
`performed although signal input operations are divided. A
`series-connected arrangement of the control transistor T ss,
`the inverter INV3, and the control transistor T s6 may be
`connected to the input or output of the transfer gate LCl in
`the circuit of FIG. 1. However, the delay time of the
`arrangement in FIG. 5 can be decreased by a time
`
`6
`corresponding to one inverter than that of the arrangement of
`the above modification.
`FIG. 6 shows still another embodiment and, more
`particularly, a modification of the latch circuit in FIG. 1. In
`this embodiment, a series-connected arrangement of an
`inverter INV3 and control transistors Ts5 and Ts6 is omitted.
`With this arrangement, a circuit 30 can be operated as a latch
`circuit as in the operations of FIGS. 1 and 4.
`FIGS. 7 and 8 show still another embodiment and, more
`10 particularly, a memory device to which the present invention
`is applied. In this embodiment, of the logic circuit group
`obtained by cascade-connecting MOS selector logic circuits
`constituted by MOSFETs having a low threshold voltage,
`the logic circuit of the latter stage is connected to one (QLl
`in this embodiment) of dummy power lines, and the logic
`circuit of the former stage is connected to the other dummy
`power line (QL2 in this embodiment), thereby controlling
`floating of the output potential.
`FIG. 7 shows a selector logic circuit 60 constituted by
`2-input NAND gates NANDI to NANDn and inverters
`INV21 to INV2n. One end of the power source terminal of
`each of the 2-input NAND gates NANDI to NANDn is
`connected to a power line PLl, and the other end of the
`power source terminal of each of the NAND gates NANDI
`to NANDn is connected to the dummy power line QL2. This
`dummy power line QL2 is connected to a power line PL2
`through a control transistor TsZA· Each NAND gate used
`here is constituted by low-V,11 CMOS transistors. As shown
`in FIG. 7, each NAND gate comprises parallel-connected
`p-channel MOS transistors T61 and T62 and n-channel MOS
`transistors T63 and T64 series-connected to the sources of
`the transistors T61 and T62. The gate electrodes of the
`transistors T62 and T63 are commonly connected to one
`input terminal 11, and the gate electrodes of the transistors
`T61 and T64 are commonly connected to the other input
`terminal I2 .
`Each of the inverters INV21 to INV2n is arranged in the
`same manner as the inverter shown in FIG. 1 and comprises
`two series-connected low-V,h transistors T65 and T66. One
`of the output electrodes of the transistor T65 is connected to
`the dummy power line QLl, and this dummy power line
`QLl is connected to the power line PLl (V nn in this
`embodiment) through a common control transistor Ts1A(cid:173)
`One of the output electrodes of the transistor T66 is directly
`connected
`to
`the power
`line PL2 (ground
`in
`this
`embodiment) without going through any dummy power line.
`Two inputs are supplied to each of the NAND gates
`NANDI to NANDn, and an output from each NAND gate
`is supplied to the input of a corresponding one of the
`inverters INV21 to INV2n. Outputs from the inverters
`INV21 to INV2n are supplied to the corresponding cells of
`a memory cell array 70 through word lines WLl to WLn,
`respectively.
`The memory cell array 70 is constituted by cells arranged
`in an nxm matrix. As shown in FIG. 8, each memory cell
`comprises a pair of a series-connected arrangement of p- and
`n-channel high-V,11 CMOS transistors Til and T72 and a
`series-connected arrangement of p- and n-channel high-V,11
`60 CMOS transistors T73 and T74, which are arranged between
`power lines PLl and PL2, ann-channel high-V,~z transistor
`T75 arranged between a bit line BLB (BL) constituting a bit
`line pair with a bit line BLand a connecting point between
`the transistors T73 and T74, and an n-channel high-v,h
`transistor T76 arranged between the bit line BL and a
`connecting point between the transistors Til and T72. The
`connecting point between the transistors Til and T72, the
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`5,486,774
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`gate electrodes of the transistors T73 and T74, and one of the
`output electrodes of the transistor T75 are commonly
`connected. Similarly, the connecting point between the
`transistors T73 and T74, the gate electrodes Til and T72,
`and one of the output electrodes of the transistor T76 are 5
`commonly connected. The other output electrode of the
`transistor T76 is connected to the bit line BL and a
`multiplexer MUX. The other output electrode of the
`transistor T75 is connected to the bit line BLB (BL) and the
`multiplexer MUX. The word line WL is connected to the 10
`gate electrodes of the transistors T76 and T75. When a signal
`of high level is supplied to the word line WL, the potential
`at the connecting point between the transistors Til and T72
`and the potential at the connecting point between the
`transistors T73 and T74 are extracted as signals. The inputs 15
`are multiplexed into 1 outputs by the multiplexer MUX.
`These 1 multiplexer outputs DO to Dl are supplied to a read
`circuit 80.
`The read circuit 80 is also arranged in the form of two
`stages as in the selector logic circuit 60. One of the power 20
`source terminals of INV31 to INV31 to which the
`multiplexer outputs DO to Dl are supplied from the memory
`cell array 70 is connected to the dummy power line QLl, and
`to the power line PLl (V vv in this embodiment) through a
`control transistor T siB· This one power source terminal is
`then connected to the other power source terminal PL2
`(ground in this embodiment) of the inverters INV31 to
`INV31.
`One of the power source terminals of inverters INV 41 to
`INV41 which respectively receive the outputs from the
`inverters INV31 to INV31 is connected to the dummy power
`line QL2 and to the power line PL2 (ground in this
`embodiment) through a control transistor T828. This one
`power source terminal is then connected to one power
`source terminal PLl (V vv in this embodiment) of the
`inverters INV41 to INV41.
`With this arrangement, the operation of the selector logic
`circuit 60 in the non-selection mode will be described below.
`In this case, since the control signal supplied to the control
`transistor TsZA for controlling the NAND gates NANDl to
`NANDn of the former stage in the selector logic circuit 60
`is set at a low potential, the transistor T S2A is kept off. Since
`the input terminals I1 and I2 of the NAND gates are set at a
`non-selection state, they are set at a low potential. The
`transistors T61 and T62 are turned on to set the dummy
`power line QL2 at the high voltage V vv· At this time, in the
`inverters of the latter stage (e.g., INV21), since the control
`signal CSB applied to the control transistor T SlA is set at a
`high potential, the control transistor T81 A is set in an OFF
`state. At this time, since the transistor T66 is set in an ON
`state, an output from the inverter INV21 is set at the low
`potential. As a result, as described above, a high-speed
`operation of the logic circuit in a selection mode and low
`power consumption in a non-selection mode can be 55
`achieved.
`In this embodiment, the control transistor on the NAND
`gate side is set at the low potential and the control transistor
`on the inverter side is set at the high potential. However, the
`control transistor on the NAND gate side may be set at the 60
`high potential, and the control transistor on the inverter side
`may be set at the low potential, as a matter of course. It is
`easily anticipated for those who are skilled in the art to
`arrange this selector logic circuit by using logic circuit
`elements except for the logic circuit elements used here. The 65
`number of