(12) Unlted States Patent
`(16) Patent N0.:
`US 6,653,693 B1
`
`Makino
`(45) Date of Patent:
`*Nov. 25, 2003
`
`USOO6653693B1
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE
`
`(75)
`
`Inventor: Hiroshi Makino; Tokyo (JP)
`-
`-
`'
`.
`-
`-
`-
`-
`-
`(73) ASSlgnee‘ M1tsub1sh1 Denkl Kabushlkl KaISha’
`Tokyo (JP)
`
`5,073,726 A * 12/1991 Kato et a1. .................... 326/24
`5,309,011 A *
`5/1994 Tazunoki et 211.
`5,455,438 A * 10/1995 Hashimoto et al.
`
`....................... 326/17
`5/1997 Ohnishi
`5,633,600 A *
`7/1997 Ikeda et al.
`5,652,457 A *
`6,144,223 A * 11/2000 Momtaz ...................... 326/83
`6,181,542 B1 *
`1/2001 Liang et al.
`................ 361/111
`FOREIGN PATENT DOCUMENTS
`
`(*) Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`13:5,?12331523123If: t2: 2‘:m1}; £63
`p
`p
`‘
`‘
`‘
`5400(2)
`.
`.
`.
`.
`SubJeCt to any dISC1almer> the term 0fth15
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`3111:
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`gggggggg 2 : 313;:
`62283718 A * 12/1987
`02203620 A *
`8/1990
`04056342 A *
`2/1992
`04170063 A *
`6/1992
`04254777 A *
`9/1992
`A—6/29834
`2/1994
`A—212218
`8/1995
`A-8/18021
`1/1996
`
`~~~~~~~~~~ $359763
`:22: H03K/19/094
`....... H03K/19/0948
`........... H01L/21/82
`
`H01L/27/04
`........... GO1R/31/28
`
`(21) Appl. No.: 09/034,257
`
`* cited by examiner
`
`Mar. 4’ 1998
`Filed:
`(22)
`Foreign Application Priority Data
`(30)
`NOV. 11, 1997
`(JP)
`............................................. 9—309024
`
`Int. Cl.7 ............................................ H01L 21/8232
`(51)
`(52) US. Cl.
`....................... 257/391; 257/392; 257/393;
`257/401
`(58) Field of Search ................................. 257/372, 379,
`257/390, 391, 401, 909, 206, 392, 393
`
`(56)
`
`References Cited
`
`US. PATENT DOCUMENTS
`
`Primary Examiner—George Fourson
`(74) Attorney, Agent, or Firm—Burns; Doane; Swecker &
`Mathis, LLP
`
`(57)
`
`ABSTRACT
`
`A semiconductor integrated circuit device of a low power
`consumption capable of performing under a low voltage has
`an array section 21 in which only low threshold voltage
`MOS FETs are formed; and areas other than the array section
`21 in Which high threshold voltage MOS FETs Whose
`threshold voltage is higher than that of each low threshold
`voltage MOS FET formed in the array section are formed.
`
`4,855,620 A *
`
`8/1989 Duvvury et al.
`
`............ 326/119
`
`5 Claims, 8 Drawing Sheets
`
`
`
`
`
`
`
`VOLTAGE
`REGION
`
`
`
`OUTPUT
`CIRCUIT
`
`
`
`OUTPUT
`CIRCUIT
`
`35
`
`‘ ’ '
`
`AMD EX1006
`
`0001
`
`US. Patent No. 6,239,614
`
`AMD EX1006
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 1 0f 8
`
`US 6,653,693 B1
`
`FIG.1
`
`
`
`C81
`
`VBl
`
`13
`
`0002
`
`0002
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 2 0f 8
`
`US 6,653,693 B1
`
`FIG.2(PRIOR ART)
`
`260
`
`26
`
`210
`
`250
`
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`
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`
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`230
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`0003
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 3 0f 8
`
`US 6,653,693 B1
`
`FIG.3
`
`27
`
`27
`
`27
`
`IIIITIIIIIZIIIIIIZIIZ 22
`\\\.
`
`23
`
`ARRAY SECTION _2_1
`
`25
`
`27
`
`27
`
`27
`
`27
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`
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`27
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`27
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`27
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`27
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`27
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`0004
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`0004
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`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 4 0f 8
`
`US 6,653,693 B1
`
`FIG.4
`
`VOLTAGE
`REGION
`
`REGION
`
`VOLTAGE
`REGION
`
`CIRCUIT
`
`INPUT/ /
`
`° 0 0
`
`OUTPUT
`CIRCUIT
`
`SWITCH
`
`INPUT/
`OUTPUT
`
`° ° °
`
` OUTPUT
`
`BUFFER
`
` INPUT
`
`BUFFER
`
`
`
`37
`
`0005
`
`0005
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 5 0f 8
`
`US 6,653,693 B1
`
`FIG.6
`
`ARRAY SECTION 2_1
`
` V'i'V’V 7 aI'P' il'l' ' 'Vl' il'l' 7 'Vl' if'l' 7 '7'?
`iflifiiiififiifiiifiiiiifiifi 2”
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`
`0006
`
`0006
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 6 0f 8
`
`US 6,653,693 B1
`
`POWER
`
`SOURCE
`
`\:
`
`\\\\‘§\\\§
`
`REGION
`
`.“““\
`
`I3a2
`
`HIGH
`
`THRESHOLD
`
`VOLTAGE
`
`REGION
`
`LOW
`
`THRESHOLD
`
`VOLTAGE
`
`0007
`
`0007
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 7 0f 8
`
`US 6,653,693 B1
`
`FIGS
`
`72 SPACE REGION
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`71 SPACE
`REGION
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`
`73 SPACE REGION
`
`74 SPACE
`REGION
`
`0008
`
`0008
`
`

`

`US. Patent
`
`Nov. 25, 2003
`
`Sheet 8 0f 8
`
`FIG.9
`
`22 IIIIIIIIIIIIIIIIIIIII
`1//
`ARRAY SECTION}
`
`23
`
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`IIIIIIIIIIIIIIIIIIIII 24
`
`0009
`
`

`

`US 6,653,693 B1
`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a semiconductor inte-
`grated circuit device of a low electric power consumption
`type.
`2. Description of the Prior Art
`FIG. 1 is a circuit diagram showing the configuration of
`a circuit capable of performing under a low electric voltage
`as a semiconductor integrated circuit device that will be used
`for explanation of preferred embodiments according to the
`present invention and following conventional examples. The
`diagram of this circuit capable of performing under the low
`voltage shown in FIG. 1 was also disclosed in the patent
`document of Japanese patent laid open publication number
`JP-A-7/212218 as a conventional semiconductor integrated
`circuit device.
`
`The circuit capable of performing under a low electrical
`voltage as a semiconductor integrated circuit device shown
`in FIG. 1 comprises multi-threshold complementary metal
`oxide semiconductors (hereinafter also referred to as MT
`CMOS).
`In FIG. 1, the reference number 1 designates a two-input
`NAND gate. Each of the reference numbers 2 and 3 denotes
`a p channel type metal oxide semiconductor field effect
`transistor (hereinafter referred to as a p MOS FET). Each of
`the reference numbers 4 and 5 indicates n channel type metal
`oxide semiconductor field effect
`transistors (hereinafter
`referred to as a n channel MOS FET). In the circuit shown
`in FIG. 1, the absolute value of the threshold voltage of this
`p MOS FET is set to a low value and the absolute value of
`the threshold voltage of this n MOS FET is set to a high
`value. The reference number 6 designates a power source of
`a predetermined voltage, 7 denotes a ground power source.
`The reference number 8 indicates a p channel MOS FET
`connected between the power source 6 and a power source
`line 12 as a hypothetical power source line. This p channel
`MOS FET 8 becomes active when a gate terminal of the P
`channel MOS FET 8 receives a control signal 9. The
`reference number 10 indicates an n channel MOS FET
`
`connected between ground 7 and a ground line 13 that is a
`hypothetical ground line. This n channel MOS FET 10
`becomes active when a gate terminal of the n channel MOS
`FET 10 receives a control signal 11. In this circuit shown in
`FIG. 1,
`it
`is formed so that the absolute values of the
`threshold voltages of the p channel MOS FET 8 and the n
`channel MOS FET 10 are higher than the absolute values of
`the threshold voltages of the p channel MOS FETs 2 and 3
`and the n channel MOS FETs 4 and 5 forming the two-input
`NAND gate 1, respectively.
`FIG. 2 is a conventional layout pattern of a memory cell
`array in a conventional semiconductor integrated circuit
`device that was disclosed in the patent document of Japanese
`patent laid open publication number JP-A-8/18021. In FIG.
`2, the reference number 210 indicates an array section in
`which a plurality of MOS FETs are arranged in an array
`form. The reference numbers 220, 230, 240, and 250 denote
`input/output circuit forming sections located in a peripheral
`section of the array section 210,
`in which input/output
`circuits are formed. The reference number 260 designates a
`region in which MOS FETs, each having a high threshold
`voltage, are formed in the array section 210. Further, the
`reference number 270 designates a region in which MOS
`
`10
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`0010
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`2
`FETs, each having a low threshold voltage, are formed in the
`array section 210.
`Next, a description will be given of the operation of the
`conventional circuit capable of performing under a low
`supply voltage as the conventional semiconductor integrated
`circuit device shown in FIG. 2.
`
`In recent years, there have been significant advancements
`of technology in portable devices such as mobile telephone
`devices and the portable devices are widely used in the
`world. Accordingly,
`it must be required to operate those
`portable devices under a lower power voltage in order to
`maintain the voltage of a battery as long as possible. To
`reduce the operational voltage used in the portable devices
`is an effective method to reduce the power consumption of
`the portable devices as small as possible. Because the power
`consumption is obtained by multiple of a voltage value and
`a current value, it is possible to reduce both the voltage value
`and the current value by reducing the operational voltage of
`the devices. In general,
`this method causes to obtain a
`greatly effect
`to reduce the power consumption of the
`devices. However, a MOS FET forming a semiconductor
`integrated circuit has a drawback in which the operation
`speed of the MOS FET becomes low according to reducing
`of the operational voltage. This characteristic of the MOS
`FET is based on that its threshold voltage is not reduced in
`proportion to the reducing of the voltage value of the power
`source. The reason is that the magnitude of a leak current
`under an off state (an inactive state) of the MOS FET is
`increased when the threshold voltage of the MOS FET is
`decreased, so that the power consumption is also increased.
`In order to solve the conventional drawback described
`
`above, a following conventional method is used.
`In the circuit operable under a low voltage shown in FIG.
`1, when the two-input NAND gate 1 operates, the level of
`the control signal (CSBl) 9 is set to a low level and the
`control signal (CS1) 11, which is an inverted signal of the
`control signal (CSBl) 9 in voltage level, is set to a high
`level. Thereby, both the p channel MOS FET 8 and the n
`channel MOS FET 10 are ON and the voltage potential of
`the hypothetical power source line 12 rises up to the voltage
`level of the power source and the voltage potential of the
`ground line 13 is fallen to the voltage level of the ground
`GND 7. As a result, two-input NAND gate 1 operates as a
`normal NAND gate. In this case, because the threshold
`voltage of each of the MOS FETs 2 to 5 is set to the low
`value, it is possible to operate the two-input NAND gate 1
`at a high speed when the voltage level of the power source
`6 is low.
`
`When the two-input NAND gate 1 is not used, the control
`signal (CSBl) 9 is set to the high level and the control signal
`(CS1) 11, that is the inverted signal of the control signal
`(CSBl) 9 in voltage level, is set to the low level. At this time,
`both the p channel MOS FET 8 and the n channel MOS FET
`10 become OFF, so that the hypothetical power source lines
`12 and the hypothetical ground line 13 are electrically
`disconnected from the power source 6 and the ground 7,
`respectively.
`Because it is so formed that the absolute value of the
`
`threshold voltage of each of the p channel MOS FET 8 and
`the n channel MOS FET 10 is higher than that of each of the
`MOS FETs 2 to 5, it is possible to suppress the value of the
`leak current within a lower value.
`
`In general, in a region in which the voltage between the
`gate and the source of a MOS FET is lower than a threshold
`voltage of the MOS FET, the magnitude of the leak current
`flowing through the source and the drain is exponentially
`
`0010
`
`

`

`US 6,653,693 B1
`
`3
`increased according to the value of the voltage of the gate.
`It is therefore possible to greatly reduce the leak current
`when the MOS FETs 2 to 5 and the MOS FETs 8 and 10 have
`
`different threshold voltage values.
`Although the above conventional example shows the
`two-input NAND gate 1 comprising MOS FETs, each hav-
`ing the lower absolute value of the threshold voltage, it is
`possible to apply the above method to many kinds of
`semiconductor integrated circuits in size and function such
`as other logical circuits, memory devices, and the like.
`FIG. 2 is the conventional layout of the circuit comprising
`gate arrays capable of performing under a low voltage as the
`semiconductor integrated circuit shown in FIG. 1. In FIG. 1,
`both the p channel MOS FET 8 and the n channel MOS FET
`10, each having a higher threshold voltage, are formed in
`regions 260, and the p channel MOS FETs 2 and 3 and the
`n channel MOS FETs 4 and 5, each having a lower threshold
`voltage, are formed in regions 270 that are the regions other
`than the region 260 in the array section 210. Further, the
`electric power from the power source 6, the ground voltage
`from the ground 7, and the control signals 9 and 11 are
`supplied to the array section 210 through input/output circuit
`regions 220, 230, 240, and 250.
`Because the conventional circuit capable of performing
`under the low voltage as the semiconductor integrated
`circuit device has the configuration described above,
`namely, because both MOS FETs having the high threshold
`voltage and the low threshold voltage are formed in the array
`section 210, it is difficult to use the regions 260 (that is used
`for the MOS FETs having the high threshold voltage) in the
`array section for the internal circuits such as the two-input
`NAND gate 1 and wiring transferring signals and voltages of
`power source. Thereby, it becomes necessary to reduce the
`wiring efficiency in the array section 210 and the peripheral
`section thereof. This limitation causes to reduce the density
`of the layout of the semiconductor integrated circuit device.
`In addition, in order to obtain a low power consumption,
`when the MT CMOS is used in a previously designed circuit
`(or in a pre-designed circuit) in which the MT CMOS is not
`used, it is difficult to use the pre-designed circuit without
`changing this layout pattern by the limitation of the regions
`260 in the array section 210 in which the MOS FETs having
`the high threshold voltage are formed. This conventional
`layout of the circuit causes a drawback that it must be
`required to design a new layout pattern again.
`SUMMARY OF THE INVENTION
`
`10
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`
`Accordingly, an object of the present invention is, with
`due consideration to the drawbacks of the conventional
`
`50
`
`semiconductor integrated circuit device, to provide a semi-
`conductor integrated circuit device as a circuit capable of
`performing under a lower voltage by forming MOS FETs
`having a higher threshold voltage in regions other than the
`array section, capable of improving a layout efficiency and
`capable of using pre-designed circuits to be used in an array
`section without any changing of its circuit design and layout
`pattern.
`In accordance with a preferred embodiment of the present
`invention, a semiconductor integrated circuit device com-
`prises an array section in which a plurality of low threshold
`voltage metal oxide semiconductor field effect transistors
`(MOS FETs) are formed in array form, and input/output
`circuit forming areas other than the array section in which
`high threshold voltage MOS FETs having a high threshold
`voltage are formed. In the semiconductor integrated circuit
`device described above, the threshold voltage of each of the
`
`55
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`60
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`65
`
`4
`high threshold voltage MOS FETs is higher than a threshold
`voltage of each of the plurality of low threshold voltage
`MOS FETs formed in said array section.
`In accordance with another preferred embodiment of the
`present invention, a semiconductor integrated circuit device
`comprises an array section in which a plurality of low
`threshold voltage metal oxide semiconductor field effect
`transistors (MOS FETS) are formed in array form, and
`input/output circuit forming areas located at peripheral sec-
`tions of the array section, each area comprising a first area
`in which input/output circuits are formed and a second area
`in which MOS FETs whose absolute vale of a threshold
`
`voltage being higher than an absolute value of a threshold
`voltage value of each of the plurality of low threshold
`voltage MOS FETs formed in the array section.
`In accordance with another preferred embodiment of the
`present invention, a semiconductor integrated circuit device
`comprises an array section in which a plurality of metal
`oxide semiconductor field effect transistors (MOS FETs) are
`formed in array form, and a plurality of areas, located at
`peripheral sections of the array section,
`in which high
`threshold voltage metal oxide field effect transistors (MOS
`FETs) and low threshold voltage MOS FETs are formed. In
`the semiconductor integrated circuit device described above,
`an absolute value of a threshold voltage of each of the high
`threshold voltage MOS FETs is higher than an absolute vale
`of a threshold voltage of each of the plurality of MOS FETs
`formed in the array section, and an absolute value of a
`threshold voltage of each of the low threshold voltage MOS
`FETs is lower than the absolute vale of the threshold voltage
`of each of the high threshold voltage MOS FETs, and each
`of the plurality of areas has an input/output circuit forming
`area having a same configuration.
`In the semiconductor integrated circuit device as another
`preferred embodiment of the present invention, the plurality
`of high threshold voltage MOS FETs are formed at areas of
`four corners other than the array section and the input/output
`circuit forming sections in the semiconductor integrated
`circuit.
`
`In the semiconductor integrated circuit device as another
`preferred embodiment of the present invention, the plurality
`of high threshold voltage MOS FETs are formed at space
`areas between the array section and the input/output circuit
`forming sections in the semiconductor integrated circuit.
`In the semiconductor integrated circuit device as another
`preferred embodiment of the present invention, switch cir-
`cuits for supplying power sources to the array section and
`electrically cutting the power sources from the array section
`are formed in the input/output circuit forming areas by using
`the high threshold voltage MOS FETs, and input/output
`circuits for inputting signals to the array section and out-
`putting the signals from the array section are formed in the
`input/output circuit forming areas by using both the high
`threshold voltage MOS FETs and the low threshold voltage
`MOS FETS.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other objects, features, aspects and advantages
`of the present invention will become more apparent from the
`following detailed description of the present invention when
`taken in conjunction with the accompanying drawings, in
`which:
`
`FIG. 1 is a circuit diagram showing a low voltage circuit
`capable of performing under a low voltage as a semicon-
`ductor integrated circuit device of the first embodiment
`according to the present invention;
`
`0011
`
`0011
`
`

`

`US 6,653,693 B1
`
`5
`FIG. 2 is a diagram showing a layout pattern of a
`conventional semiconductor integrated circuit device corre-
`sponding to the low voltage circuit capable of performing
`under the low voltage shown in FIG. 1;
`FIG. 3 is a diagram showing a layout pattern of regions in
`which the low voltage circuits capable of performing under
`the low voltage shown in FIG. 1 are formed as the semi-
`conductor integrated circuit device of the first embodiment
`according to the present invention;
`FIG. 4 is a diagram showing detailed layout patterns of
`the regions in which input/output circuits are formed in the
`semiconductor integrated circuit as the first embodiment
`shown in FIG. 3;
`FIG. 5 is a detailed circuit diagram showing the input/
`output circuit formed in the input/output forming region in
`the semiconductor integrated circuit of the first embodiment
`shown in FIG. 3;
`FIG. 6 is a diagram showing another layout pattern of the
`low voltage circuit capable of performing under the low
`voltage as the semiconductor integrated circuit device of the
`second embodiment according to the present invention;
`FIG. 7 is a diagram showing another layout pattern of the
`regions in which the input/output circuits are formed in the
`semiconductor integrated circuit as the second embodiment
`shown in FIG. 6;
`FIG. 8 is a diagram showing another layout pattern of the
`low voltage circuit capable of performing under the low
`voltage as the semiconductor integrated circuit device of the
`third embodiment according to the present invention; and
`FIG. 9 is a diagram showing another layout pattern of the
`low voltage circuit capable of performing under the low
`voltage as the semiconductor integrated circuit device of the
`fourth embodiment according to the present invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Other features of this invention will become apparent
`through the following description of preferred embodiments
`which are given for illustration of the invention and are not
`intended to be limiting thereof.
`Preferred embodiments of the semiconductor integrated
`circuit device according to the present invention will now be
`described with reference to the drawings.
`First Embodiment
`
`FIG. 1 is the circuit diagram showing the circuit capable
`of performing under the low voltage as the semiconductor
`integrated circuit device of the first embodiment according
`to the present invention.
`The circuit capable of performing under the low voltage
`(hereinafter referred to as the low voltage operation circuit)
`comprises multi-threshold complementary metal oxide
`semiconductors (hereinafter referred to as MT CMOS). In
`FIG. 1,
`the reference number 1 designates a two-input
`NAND gate, each of the reference numbers 2 and 3 denotes
`a p channel type metal oxide semiconductor field effect
`transistor (hereinafter referred to as a p MOS FET). Each of
`the reference numbers 4 and 5 indicates n channel type metal
`oxide semiconductor field effect
`transistors (hereinafter
`referred to as a n channel MOS FET). The absolute value of
`the threshold voltage of this p MOS FET is set to a low value
`and the absolute value of the threshold voltage of this n
`MOS FET is set to a high value. The reference number 6
`designates the power source, 7 denotes the ground power
`source. The reference number 8 indicates the p channel
`MOS FET connected between the power source 6 and a
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`power source line 12 as a hypothetical power source line.
`This p channel MOS FET 8 becomes active when a gate
`terminal of the P channel MOS FET 8 receives the control
`
`signal 9. The reference number 10 indicates the n channel
`MOS FET connected between the ground power source 7
`and the ground voltage line 13 that is a hypothetical ground
`line. This n channel MOS FET 10 becomes active when a
`
`gate terminal of the n channel MOS FET 10 receives the
`control signal 11. In this circuit shown in FIG. 1, it is formed
`so that the values of the threshold voltages of the p channel
`MOS FET 8 and the n channel MOS FET 10 are higher than
`the values of the threshold voltages of the p channel MOS
`FETs 2 and 3 and the n channel MOS FETs 4 and 5 forming
`the two-input NAND gate 1, respectively.
`FIG. 3 is a diagram showing a layout pattern of the low
`voltage operation circuit shown in FIG. 1 as the semicon-
`ductor integrated circuit device of the first embodiment
`according to the present invention. In FIG. 3, the reference
`number 21 designates an array section in which a plurality
`of MOS FETs are arranged in array form, 22 to 25 denote
`input/output circuit section in which input/output circuits are
`formed in peripheral regions in the array section 21. The
`reference number 27 indicates regions in which MOS FETs
`(high threshold voltage MOS FET) are formed in and each
`MOS FET in the regions 27 has a higher threshold voltage
`than the threshold voltage of each MOS FET formed in the
`array section 21. In the regions other than the regions 27 in
`the input/output circuit sections 22 to 25, input/output cir-
`cuits are formed.
`
`FIG. 4 is a diagram showing detailed layout patterns of
`the regions in which input/output circuits are formed in the
`semiconductor integrated circuit as the first embodiment
`shown in FIG. 3. In FIG. 4, the reference numbers 28 and 30
`designate signal pads, 29 indicates a power source pad, and
`31 to 33 denote lines as wiring connecting the signal pads 28
`and 30 and the power source pad 29 to the input/output
`circuits formed in the regions 34 and 35 and switch circuits
`formed in the region 7. In this case shown in FIG. 4, the
`input/output circuits are formed in the regions 34 and 35
`(namely, those regions 34 and 35 correspond to the regions
`other than the region 27 in the input/output forming regions
`22 to 25 shown in FIG. 3) in which the low threshold voltage
`MOS FETs are formed, and the switch circuits are formed in
`the region 27 in which the high threshold voltage MOS FET
`are formed.
`
`Further, FIG. 5 is a detailed circuit diagram showing the
`input/output circuit formed in the input/output forming
`region in the semiconductor integrated circuit of the first
`embodiment shown in FIG. 3. In FIG. 5,
`the reference
`number 36 designates an output buffer circuit, 37 denotes an
`input buffer circuit. The reference number 38 designates an
`output signal generated by internal circuits such as the
`two-input NAND gate 1 and the like, 39 indicates a control
`signal by which the output buffer circuit 36 enters the active
`state or the inactive state. The reference number 40 indicates
`
`an input signal to be transferred to the internal circuits, 41
`designates an input/output signal transferred to the signal
`pads 28 and 30.
`Next, a description will be given of the operation of the
`semiconductor integrated circuit device as the first embodi-
`ment.
`
`In the low voltage operation circuit shown in FIG. 1, when
`the two-input NAND gate 1 operates, the level of the control
`signal 9 is set to the low level, and the level of the control
`signal that is the inverted level of the control signal 9 is set
`to the high level. Thereby, both the p channel MOS FET 8
`and the n channel MOS FET 10 are ON and the level of the
`
`0012
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`0012
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`

`

`US 6,653,693 B1
`
`7
`hypothetical power source line 12 is risen up to the voltage
`level of the power source 6 and the level of the hypothetical
`ground line 13 is fallen into the voltage level of the ground
`7. As a result, the two-input NAND gate 1 performs the
`normal operation. In this case, because the value of the
`threshold voltage of each of the MOS FETs 2 to 5 is set to
`a low value,
`it
`is possible to operate the semiconductor
`integrated circuit of the first embodiment at a high speed
`even if the voltage level of the power source 6 is a low.
`When the two-input NAND gate 1 is not used, the level
`of the control signal 9 is set to the high level and the level
`of the control signal 11 is set to the low level. In this case,
`both the p channel MOS FET 8 and the n channel MOS FET
`10 become OFF. Thereby, both the hypothetical power
`source line 12 and the hypothetical ground line 13 are
`disconnected electrically from the power source 6 and the
`ground 7. Because both the absolute value of the threshold
`voltage of each of the p channel MOS FET 8 and the n
`channel MOS FET 10 is set to the high value rather than that
`of each of the MOS FETs 2 to 5, it is possible to suppress
`the magnitude of the leak current as small as possible.
`In general, in the region in which MOS FETs (in each
`MOS FET, a voltage between the gate and the source of this
`MOS FET is a lower value than the threshold voltage of this
`MOS FET) are formed, because the leak current flowing
`through the source and the drain is increased exponentially
`corresponding to the increasing of the gate voltage, it is
`possible to reduce the leak current when the two-input
`NAND gate 1 is not used by setting the different threshold
`voltages to the MOS FETs 2 to 5 and the MOS FETs 8 and
`10.
`
`In the explanation of the semiconductor integrated circuit
`device of the first embodiment described above, although
`the two-input NAND gate 1 is used as the circuit comprising
`MOS FETs having the low threshold voltage, it is possible
`to apply this concept of the present invention to other kinds
`of circuits having different hardware sizes to form other
`logical devices, memory devices, and semiconductor inte-
`grated circuit devices.
`FIG. 3 is the layout pattern of the low voltage operating
`circuit shown in FIG. 1 comprising gate arrays. In FIG. 3,
`the p channel MOS FET 8 and the n channel MOS FET 10
`having the higher threshold voltage forming the switching
`circuits are formed in the region 27, and the p channel MOS
`FETs 2 and 3 and the n channel MOS FETs 4 and 5 having
`the lower threshold voltage forming the two-input NAND
`gate 1 are formed in the array section 21.
`The voltages of the power source 6 and the ground 7, and
`the control signals 9 and 11 are provided to/from the array
`section 21 through the regions 22 to 25 in which the
`input/output circuits are formed.
`FIG. 4 is the diagram showing the layout pattern of the
`switch circuits and the input/output circuits formed in the
`input/output circuit forming regions 22 to 25.
`In general, the semiconductor integrated circuit device
`has the signal pads and the power source pads. Through the
`signal pads, various kinds of signals are transferred between
`the internal circuits and external circuits. The voltage and
`the ground voltage are provided to the internal circuits of the
`semiconductor integrated circuit device through the power
`source pads. In addition,
`the input/output circuit regions
`corresponding to the input/output pads are used for forming
`the input/output circuits. On the contrary, the input/output
`circuit regions corresponding to the power source pads are
`only used for connecting the power source lines and are not
`used for forming the input/output circuits comprising MOS
`FETS. Therefore it is possible to form the MOS FETs having
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`a high threshold voltage in those input/output circuit regions
`corresponding to the power source pads.
`In FIG. 4,
`the MOS FETs having the high threshold
`voltage are formed in the region corresponding to the power
`source pad 29. In this region, the p channel MOS FET 8 and
`the n channel MOS FET 10 having the high threshold
`voltage as the switch circuits are formed. The input/output
`circuit regions corresponding to the signal pads 28 and 30
`are the regions 34 and 35 in which the MOS FETs having the
`low threshold voltage are formed. In those regions 34 and
`35, the input/output circuits are formed.
`FIG. 5 is the detailed circuit diagram showing the input/
`output circuit shown in FIG. 4. when the signals from the
`semiconductor integrated circuit are transferred to other
`circuits, when receiving the control signal 39, the output
`buffer circuit 36 is activated, and thereby, the output signal
`38 is amplified by the MOS FET having a larger area formed
`in the output buffer 36 and transferred to the external
`devices, that are located in outside areas of the semicon-
`ductor integrated circuit device, as the input/output signal 41
`having a larger driving ability.
`Next, when an external signal generated by the outside
`devices of the semiconductor integrated circuit device is
`transferred to the internal circuits in the semiconductor
`
`integrated circuit device, the output buffer 36 receives the
`control signal 39, so that the output buffer 39 becomes
`inactive. Thereby, both two lines connected to the output
`buffer 36 are disconnected electrically. Therefore, the input/
`output signal 41 is amplified by the input buffer 40 without
`any influence from the output signal 38. Then, the input/
`output signal 41 amplified by the input buffer 37 is trans-
`ferred to the internal circuit in the semiconductor integrated
`circuit device. In the semiconductor integrated circuit device
`as the first embodiment, both the output buffer circuit 36 and
`the input buffer circuit 37 are formed by using the MOS
`FETs having the low threshold voltage.
`As described above, according to the semiconductor inte-
`grated circuit device as the first embodiment, it is possible
`to realize the semiconductor integrated circuit device includ-
`ing MT CMOSs capable of performing at a high speed and
`of achieving a low power consumption. In addition to this
`effect of the present invention, it may prevent to decrease the
`density of the layout pattern of the semiconductor integrated
`circuit device. On the contrary, the conventional semicon-
`ductor integrated circuit device shown in FIG. 2 has a lower
`density in the layout pattern because the reg