Trials@uspto.gov
`Tel: 571-272-7822
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`Paper 12
`Entered: March 6, 2020
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`v.
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`_______________
`
`IPR2019-01525
`Patent 6,239,614 B1
`_______________
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`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
`
`HAGY, Administrative Patent Judge.
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`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
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`Tel: 571-272-7822
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`Paper 12
`Entered: March 6, 2020
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`v.
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`_______________
`
`IPR2019-01525
`Patent 6,239,614 B1
`_______________
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`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
`
`HAGY, Administrative Patent Judge.
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
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`I. INTRODUCTION
`Advanced Micro Devices, Inc. (“Petitioner”)1 filed a Petition (Paper
`2, “Pet.”) to institute an inter partes review of claims 1–5 (the “challenged
`claims”) of U.S. Patent 6,239,614 B1 (Ex. 1001, the “’614 patent”). Aquila
`Innovations, Inc. (“Patent Owner”) filed a Preliminary Response (Paper 9,
`“Prelim. Resp.”). With authorization from the Board, Petitioner filed a
`Reply (Paper 10, “Reply”), and Patent Owner filed a Sur-reply (Paper 11,
`“Sur-reply”).
`Institution of an inter partes review is authorized by statute when “the
`information presented in the petition . . . and any response . . . shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a)
`(2012). A decision to institute under 35 U.S.C. § 314 may not institute on
`fewer than all claims challenged in the petition. SAS Inst., Inc. v. Iancu,
`138 S. Ct. 1348, 1359–60 (2018).
`After considering the evidence and arguments presented in the
`Petition, Preliminary Response, Reply, and Sur-reply, we determine
`Petitioner has demonstrated a reasonable likelihood that it would prevail in
`showing unpatentability of claims 1–5 of the ’614 patent, and we institute
`review on all challenged claims and on all grounds.
`
`
`1 Petitioner identifies itself and ATI Technologies ULC as the real parties-in-
`interest. Pet. 4.
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`A. Related Proceedings
`Petitioner states the ’614 patent has been asserted by Patent Owner
`
`against Nichia Corporation and Nichia America Corporation in Aquila
`Innovations Inc. v. Advanced Micro Devices, Inc., Case No. 1:18-cv-00554-
`LY, filed July 2, 2018, pending in the Western District of Texas. Pet. 4; see
`also Paper 5, 2.
`
`B. The ’614 Patent
`The ’614 patent was filed on April 1, 1999, and claims priority to a
`Japanese application filed on January 14, 1999. Ex. 1001, codes (22), (30).
`The ’614 patent relates to a layout for a semiconductor integrated circuit
`device including multi-threshold voltage metal oxide semiconductor
`(“MOS”) transistors (“MTCMOS”), which is capable of operating at a lower
`power supply voltage when active and with reduced leakage current during
`standby. Id. at code (57), 1:7–12. The ’614 patent also relates to the use of
`MOS decoupling capacitors to reduce voltage variations and time delays in
`MTCMOS devices. Id. at code (57), 4:59–5:9.
`By way of background, the ’614 patent describes the desirability of
`operating integrated circuit devices with a low threshold voltage to reduce
`power consumption. Id. at 1:14–21. Lowering the threshold voltage,
`however, increases leakage current of the MOS transistor during standby.
`Id. at 1:21–26. The ’614 patent describes a type of transistor—the
`MTCMOS transistor—that was known to address this problem. Id. at 1:26–
`32. The MTCMOS transistor is comprised of MOS transistors having a low
`threshold voltage, which allow reduced power consumption while
`maintaining operating speed, and standby power control MOS transistors
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`each having a high threshold voltage, which reduce leakage current during
`standby. Id. at 1:33–41.
`The ’614 patent states that the conventional layout for MTCMOS
`devices adopted “a standard cell system in which layout design is performed
`in units of a latch circuit such as a flip-flop circuit comprised of an inverter
`circuit, a master circuit and a slave circuit, and a logic circuit.” Id. at 1:50–
`55. The ’614 patent further notes that “[t]he layout design based on such a
`standard cell system has a problem in that since it is performed in respective
`circuit units, the period required to manufacture the MTCMOS becomes
`long.” Id. at 1:55–58. The ’614 patent purports to address this problem by
`“implement[ing] the layout of a semiconductor integrated circuit device by a
`gate array system, thereby shortening a manufacturing period thereof as
`compared with the conventional standard cell system.” Id. at 2:1–7.
`Figure 1 of the ’614 patent, reproduced below, illustrates the layout of
`MTCMOS transistors in a gate array:
`
`
`Figure 1 of the ’614 patent, reproduced above, is a layout showing an
`embodiment of the claimed invention. Id. at 2:49–50. In particular, Figure 1
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`illustrates unit cell array 1, in which unit cells 2 with low-threshold
`MOSFETs are shown in columns alternating with columns of unit cells 3
`with high-threshold MOSFETs. Id. at 3:7–16. Power switch 4 is placed
`around the unit cell array 1, and input/output circuits 5 are disposed there
`around. Id. at 3:16–19. Power switch 4 comprises a PMOS transistor and an
`NMOS transistor, each of which is a MOS transistor 7 that has a high
`threshold voltage for cutting off leakage current during standby. Id. at 3:19–
`22.
`Figure 3 of the ’614 patent, shown below, illustrates the unit cells in a
`
`MTCMOS integrated circuit device.
`
`
`Figure 3 of the ’614 patent, reproduced above, is a circuit diagram depicting
`one example of the unit cells shown in Figure 1 according to the claimed
`invention. Id. at 2:54–56. In particular, the MTCMOS device comprises
`(1) unit cells having low threshold voltage MOS transistors to form logic
`cells 20 connecting between two virtual power supply lines 13 and 14,
`(2) unit cells having high threshold voltage MOS transistors to form the DFF
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`(D flip flop) cell connecting between two power supply lines 11 and 12, and
`(3) high threshold PMOS and NMOS transistors 15, 16, 17, 18 to form the
`power switch. Id. at 3:7–45.
`
`As also shown above in Figure 3, the MTCMOS includes capacitors
`21 and 22 formed between power supply lines and virtual power supply
`lines. Id. at 3:36–39. With these capacitors, according to the ’614 patent,
`the MTCMOS is described as “capable of restraining variations in the values
`of voltages applied to a virtual power supply line and a virtual ground line
`and reducing a delay time when switching is done between logic circuits
`provided within an MTCMOS.” Id. at 2:6–13.
`C. Illustrative Claim
`Of the contested claims, claims 1 and 4 are independent, claims 2 and
`3 depend from claim 1, and claim 5 depends from claim 4. Claims 1 and 4,
`reproduced below, illustrate the claimed subject matter:
`1.
`A semiconductor integrated circuit device, comprising:
`a plurality of first unit cells each including a plurality of first
`MOS transistors, each of the first MOS transistors having
`a first threshold voltage;
`a plurality of second unit cells each including a plurality of
`second MOS transistors, each of the second MOS
`transistors having a second threshold voltage;
`a unit cell array comprised of said first and second unit cells
`laid in array form;
`a power switch disposed around said unit cell array and
`comprised of a plurality of third MOS transistors, each of
`the third MOS transistors having the second threshold
`voltage; and
`a plurality of input/output circuits disposed around said unit
`cell array.
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`4.
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`A semiconductor integrated circuit device comprising:
`a first power supply line supplied with a first power supply
`potential level;
`a second power supply line supplied with a second power
`supply potential level;
`a first virtual power supply line;
`a second virtual power supply line;
`a latch circuit connected between said first and second
`power supply lines;
`a logic circuit connected between said first power supply
`line and said second virtual power supply line;
`a first capacitor connected between said first power supply
`line and said second virtual power supply line; and
`a second capacitor connected between said second power
`supply line and said first virtual power supply line;
`wherein said latch circuit, said logic circuit and said first and
`second capacitors are constructed by connecting MOS
`transistors placed within unit cells in array form.
`
`D. Asserted Grounds of Unpatentability
`Petitioner asserts that the challenged claims are unpatentable under
`35 U.S.C. § 103(a)2 based on the following grounds (Pet. 4–6):
`
`
`2 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended several provisions of 35 U.S.C., including § 103.
`Because the ’614 patent has an effective filing date prior to the effective date
`of the applicable AIA amendments, we refer herein to the pre-AIA version
`of § 103.
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`Claims Challenged
`1–3
`1–3
`4, 5
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`35 U.S.C. §
`103(a)
`103(a)
`103(a)
`
`References/Basis
`Urano,3 Mutoh0214
`Mutoh,5 Mutoh021
`Douseki,6 Ramus7
`
`As further support, Petitioner offers the Declaration of Douglas R.
`Holberg Ph.D. Ex. 1003 (“Holberg Declaration”).
`
`II. DISCUSSION
`A. Principles of Law
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`
`
`3 Urano, Japanese Pat. App. H10–125878, published May 5, 1988 (Ex. 1008,
`“Urano”) (English translation).
`4 Mutoh et al., Japanese Pat. App. H08-018021A, published Jan. 19, 1996
`(Ex. 1013, “Mutoh021”) (English translation).
`5 S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada, “1-
`V Power Supply High-Speed Digital Circuit Technology with
`Multithreshold-Voltage CMOS,” IEEE J. SSC, vol. 30, no. 8, pp. 847–854
`(Aug. 1995) (Ex. 1005, “Mutoh”).
`6 Douseki et al., U.S. Pat. No. 5,486,774, filed Nov. 2, 1994, issued Jan. 23,
`1996 (Ex. 1010, “Douseki”).
`7 Ramus et al., U.S. Pat. No. 5,631,492, filed Apr. 15, 1996, issued May 20,
`1997 (Ex. 1011, “Ramus”).
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`(3) the level of ordinary skill in the art; and (4) when in evidence, objective
`evidence of nonobviousness.8 Graham v. John Deere Co., 383 U.S. 1,
`17–18 (1966).
`“In an [inter partes review], the petitioner has the burden from the
`onset to show with particularity why the patent it challenges is
`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the
`grounds for the challenge to each claim”)). This burden of persuasion never
`shifts to Patent Owner. See Dynamic Drinkware, LLC v. Nat’l Graphics,
`Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (discussing the burden of proof in
`inter partes review).
`B. Level of Ordinary Skill in the Art
`Relying on the testimony of Dr. Holberg, Petitioner describes the level
`of ordinary skill as follows:
`A person of ordinary skill in the art (“POSA”) at the time of the
`claimed invention would have a B.S. degree in Electrical
`Engineering or an equivalent field, as well as at least 3–5 years
`of academic or industry experience in semiconductor integrated
`circuit field, or comparable industry experience.
`Pet. 14–15 (citing Ex. 1003 ¶ 26).
`At this stage, Patent Owner does not propose an alternative
`assessment. To the extent necessary, and for purposes of this Decision, we
`accept the assessment offered by Petitioner as it is consistent with the ’614
`
`8 Patent Owner does not present arguments or evidence of such secondary
`considerations in its Preliminary Response. Therefore, secondary
`considerations do not constitute part of our analysis herein.
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`patent and the asserted prior art.
`C. Claim Construction
`In interpreting the claims of the ’614 patent, we “us[e] the same claim
`construction standard that would be used to construe the claim in a civil
`action under 35 U.S.C. [§] 282(b).” See 37 C.F.R. § 42.100(b) (2019). The
`claim construction standard includes construing claims in accordance with
`the ordinary and customary meaning of such claims as understood by one of
`ordinary skill in the art and the prosecution history pertaining to the patent.
`See id.; Phillips v. AWH Corp., 415 F.3d 1303, 1312–14 (Fed. Cir. 2005).
`1. “unit cells”
`Petitioner proposes we construe the term “unit cells,” which is recited
`in independent claims 1 and 4, as “semiconductor integrated circuits
`implemented by a gate array system, cannot be a conventional standard
`cell.” Pet. 16.
`As support for this construction, Petitioner first notes that the term
`“unit cells” is not a term of art nor is it defined in the ’614 specification. Id.
`Petitioner asserts, however, that the ’614 patent consistently distinguishes
`the claimed invention, which is implemented “by a gate array system,” from
`conventional MTCMOS circuits that “implemented a standard cell system.”
`Id. at 17 (citing Ex. 1001, 1:51–58, 2:3–7). For example, according to
`Petitioner, “[t]he ’614 patent explains that ‘for achieving the’ objective of a
`MTCMOS gate array system, ‘unit cells each including PMOS transistors
`and NMOS transistors’ are used in an array format instead of standard cells.”
`Id. (citing Ex. 1001, 2:14–26). Relying on the testimony of Dr. Holberg,
`Petitioner further asserts “gate arrays and standard cells are two distinct
`ways of designing and fabricating semiconductor circuits,” and the
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`ordinarily skilled artisan “reading the specification would understand that
`‘unit cells’ as recited in claims 1 and 4 are semiconductor integrated circuits
`implemented by a gate array system, and that they cannot be a conventional
`standard cell.” Id. at 18 (citing Ex. 1003 ¶¶ 74–78).
`Patent Owner criticizes Petitioner’s proposed construction as “a
`transparent and improper effort to import a limitation from the specification
`into the claims.” Prelim. Resp. 7. Patent Owner acknowledges that the
`Specification depicts the unit cells in a gate array configuration, but asserts
`“[w]hen the specification describes a single embodiment to enable the
`invention, this court will not limit broader claim language to that single
`application ‘unless the patentee has demonstrated a clear intention to limit
`the claim scope using “words or expressions of manifest exclusion or
`restriction.”’” Id. at 8 (quoting Abbott Labs. v. Sandoz, Inc., 566 F.3d 1282,
`1288 (Fed. Cir. 2009)). Patent Owner asserts the Specification does not
`include such words of “manifest exclusion or restriction,” but instead
`describes the examples in permissive language, stating that the “layout of the
`MTCMOS 10 can be implemented in accordance with a gate array system,”
`without requiring that it “must be implemented” with a gate array. Id. at 9
`(emphasis added) (citing Ex. 1001, 3:51–54).
`Although Patent Owner does not propose a construction of “unit cells”
`in this proceeding, Patent Owner has (according to Petitioner) proposed in
`the co-pending district court proceeding a construction of “unit cells” as
`“logical elements of which a unit cell array is comprised.” See Pet. 18.9
`
`
`9 The parties’ constructions as proposed in the district court are not part of
`the record before us, aside from Petitioner’s representations. Patent Owner
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`Petitioner asserts this construction “fails to provide clarity to the term, is
`inaccurate, and fails to account for the specification’s distinction between
`unit cells and standard cells.” Id.
`We determine that the parties’ dispute over whether “unit cells” are
`limited to those implemented by a gate array system, to the exclusion of
`standard cells, is not material to whether we will institute review. As
`Petitioner tacitly acknowledges, Petitioner’s proposed construction is
`actually narrower than the one Patent Owner has proposed in the district
`court proceeding. See Pet. 18. In addition, Petitioner relies on both
`constructions in its Petition, applying Patent Owner’s broader construction
`exclusively in two of the three grounds presented (see id. at 65 (Ground 2),
`77–78 (Ground 3)), and applying it alternatively for Ground 1 (id. at 42–45).
`According to our practice, if we institute on one ground, we will institute on
`all grounds.10 Therefore, although the proper construction of this term may
`be material to whether Petitioner ultimately succeeds in demonstrating
`unpatentability according to all three of its grounds, our institution decision
`does not depend on resolving this dispute. As our reviewing court has held,
`“only those terms need be construed that are in controversy, and only to the
`extent necessary to resolve the controversy.” See Vivid Techs., Inc. v. Am.
`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999); see also Nidec Motor
`
`
`does not, however, dispute Petitioner’s representation as to this term.
`10 See Consolidated Trial Practice Guide at 5 (Nov. 2019) (citing SAS
`Institute Inc. v. Iancu, 138 S. Ct. 1348, 1359–60 (2018); PGS Geophysical
`AS v. Iancu, 891 F.3d 1354, 1359–62 (Fed. Cir. 2018); Adidas AG v. Nike,
`Inc., 894 F.3d 1256, 1258, (Fed. Cir. 2018)), available at
`https://www.uspto.gov/sites/default/files/documents/tpgnov.pdf?MURL=.
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`Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed.
`Cir. 2017) (citing Vivid Techs. in the context of an inter partes review).
`Therefore, at this stage, we determine that the term “unit cells”
`includes “logical elements of which a unit cell array is comprised,” and we
`adopt that construction for purposes of this Decision. We do not determine
`at this stage whether the proper construction of this term excludes
`conventional standard cells, as Petitioner contends.
`We further note that our claim constructions in this Decision do not
`preclude the parties from arguing their proposed constructions of the claims
`during trial. Indeed, the parties are hereby given notice that claim
`construction, in general, is an issue to be addressed at trial. Claim
`construction will be determined at the close of all the evidence and after any
`hearing. The parties are expected to assert all their claim construction
`arguments and evidence in the Petition, Patent Owner’s Response,
`Petitioner’s Reply, or otherwise during trial, as permitted by our rules.
`2. “unit cell array”
`Claim 1 recites “a unit cell array comprised of said first and second
`unit cells laid in array form.” Petitioner proposes we construe “unit cell
`array” as “a plurality of said first and second unit cells laid in a regular
`arrangement or pattern.” Pet. 19. As support for this construction,
`Petitioner relies on a dictionary definition of “array” as meaning “a regular
`and imposing group or arrangement.” Id. (citing Merriam-Webster’s
`Collegiate Dictionary (10th ed. 2001) (Ex. 1037, 64)).
`Patent Owner criticizes Petitioner’s proposed construction as based on
`a “selectively edited non-technical dictionary” and as failing to state “that
`this definition is consistent with how a person of ordinary skill in the art
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`would understand the term, or explain why resort to extrinsic evidence is
`necessary.” Prelim. Resp. 9. In challenging Petitioner’s proposed
`construction (without proposing its own construction), Patent Owner
`apparently takes issue with Petitioner’s inclusion of a “regular arrangement
`or pattern.” This assumption is borne out by the fact that, as Petitioner
`represents (and Patent Owner does not dispute), Patent Owner has proposed
`in the co-pending district court litigation that “unit cell array” be construed
`as “an arrangement of first and second unit cells, not necessarily in a regular
`arrangement or pattern.” See Pet. 19 (emphasis added).
`We determine that Petitioner’s proposed construction is supported by
`the Specification, which describes a “unit cell array” as “comprised of the
`first and second unit cells laid in array form.” Ex. 1001 at 2:21–23. The
`Specification further refers to Figure 1 (reproduced below) as depicting unit
`cells 2 and 3 being “laid in array form” (id. at 3:17):
`
`
`Figure 1 of the ’614 patent, reproduced above, depicts a layout of an
`embodiment of the claimed invention. Id. at 2:49–50. Figure 1 shows an
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`arrangement of unit cells 2 and 3 in a regular pattern consisting of repeating
`rows and columns. The ’614 patent does not depict or describe any other
`arrangement of the unit cells or otherwise define “unit cell array.”
`
`At this stage, we determine Petitioner’s proposed construction of “unit
`cell array” is consistent with the Specification and is supported by
`Petitioner’s proffered dictionary definition, which is informative of the
`ordinary meaning of the term “array.” See Phillips, 415 F.3d at 1314 (noting
`that “[i]n some cases, the ordinary meaning of claim language as understood
`by a person of skill in the art may be readily apparent even to lay judges, and
`claim construction in such cases involves little more than the application of
`the widely accepted meaning of commonly understood words”). Patent
`Owner has not proposed an alternative construction at this stage.
`Therefore, at this stage, we determine the term “unit cell array”
`includes “a plurality of said first and second unit cells laid in a regular
`arrangement or pattern,” as proposed by Petitioner, and we adopt that
`construction for purposes of this Decision. As noted above, our construction
`of terms herein is not a final construction, and claim construction will be
`determined at the close of all the evidence and after any hearing. The parties
`are encouraged to further address the proper construction of this term to the
`extent they believe it is material to our final decision.
`Petitioner also provides constructions for several other terms. See Pet.
`19–24. Patent Owner does not address those proposed constructions. For
`purposes of this Decision, we determine that we need not provide an express
`construction for any other terms in the ’614 patent. See Nidec Motor Corp.,
`868 F.3d at 1017.
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`D. Ground 1: Obviousness of Claims 1–3 Over Urano and Mutoh021
`1. Overview of Urano (Ex. 1008)
`Urano is a Japanese Unexamined Patent Application that was
`published on May 5, 1998; accordingly, it is prior art under 35 U.S.C.
`§ 102(a). Pet. 6. Patent Owner does not dispute the prior-art status of
`Urano.
`Urano describes a semiconductor integrated circuit device, and
`specifically, a cell array that includes a MTCMOS circuit to achieve low
`voltage and high-speed operation. Ex. 1008, code (57). Urano’s integrated
`circuit device includes an array of “basic cells” to utilize logic functions,
`where the cells include components of an MTCMOS circuit having high-
`speed and low-voltage output. Id. ¶¶ 1, 29. Urano also teaches that a
`plurality of low-threshold MOSFETs can be provided along with high-
`threshold MOSFETs to form different types of basic cells used in a cell
`array. Id. ¶¶ 30, 38.
`Figure 25 of Urano, reproduced below, illustrates a layout of cells in a
`gate array format.
`
`
`Figure 25 of Urano, reproduced above, is a “diagram for a gate array”
`according to Urano’s invention. Id. ¶ 101. As shown in Figure 25, the gate
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`array include multiple first basic cells 31 having low-threshold MOSFETs,
`multiple second basic cells 39 having high-threshold MOSFETS, and
`multiple third basic cells 42 with high-threshold MOSFETs used as power
`switch cells. Id. ¶¶ 62, 75, 82, 85–87. Urano states “first basic cells 31 and
`second basic cells 39 are laid out on the chip 30, repeated in units of specific
`numbers of cells, and third basic cells 42 are arranged on the periphery
`thereof.” Id. ¶ 85.
`
`2. Overview of Mutoh021 (Ex. 1013)
`Mutoh021 is an Unexamined Japanese Application published on
`January 19, 1996, more than one year before the priority date of the ’614
`patent; accordingly, it is prior art under 35 U.S.C. § 102(b). Ex. 1013;
`Pet. 6. Patent Owner does not dispute the prior-art status of Mutoh021.
`Mutoh021 discloses a MTCMOS IC device configured in a gate array
`and, more specifically, a gate array-type IC compatible with CMOS circuits
`for low-voltage / high-speed operation, composed of a high threshold
`voltage transistor and a low threshold voltage transistor. Ex. 1013 ¶ 1.
`Mutoh021 teaches various layouts in which the high-threshold power
`switch transistors are located at different regions of the gate array. For
`example, Mutoh021 states that “a group of logic circuits is formed in the
`first basic cell, and a power supply control circuit is formed in the second
`basic cell to control the supply of power to the group of logic circuits,” with
`“the second basic cell being arranged adjacent to the cell array composed of
`the first basic cell, at any end vertically or horizontally, at both ends
`horizontally, at both ends vertically, at all ends vertically and horizontally,
`or inside [the cell array composed of] the first basic cell.” Id. ¶¶ 15–16.
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`Examples of the various layouts are selectively illustrated in Figures 1 and
`68 of Mutoh021.
`Figure 1 of Mutoh21, reproduced below, illustrates a first layout of
`the gate array.
`
`
`Figure 1 of Mutoh21, reproduced above, is a schematic diagram of LSI chip
`1 with a gate array integrated circuit. Id. ¶ 19. The array includes first basic
`cells 2 arranged in “matrix fashion” to form cell arrays 1A, 2B, and 2C. Id.
`¶¶ 3, 19. In each of cell arrays 2A, 2B, and 2C, cell columns (cell arrays)
`3A, 3B, 3C, and 3D consisting of second basic cells 3 are arranged next to
`each other. Id. ¶ 19. Input / output cells 4 are located at the periphery of the
`cell array to form an interface with outside components. Id. A power
`supply control circuit is formed in the second basic cell to control the supply
`of power to the group of logic circuits. Id. ¶ 16. The cell array composed of
`the second basic cell may be “arranged adjacent to the cell array composed
`of the first basic cell, at any end vertically or horizontally, at both ends
`
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`horizontally, at both ends vertically, at all ends vertically and horizontally,
`or inside the first basic cell.” Id. ¶ 15.
`Figures 6 and 8 of Mutoh021, reproduced below, illustrate second and
`third layouts of the gate array, respectively.
`
`
`
`Figures 6 and 8 of Mutoh021, reproduced above, depict circuit diagrams of
`different embodiments of the gate array. Id. ¶¶ 27, 30. In the second layout,
`shown in Figure 6, second basic cells 3A, 3D are located on the left and right
`ends. Id. ¶ 27. In the third layout, shown in Figure 8, second basic cells 3A,
`3D are located on the upper and lower ends. Id. ¶ 30.
`3. Analysis
`In Ground 1, Petitioner contends claims 1–3 are unpatentable under
`35 U.S.C. § 103(a) as obvious over the combination of Urano and
`Mutoh021. Pet. 34–59. We are persuaded that Petitioner has established a
`reasonable likelihood of prevailing on this ground.
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`a. Claim 1: “semiconductor integrated circuit device”
`(preamble)
`To the extent the preamble is limiting, Petitioner persuasively asserts
`Urano discloses a semiconductor integrated circuit device comprising a gate
`array of transistors arranged on a chip. Pet. 41 (citing Ex. 1008 ¶ 1). At this
`stage, Patent Owner does not present separate arguments pertaining to the
`preamble of claim 1.
`Based on the current record, for purposes of this Decision, we are
`persuaded that Petitioner has demonstrated sufficiently that Urano teaches
`the subject matter of the preamble of claim 1.
`b. Claim 1: “a plurality of first unit cells each including a
`plurality of first MOS transistors, each of the first MOS
`transistors having a first threshold voltage”
`“a plurality of second unit cells each including a plurality of
`second MOS transistors, each of the second MOS transistors
`having a second threshold voltage”
`Petitioner contends Urano discloses a plurality of first unit cells (e.g.,
`
`first basic cells 31), each including a plurality of first MOS transistors (e.g.,
`Q1–Q4) having a first threshold voltage (e.g., low). Pet. 42–44 (citing
`Ex. 1008 ¶ 85, Fig. 25). Petitioner also contends Urano discloses a plurality
`of second unit cells (e.g., basic cells 39) that each include MOS transistors
`(e.g., Q6, Q8) with a second threshold voltage (e.g., high). Id. at 45–46.
`Petitioner further contends Urano discloses the basic cells are laid out in a
`gate array. Id. at 42, 45 (citing Ex. 1008 ¶ 85). Petitioner also contends
`Urano discloses “that the MOS transistors can be implemented in a standard
`cell layout.” Id. at 44, 48 (citing Ex. 1008 ¶¶ 15–16, Fig. 42).
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`Patent Owner does not address the teachings of Urano with regard to
`these limitations, but argues the Petition is deficient because Petitioner
`allegedly fails to apply its own construction of “unit cells” when discussing
`Urano’s disclosure of these limitations. Prelim. Resp. 14–16; Sur-reply 1–2.
`The record does not support Patent Owner’s contention. As noted above,
`Petitioner proposes “unit cells” be construed as “semiconductor integrated
`circuits implemented by a gate array system, cannot be a conventional
`standard cell.” See supra, II.C.1. Petitioner applies this construction by
`contending that (1) Urano “is directed to a semiconductor IC device, and
`specifically, a gate array that includes a MTCMOS circuit to achieve low
`voltage and high-speed operation” (Pet. 25 (emphasis added); Reply 2); and
`(2) Urano’s gate array includes first and second unit cells (e.g., first and
`second basic cells, 31 and 39) laid out on a chip with third basic cells
`arranged on the periphery (Pet. 42, 45–46; Reply 1–3). It is apparent from
`the Petition that Petitioner is applying its proposed construction, even though
`Petitioner does not explicitly quote that construction at that point in its
`Petition. Thus, Patent Owner is incorrect in asserting that Petitioner fails to
`apply its own proposed construction.
`Petitioner also argues, alternatively, that if the claims are construed
`more broadly as including standard cells (as Patent Owner apparently
`contends), Urano also discloses implementing MOS transistors in a standard
`cell layout. Pet. 43–45; Reply 3. Contrary to Patent Owner’s contention,
`Petitioner’s reliance on an alternative construction apparently advocated by
`Patent Owner in related litigation is not improper. See Prelim. Resp. 21;
`Sur-reply 3–4. Petitioner complies with our rules by identifying claim
`constructions it proposes as the basis for requesting review of the challenged
`
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`claims, and such identification includes presenting an alternative
`construction based on a claim construction proposed by a patent owner in a
`related district court proceeding. See Western Digital Corp. v. SPEX Techs.
`Inc., IPR2018-00084, 2018 WL 1990268 at *5 (PTAB April 25, 2018)
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