United States Patent 15
`5,048,019
`(11) Patent Number:
`145] Date of Patent:
`Sep. 10, 1991
`Albertsen
`
`(54] METHOD OFTESTING A READ-ONLY
`MEMORY AND DEVICE FOR
`PERFORMING THE METHOD
`
`[75]
`
`Inventor: Hans-Gerd Albertsen, Hamburg,
`Fed. Rep. of Germany
`
`[73] Assignee: U.S. Philips Corporation, New York,
`N.Y.
`
`{21] Appl. No.: 366,571
`
`[22] Filed:
`
`Jun. 15, 1989
`
`Foreign Application Priority Data
`[30]
`Jun. 18, 1988 [DE]
`Fed. Rep. of Germany ..... 38207281
`
`Int. Clo oe GO6F 11/00; G11C 29/00
`(51)
`[52] U.S. Ch. ee ceeeetseeerees 371/21.1; 371/16.1;
`,
`371/16.2
`[58] Field of Search .................. 371/16.1, 16.2, 21.1;
`364/200 MS File, 900 MS File
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`6/1982 Bourgois et al. ....... eee 371/16.1
`4,334,307
`7/1982 Hosaka et al. 0. 371/161
`4,339,801
`6/1984 Bhaskar et al...
`eee 371/16.2
`4,455,654
`4,622,647 11/1986 Sagnard et al. «oe 371/16,2
`
`9/1987 PHIIEpS ceecsscssecsssseceosee 371/16.2
`4,691,316
`
` wv 369/200
`4,777,586 10/1988 Matsubara et al.
`.
`
`wee 3T1/16.2
`4,868,822
`9/1989 Scott et al...
`6/1990 Eckard et ale cecccscssseseuen 371/16.2
`4,933,941
`
`Primary Examiner—Charles E. Atkinson
`Attorney, Agent, or Firm—Anne E.Barschall
`
`ABSTRACT
`(57]
`Microcontrollers generally comprise, in addition to the
`actual processor, a program memory which is con-
`structed as a read-only memory. In order to enable
`testing of the contents of the program me “ory without
`making these contentsalso available to th: environment
`of the microcontroller, the reference data of the pro-
`gram are externally supplied and the comparison is
`performed inside the microcontroller. In accordance
`with the invention this test is preferably performed as a
`small
`test program which is preferably stored in an
`additional read-only memory in the microcontroller
`which operates in the test mode and which performs
`this test. Consequently, except for the memoryfor the
`test program,
`this test program requires hardly any
`additional hardware.
`
`14 Claims, 2 Drawing Sheets
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`1
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` HIORO-CONTROLLER
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`1
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`APPLE 1022
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`1
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`APPLE 1022
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`

`

`U.S. Patent
`
`Sep. 10, 1991
`
`Sheet 1 of 2
`
`5,048,019
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`S a
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`1
`Df
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`MICRO-CONTROLLER
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`PROCESSOR
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`REG
`pS
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`2
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`U.S. Patent
`
`Sep. 10, 1991
`
`Sheet 2 of 2
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`5,048,019
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`°
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`}..3
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`_}-~-32
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`START COUNTER
`
`INIT ROM ADDRESS
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`ROM ADDRESS
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`WRITE TEST DATA
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`INCREMENT
`ROM ADDRESS
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`ZERO ACCUMULATOR REG:
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`ADDRESS OF ROM?x
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`-
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`44
`REGISTER ERROR
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`N
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`ROM
`DATA=TEST
`DATA
`9
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`CONTINUE
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`REACHED HIGHEST
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`Y
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`47
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`ERROR
`REGISTERED
`48
`Ty
`49
`Fig.2
`po CesTOK|
`ROM CONTAINS ERRORS
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`Y
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`|
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`3
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`1
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`5,048,019
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`METHODOF TESTING A READ-ONLY MEMORY
`AND DEVICE FOR PERFORMING THE METHOD
`
`2
`Thus, only a small additional memorywill be re-
`quired for the test program which need comprise only
`few instructions, and for the remainder of the execution
`of the test use is made exclusively of elements of the
`processor or the integrated circuit which have already
`been. provided for normal operation. As a result, with
`the exception of the additional test program memory,
`substantially no modifications are required for perform-
`ing the test in the integrated circuit; additional connec-
`tions, notably for the error message, are not required
`either.
`In principleit is sufficient to obtain information con-
`cerning the correctness of the contents of the read-only
`memory or whether an error has occurred. For many
`purposes, for example for correction, if any, of the man-
`ufacturing process, however,it is also advantageous to
`knowwhether many errors are present in the contents
`of the read-only memory. In a version of the method in
`accordance with the invention, therefore, each error
`message occurring is temporarily stored and at the end
`of the test program a message concerning the numberof
`error messagesis output to the environment. This num-
`ber of error messages can again be determined, stored
`and output merely by way of program steps of the pro-
`cessor, without additional hardware being required.
`A device for performing the method in accordance
`with the invention, comprising an integrated circuit
`which comprises a processor having an arithmetic unit
`and at least one storage register and one read-only mem-
`ory as well as a number of external connections, at least
`one of which is connected to a test device supplying test
`data, is characterized in that the integrated circuit com-
`prises a test program memory for storing control in-
`structions of a test program in that, after having been
`switched to the test mode, the processor reads control
`instructions from the test program memoryand succes-
`sively reads, under the control of these control instruc-
`tions, the data from the read-only memoryand applies
`these data, together with the test data supplied, to the
`arithmetic unit for comparison, and in that in the case of
`a control signal indicating non-correspondence of the
`supplied data the arithmetic unit modifies the contents
`of the storage register with respect to a predetermined
`initial state and applies, at the end of the test program.
`the contents of the storage register to a connection
`which acts as a data output during normal operation of
`the integrated circuit.
`In an embodimentofthe device in accordance with
`the invention the processor increments the contents of
`the storage register, the contents being a binary number,
`by one unit in response to each control signal from the
`arithmetic unit. This can be realized by way of appro-
`‘priate instructions in the test program.
`In order to minimize the modification of customary
`microcontrollers required for performing the test of the
`ROM contents in accordance with the invention,
`in a
`further embodiment of the invention the read-only
`memory and the test program memory are connected to
`the processor via a switch which is switched in depen-
`dence on the test mode and on the progress of the test
`program. Thus, the processor can be controlled succes-
`sively by the test program memory and the read-only
`memory as the actual program memory. The switch
`consists of, for example the bus switches alreadypresent
`at the output of the memory.
`The test program memory mayberealized in various
`ways. Preferably, the test program memoryis a read-
`only memory. The contents thereof are then defined,
`
`BACKGROUNDOF THE INVENTION
`1. Field of the Invention
`Theinvention relates to a method of testing the con-
`tents of a read-only memoryin an, integrated circuit
`which also comprises a processor which is controlled
`by the contents of the read-only memory and also com-
`prises an arithmetic unit and a storage register. The
`processor is connected to external connections of the
`integrated circuit and is switchable to a test mode in
`which the contents of the read-only memory in the
`integrated circuit are compared with externally sup-
`plied test data, an error message is generated in the case
`of non-correspondence. The invention also relates to a
`device for performing the method.
`2. Prior Art
`A method of this kind and an appropriate device are ~
`known from U.S. Pat. No. 4,777,586. The program
`stored in the read-only memoryis often developed by
`the customer at substantial expense, possibly with the
`assistance of the manufacturer of the microcontroller,
`so that this program represents a substantial value. In
`order to ensure that a third party cannot acquire such a
`microcontroller and read the contents of the read-only
`memoryin order to build or program microcontrollers
`so that said third party would save the expenditure for
`the development of the program, testing of the contents
`of the read-only memory must be possible without these
`contents being directly detectable from the outside.
`In accordance with said U.S. Pat. No. 4,777,586this is
`realized in that the contents of the read-only memory
`are read by meansof a separately generated clock signal
`in order to be applied to a separate comparator which
`receives externally applied test data upon inversion of
`said clock signal. The occurrence of errors is stored and
`output to the environment, via a separate output,after a
`predetermined numberof test steps. A separate counter
`is required for counting-this numberoftest steps. The
`comparator is provided with registers for the intermedi-
`ate storage of the data read from the read-only memory
`and thetest data. Thus, a numberof additional elements
`are required for testing the contents of the read-only
`memory, which elements require an additional surface
`area on the integrated circuit.
`SUMMARYOF THE INVENTION
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`Therefore, it is an object of the invention to provide
`a method ofthe kind set forth which enables the testing
`of the contents of the read-only memory in the inte-
`grated circuit to be performed with a minimum number
`of modifications, i.e. with a minimum amount of hard-
`ware.
`in accordance with the invention
`To achieve this,
`there is provided a test program whichis stored in the
`processor and whichis activated in the test mode ofthe
`processor. Upon execution ofsaid test program bythe
`processor the contents of the read-only memory are
`successively read and applied, together with the corre-
`sponding, externally supplied test data, to the arithmetic
`unit for comparison. Any error message which occursis
`stored in the storage register and is output only at the
`end of the test program via a connection which acts as
`a data connection during normal operation of the pro-
`cessor.
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`BRIEF DESCRIPTION OF THE DRAWING
`Embodiments in accordance with the invention will
`be described in detail hereinafter with reference to the
`drawing. Therein:
`FIG. 1 shows a diagrammatic block diagram of the
`essential parts of a device in accordance with the inven-
`tion,
`FIG. 2 showsa flowchart illustrating a possible exe-
`cution of the method in accordance with the invention.
`
`3
`4
`like the contents of the read-only memoryfor the pro-
`The switch 8 maybe constructed as a multiplexer or
`gram, during the manufacture of the integrated circuit
`be formed by bus data switches customarily connected
`and cannot be abusively modified.
`behind the outputs of the two memories 4 and 6 andis
`It may also be that the contents of the test program
`controlled, via the lead 11, by a test control circuit 10
`which controls the test mode in the microcontroller 1
`memory includeerrors, so that an error in the contents
`of the read-only memory can becomeapparent for the
`and whichitself is influenced by the CPU 2 via the lead
`program, even though it
`is actually correct and the
`13. Suchatest control circuit 10 is in any case provided
`microcontroller is, therefore operational, because the
`for testing the integrated circuit 1, independent of the
`test program is not used during normal operation.
`described testing of the contents of the ROM 4.
`Therefore, the contents of the test program memoryare
`For test purposes the microcontroller 1 is connected
`preferably accessible from outside the integrated cir-
`to a test device 22 via the already present input/output
`cuit. Thus, first the contents of the test program mem-
`circuits 18 and 20. The input/output circuits 18 and 20
`ory are then tested, which can be customarily done by
`comprise driver circuits for outgoing leads and receiver
`way of a comparison outside the integrated circuit be-
`circuits for incoming leads, which circuits are at least
`cause the contents of the test program memoryare of no
`partly controllable or switchable. This holds good nota-
`significance to third parties. It is only when the test
`bly for the input/output circuits 18 via which data
`program is correct that the actual testing of the read-
`words can be exchanged with externally connected
`devices, 1.e. in this case also with the test device 22. In
`only memoryfor the program can be performed,so that
`an error message then occurring can in any case be
`the device 18 the outgoing data leads are often associ-
`attributed to an error in the contents of the program
`ated with a register so that these data need be only
`memory.
`briefly generated by the processor 2 and remain exter-
`nally available for a prolonged period of time.
`In order to perform the test, the test device 22 trans-
`mits, via the lead 27 which may actually comprise a
`plurality of leads, a signal for adjusting the test mode.
`which signal is applied to the test control circuit 10 via
`the input/output circuit 20 and the lead 21. Beforethat,
`the test device 22 as well as the microcontroller 1 have
`been set to an initial state by a reset signal (not shown).
`The test control circuit 10 then sets, via the lead 11, the
`switch 8 to the position shown,
`thus transferring the
`first test construction from the test program memory6,
`DETAILED DESCRIPTION OF THE
`via the bus 3, to the processor 2 in which it is stored, for
`PREFERRED EMBODIMENT
`example in an instruction register (not shown). Subse-
`FIG. 1 shows a microcontroller 1 which is con-
`quently, further instructions maybe given, if any, which
`structed as a monolithic integrated circuit and which is
`set
`the processor 2 to a desired state. Instead, or in
`connected to a test device 22. Only the elements of the
`addition thereto, the processor 2 may also be set to the
`test mode via a connection 9.
`microcontroller 1 which are important for the follow-
`ing description are shown; other elements having been
`Subsequently,
`the test control circuit 10 briefly
`omitted for the sake ofclarity.
`switches over the switch 8 and applies the first data
`An essential part of the microcontroller 1 is formed
`word from the ROM 4,via the bus3, to the processor 2
`by the processor 2, also referred to as CPU, which
`in whichit is temporarily stored in the register 14 andis
`comprises a numberof circuits, only the circuits which
`present on an input of the ALU 12. Subsequently, the
`are important
`for
`the following description being
`switch 8 is switched back to the position shown and a
`shown.Firstof all there is the arithmetic and logic unit
`data word generated on the output lead 23 bythe test
`12 whichis generally referred to as ALU. Thereis also
`device 22 and corresponding to the first correct data
`showna register 14 whose output is connected to a data
`word in the ROM4is applied to the other input of the
`input of the ALU,the other input of the ALU 12 and
`ALU 12 via the input/output circuit 18 and the bus 3,
`the input of the register being connected to aninternal
`after which the two data words are compared, for ex-
`bus 3 (diagrammatically shown). A control output 17 of
`ample by adjusting the ALU for a subtraction or a logic
`the ALU 12, carrying a signal when the result of the
`comparison function,
`if present. On the lead 17 it
`is
`logic operation performed in the ALU 12 is unequal to
`merely indicated whether correspondence or non-cor-
`zero, is connected to a further register 16 via program-
`respondence has been detected. In the latter case,
`i.e.
`controlled switches (not shown).
`the case where the first word in the ROM 4 does not
`There is also provided a program memory 4 which
`correspond to the predetermined contents, the corre-
`contains the program to be executed by the microcon-
`spondingsignal ontheline 17 is written into the register
`troller during normal operation and which is con-
`structed as a read-only memory (ROM), as well as a
`After the comparison, or simultaneously therewith,
`further read-only memory 6 which contains the test
`the address for the ROM4is incremented by 1 and,
`60
`moreover, via the lead 13 the test control circuit 10
`program. The output 5 of the ROM 4 and the output 7
`of the test program memory 6 can be connected as
`receives a signal for the end of a test step; in response
`desired to the internal bus 3 via a switch 8, The address-
`thereto, the test control circuit 10 issues, via the lead 19,
`ing of the memories 4 and6is not separately shown and
`a synchronization signal whichis applied, via the input-
`customarily takes place by the processor 2 via address
`/output circuit 20 and the lead 29, to the test device 22
`leads in the bus 3. When the test program operates
`in which it enables the next comparison value on the
`without loops and branches, the test program memory6
`lead 23. Furthermore, via the lead 11 the switch 8 is
`could also be controlled by a separate address genera-
`again switched overto the position shown and the next
`tor, for example a counter.
`test step is performed in the same manner. Thus, the
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`Whatis claimed is:
`contents of the ROM4are successively compared with
`1, A method for testing the contents of a read-only
`corresponding comparison values from the test device
`memoryin an integrated circuit, the method comprising
`22. Whena plurality of error signals are then generated
`the steps of:
`on the lead 17, the contents of the register 16, being a
`(a) switching a processorof the integrated circuit toa
`binary number, can be incremented each time by one
`test mode, which processor is controlled by con-
`step corresponding control by the CPU 2.
`tents of the read-only memory;
`.
`Whenultimately the last, ie. the highest address, has
`(b) activating a test program stored in the processor
`been generated for the ROM 4,the test control circuit
`to control the processor rather than the contents;
`10 terminates the test and switches the switch 8 perma-
`(c) receiving externally supplied test data at the pro-
`nently to the position which is not shown, moreover,
`cessor via external connections of the integrated
`the contents of the register 16 whose output can be
`circuit;
`,
`customarily connected to the bus 3, are output on an
`(d) under control of the test program,
`output 25 via the input/output circuit 18. The contents
`(i) successively reading the contents;
`are customarily formed by a data word in which, for
`(ii) comparing the contents and the externally sup-
`example the values of given data bits indicate whether
`plied test data in an arithmetic unit of the proces-
`or not an error signal has occurred during the test.
`—
`sor;
`The execution of the test procedure described with
`(iii) supplying an error message in response to a
`reference to the device shown in FIG. 1 will beillus-
`negative comparison result;
`trated in a more general form with reference to the
`flowchart of FIG. 2.
`(iv) storing any error message in a storage register
`of the processor;
`/
`i.e. the microcon-
`In block 30 the entire assembly,
`(v) only outputting any stored error messageafter
`troller and the test device,
`is reset to a defined initial
`the end ofthe test program, via an external con-
`state. In block 31 a counterin the test device 22 which
`nection of the integrated circuit which is also a
`successively addresses the test data is set to theinitial
`data connection during normal operation of the
`position and in block 32 the address of the ROM isset
`processor,
`to the initial address. Moreover, in block 33 the ALU or
`whereby the contents are tested without the contents
`the accumulator register forming part thereofis set to
`zero.
`,
`being either supplied or accessible externally to the
`integrated circuit.
`Via an input/output circuit, in block 34 a signal is
`2. The method of claim 1 wherein:
`generated which triggers the test device to apply the
`next test data to the microcontroller. In block 35 the
`the outputting step further comprises outputting a
`message including the number of error messages;
`memorylocation in the ROM whichis addressed by the
`and
`processor is read and applied to the processor, and in
`the method further comprises the step of deleting any
`block 36 the test data produced by the test device are
`written. In block 37 the address for the ROM is incre-
`stored error messages after the outputting step.
`3. A device for testing a read-only memory in an
`mented by 1 in a preparatory fashion.
`In block 40 it is tested whether the data read from the
`integrated circuit, which integrated circuit comprises a
`microprocessor having an arithmetic unit; at least one
`ROM (block 38) correspondto the data supplied by the
`storage register: a plurality of external connections, at
`test device 22 (block 36). If this is not the case, in block
`least one of the external connections being for connect-
`44 an error register is set or an error counter is incre-
`ing to a test apparatus supplying test data, the device
`mented, after which the procedure continues with block
`comprising, within the integrated circuit:
`41; in the case of correspondenceof the two data, how-
`(a) a test program memoryfor storing control instruc-
`ever, the procedure immediately proceeds to the block
`tions of a test program;
`41 in which the signal on the output of the microcon-
`(b) means for switching the processor into a test
`troller, requesting data from the test device 22,is reset.
`mode, so that the processor reads control instruc-
`Finally, in block 42 it is tested whether the last address
`tions from the test program memory and succes-
`read is the highest address of the ROM,i.e. because of
`sively reads, under the control of these control
`the block 37 it is tested whether the next address sup-
`instructions, data from the read-only memory;
`plied by the processor is higher than the highest address
`(c) means for supplying the data from the read only-
`of the ROM. If this is not the case, the procedure. re-
`memory and the test data to the arithmetic unit for
`turns to the block 33 and is repeated again.
`When the last address of the ROM, however, has
`comparison;
`(d) means for supplying a control signal indicating
`been read,
`it
`is tested in block 47 whether the error
`non-correspondence ofthe test data and the data
`register has been set or whether the error counter has
`from the read-only memory;
`left its initial position. If this is not the case, a data word
`(e) means for modifying the contents of the storage
`is produced on an output in the described manner in
`register with respect to a predeterminedinitialstate
`order to indicate that the test has been completed and
`in response to the controlsignal;
`that no error has occurred; in the case of a set error
`(f) meansfor applying, at the end ofthe test program,
`register or an incremented counter in the block 49,
`the contents of the storage register to one of the
`however, another data word is generated on the output
`external connections which acts as a data output
`of the microcontroller in order to indicate that
`the
`during normal operation of the integrated circuit;
`ROM contains errors. This terminates the test proce-
`dure.
`whereby contents of the read-only memoryare tested
`without the contents being either supplied or accessible
`Instead of the test in the block 47, after the block 42
`externally to the integrated circuit.
`the contents of the error register or the error counter
`4. A device as claimed in claim 3, characterized in
`can also be unconditionally output to the environment,
`that for each control signal of the arithmetic unit (12)
`because the contents thereof directly indicate whether
`occurring the processor (2) increments the contents of
`or not an error has occurred.
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`the storage register (16), being a binary number, by one
`unit.
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`5,048,019
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`8
`switch (8) which is switched in dependence on the test
`mode and on the progressofthetest.
`10. A device as claimed in claim 9, characterized in
`that the test program memory(6) is a read-only mem-
`ory.
`11. The device of claim 9, wherein the contents of the
`test program memory are accessible from outside the
`integrated circuit.
`12. A device as claimed in claim 3, characterized in
`that the test program memory(6) is a read-only mem-
`ory.
`13. The device of claim 12, wherein the contents of
`the test program memoryare accessible from outside
`the integrated circuit.
`14. A device as claimed in claim 3, characterized in
`that the contents of the test program memory (6) are
`accessible from outside the integrated circuit (1).
`x
`*
`*
`*€
`*
`
`5. A device as claimed in claim 4, characterized in
`that the only read-only memory (4) and the test pro-
`gram memory (6) are connected to the processor(2) via
`a switch (8) whichis switched in dependenceon thetest
`mode and on the progress of the test.
`6. A device as claimed in claim §, characterized in
`that the test program memory(6) is a read-only mem-
`ory.
`7. A device as claimed in claim 4, characterized in
`that the test program memory (6)is a read-only mem-
`ory.
`8. A device as claimed in claim 4, characterized in
`that the contents of the test program memory (6) are
`accessible from outside the integrated circuit (1).
`9. A device as claimed in claim 3, characterized in
`that the read-only memory (4) and the test program
`memory (6) are connected to the processor (2) via a
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