U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`IN THE
`UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`AMAZON WEB SERVICES, INC.,
`AMAZON.COM, INC., and VADATA, INC.,
`Petitioners
`
`- vs. -
`
`SRC LABS, LLC, and
`SAINT REGIS MOHAWK TRIBE,
`
`_____________
`
`Patent Owners
`
`Patent No. 7,149,867
`Issued: December 12, 2006
`Inventors: Daniel Poznanovic, David E. Caliga, Jeffrey Hammes
`Title: SYSTEM AND METHOD OF ENHANCING EFFICIENCY
`AND UTLILZATION OF MEMORY BANDWITH
`IN RECONFIGURABLE HARDWARE
`Inter Partes Review No.
`
`DECLARATION OF BRAD L. HUTCHINGS, PH.D., IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,149,867
`
`_____________
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`October 19, 2018
`
`Petitioners Amazon
`Ex. 1002, Cover
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`
`VI.
`
`Page
`INTRODUCTION .......................................................................................... 1
`I.
`BACKGROUND AND QUALIFICATIONS ................................................ 1
`II.
`III. COMPENSATION AND RELATIONSHIP WITH PARTIES ..................... 2
`IV. MATERIALS CONSIDERED ....................................................................... 2
`BASIS OF OPINIONS FORMED ................................................................. 4
`V.
`A.
`LEGAL STANDARDS FOR CLAIM CONSTRUCTION ................. 4
`ANTICIPATION AND OBVIOUSNESS STANDARDS .................. 5
`B.
`LEVEL OF ORDINARY SKILL IN THE ART ................................. 6
`C.
`THE ’867 PATENT ........................................................................................ 8
`TECHNICAL OVERVIEW AND ALLEGED INVENTION OF
`A.
`THE ’867 PATENT.............................................................................. 8
`1.
`Reconfigurable Processors ......................................................... 8
`Description of the ’867 Patent ................................................... 9
`2.
`PRIORITY DATE .............................................................................. 12
`B.
`VII. CLAIM CONSTRUCTION ......................................................................... 12
`VIII. ANALYSIS OF THE TECHNICAL BASIS UNDERLYING THE
`GROUNDS OF REJECTION SET FORTH IN THE PETITION FOR
`INTER PARTES REVIEW ............................................................................ 14
`A.
`RELEVANT PRIOR ART REFERENCES ....................................... 15
`Lange ........................................................................................ 15
`1.
`Zhong ....................................................................................... 17
`2.
`REASONS THE SELECTED CLAIMS ARE
`UNPATENTABLE—LANGE ........................................................... 19
`1.
`Lange Anticipates and/or Renders Obvious Claim 1 of the
`’867 Patent ............................................................................... 19
`i.
`“A reconfigurable processor that instantiates an
`algorithm as hardware comprising” ............................... 19
`“a first memory having a first characteristic memory
`bandwidth and/or memory utilization; and” .................. 22
`
`B.
`
`ii.
`
`ii
`
`Petitioners Amazon
`Ex. 1002, p. ii
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`(Continued)
`
`iii.
`iv.
`
`v.
`
`vi.
`
`Page
`“a data prefetch unit coupled to the memory” ............... 24
`“wherein the data prefetch unit retrieves only
`computational data required by the algorithm from a
`second memory of second characteristic memory
`bandwidth and/or memory utilization and places the
`retrieved computational data in the first memory” ........ 26
`“wherein the data prefetch unit operates independent
`of and in parallel with logic blocks using the
`computional [sic] data” .................................................. 30
`“and wherein at least the first memory and data
`prefetch unit are configured to conform to needs of the
`algorithm” 32
`“and the data prefetch unit is configured to match
`format and location of data in the second memory.” .... 33
`Lange Anticipates and/or Renders Obvious Claim 3 of the
`’867 Patent ............................................................................... 34
`i.
`“The reconfigurable processor of claim 1, wherein the
`data prefetch unit receives processed data from on-
`processor memory and writes the processed data to an
`external off-processor memory.” ................................... 34
`Lange Anticipates and/or Renders Obvious Claim 4 of the
`’867 Patent ............................................................................... 36
`i.
`“The reconfigurable processor of claim 1, wherein the
`data prefetch unit comprises at least one register from
`the reconfigurable processor.” ....................................... 36
`Lange Renders Obvious Claim 5 of the ’867 Patent ............... 38
`“The reconfigurable processor of claim 1, wherein the
`i.
`data prefetch unit is disassembled when another
`program is executed on the reconfigurable processor.” 38
`Lange Anticipates and/or Renders Obvious Claim 6 of the
`’867 Patent ............................................................................... 39
`i.
`“The reconfigurable processor of claim 1 wherein said
`second memory comprises a processor memory and
`said data prefetch unit is operative to retrieve data
`from a processor memory.” ........................................... 39
`
`vii.
`
`2.
`
`3.
`
`4.
`
`5.
`
`iii
`
`Petitioners Amazon
`Ex. 1002, p. iii
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`(Continued)
`
`Page
`
`6.
`
`7.
`
`8.
`
`9.
`
`10.
`
`Lange Anticipates and/or Renders Obvious Claim 7 of the
`’867 Patent ............................................................................... 40
`“The reconfigurable processor of claim 6 wherein said
`i.
`processor memory is a microprocessor memory.” ........ 40
`Lange Anticipates and/or Renders Obvious Claim 8 of the
`’867 Patent ............................................................................... 40
`i.
`“The reconfigurable processor of claim 6 wherein said
`processor memory is a reconfigurable processor
`memory.” 41
`Lange Anticipates and/or Renders Obvious Claim 9 of the
`’867 Patent ............................................................................... 41
`i.
`“A reconfigurable hardware system, comprising” ........ 41
`“a common memory; and” ............................................. 43
`ii.
`“one or more reconfigurable processors that can
`iii.
`instantiate an algorithm as hardware coupled to the
`common memory” ......................................................... 43
`“wherein at least one of the reconfigurable processors
`includes a data prefetch unit to read and write only
`data required for computations by the algorithm
`between the data prefetch unit and the common
`44
`memory”
`“wherein the data prefetch unit operates independent
`of and in parallel with logic blocks using the
`computational data” ....................................................... 44
`“and wherein the data prefetch unit is configured to
`conform to needs of the algorithm and match format
`and location of data in the common memory.” ............. 44
`Lange Anticipates and/or Renders Obvious Claim 11 of the
`’867 Patent ............................................................................... 44
`i.
`“The reconfigurable hardware system of claim 9,
`wherein the at least of the reconfigurable processors
`also includes a computational unit coupled to the data
`access unit.” 45
`Lange Anticipates and/or Renders Obvious Claim 12 of the
`’867 Patent ............................................................................... 46
`
`iv.
`
`v.
`
`vi.
`
`iv
`
`Petitioners Amazon
`Ex. 1002, p. iv
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`(Continued)
`
`Page
`
`11.
`
`12.
`
`13.
`
`i.
`
`ii.
`
`iii.
`
`iv.
`
`“The reconfigurable hardware system of claim 11,
`wherein the computational unit is supplied the data by
`the data access unit.” ..................................................... 46
`Lange Anticipates and/or Renders Obvious Claim 13 of the
`’867 Patent ............................................................................... 46
`i.
`“A method of transferring data comprising:
`transferring data between a memory and a data
`prefetch unit in a reconfigurable processor; and” ......... 47
`“transferring the data between a computational unit
`and the data access unit” ................................................ 47
`“wherein the computational unit and the data access
`unit, and the data prefetch unit are configured to
`conform to needs of an algorithm implemented on the
`computational unit and transfer only data necessary for
`computations by the computational unit” ...................... 48
`“and wherein the prefetch unit operates independent of
`and in parallel with the computational unit.” ................ 49
`Lange Anticipates and/or Renders Obvious Claim 14 of the
`’867 Patent ............................................................................... 49
`i.
`“The method of claim 13, wherein the data is written
`to the memory, said method comprising” ...................... 49
`“transferring the data from the computational unit to
`the data access unit; and” ............................................... 49
`“writing the data to the memory from the data prefetch
`unit.”
`50
`Lange Anticipates and/or Renders Obvious Claim 15 of the
`’867 Patent ............................................................................... 50
`i.
`“The method of claim 13, wherein the data is read
`from the memory, said method comprising” ................. 50
`“transferring only the data desired by the data prefetch
`unit as required by the computational unit from the
`memory to the data prefetch unit; and” ......................... 50
`“reading the data directly from the data prefetch unit to
`the computational unit through a data access unit.” ...... 51
`
`ii.
`
`iii.
`
`ii.
`
`iii.
`
`v
`
`Petitioners Amazon
`Ex. 1002, p. v
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`(Continued)
`
`14.
`
`15.
`
`16.
`
`C.
`
`D.
`
`Page
`Lange Anticipates and/or Renders Obvious Claim 16 of the
`’867 Patent ............................................................................... 51
`i.
`“The method of claim 15, wherein all the data
`transferred from the memory to the data prefetch unit
`is processed by the computational unit.” ....................... 51
`Lange Anticipates and/or Renders Obvious Claim 17 of the
`’867 Patent ............................................................................... 52
`i.
`“The method of claim 15, wherein the data is selected
`by the data prefetch unit based on an explicit request
`from the computational unit.” ........................................ 52
`Lange Anticipates and/or Renders Obvious Claim 18 of the
`’867 Patent ............................................................................... 53
`i.
`“The method of claim 13, wherein the data transferred
`between the memory and the data prefetch unit is not a
`complete cache line.” ..................................................... 53
`LANGE ANTICIPATES AND/OR RENDERS OBVIOUS CLAIM
`19 OF THE ’867 PATENT ................................................................ 54
`i.
`“The method of claim 13, wherein a memory
`controller coupled to the memory and the data prefetch
`unit, controls the transfer of the data between the
`memory and the data prefetch unit.” ............................. 54
`REASONS THE SELECTED CLAIMS ARE
`UNPATENTABLE—ZHONG .......................................................... 54
`1.
`Zhong Anticipates and/or Renders Obvious Claim 1 of the
`’867 Patent ............................................................................... 54
`i.
`“A reconfigurable processor that instantiates an
`algorithm as hardware comprising” ............................... 55
`“a first memory having a first characteristic memory
`bandwidth and/or memory utilization; and” .................. 57
`“a data prefetch unit coupled to the memory” ............... 59
`“wherein the data prefetch unit retrieves only
`computational data required by the algorithm from a
`second memory of second characteristic memory
`bandwidth and/or memory utilization and places the
`retrieved computational data in the first memory” ........ 61
`
`ii.
`
`iii.
`iv.
`
`vi
`
`Petitioners Amazon
`Ex. 1002, p. vi
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`(Continued)
`
`v.
`
`vi.
`
`Page
`“wherein the data prefetch unit operates independent
`of and in parallel with logic blocks using the
`computional [sic] data” .................................................. 64
`“and wherein at least the first memory and data
`prefetch unit are configured to conform to needs of the
`algorithm” 65
`“and the data prefetch unit is configured to match
`format and location of data in the second memory.” .... 67
`Zhong Anticipates and/or Renders Obvious Claim 4 of the
`’867 Patent ............................................................................... 68
`i.
`“The reconfigurable processor of claim 1, wherein the
`data prefetch unit comprises at least one register from
`the reconfigurable processor.” ....................................... 68
`Zhong Anticipates and/or Renders Obvious Claim 6 of the
`’867 Patent ............................................................................... 68
`i.
`“The reconfigurable processor of claim 1 wherein said
`second memory comprises a processor memory and
`said data prefetch unit is operative to retrieve data
`from a processor memory.” ........................................... 69
`Zhong Anticipates and/or Renders Obvious Claim 7 of the
`’867 Patent ............................................................................... 71
`i.
`“The reconfigurable processor of claim 6 wherein said
`processor memory is a microprocessor memory.” ........ 71
`Zhong Anticipates and/or Renders Obvious Claim 9 of the
`’867 Patent ............................................................................... 72
`i.
`“A reconfigurable hardware system, comprising” ........ 72
`“a common memory; and” ............................................. 72
`ii.
`“one or more reconfigurable processors that can
`iii.
`instantiate an algorithm as hardware coupled to the
`common memory” ......................................................... 73
`“wherein at least one of the reconfigurable processors
`includes a data prefetch unit to read and write only
`data required for computations by the algorithm
`between the data prefetch unit and the common
`73
`memory”
`
`vii.
`
`iv.
`
`2.
`
`3.
`
`4.
`
`5.
`
`vii
`
`Petitioners Amazon
`Ex. 1002, p. vii
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`TABLE OF CONTENTS
`(Continued)
`
`v.
`
`vi.
`
`Page
`“wherein the data prefetch unit operates independent
`of and in parallel with logic blocks using the
`computational data” ....................................................... 74
`“and wherein the data prefetch unit is configured to
`conform to needs of the algorithm and match format
`and location of data in the common memory.” ............. 74
`
`viii
`
`Petitioners Amazon
`Ex. 1002, p. viii
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`I, BRAD L. HUTCHINGS, PH.D., declare as follows:
`I.
`INTRODUCTION
`I have been asked by Petitioners Amazon Web Services, Inc., Ama-
`1.
`
`zon.com, Inc., and VADATA, Inc. (collectively, “Amazon” or “Petitioners”), to pro-
`
`vide my expert opinions in support of the above-captioned petition for inter partes
`
`review of U.S. Patent No. 7,149,867 (the “’867 patent”), challenging the patentabil-
`
`ity of claims 1, 3-9, and 11-19 (the “challenged claims”) of the ’867 patent.
`
`2.
`
`3.
`
`I currently hold the opinions set forth in this declaration.
`
`In summary, it is my opinion that the references cited below render ob-
`
`vious the challenged claims. My detailed opinions on the claims are set forth below.
`II.
`BACKGROUND AND QUALIFICATIONS
`4.
`I currently hold the position of professor in the department of Electrical
`
`and Computer Engineering at Brigham Young University (BYU) in Provo, Utah. I
`
`received a Bachelor of Science degree in Computer Science in 1984, a Master of
`
`Science degree in Computer Science in 1987, and a Ph.D. degree in Computer Sci-
`
`ence in 1992, all from the University of Utah. I have been a professor at BYU since
`
`1992. Since that time, I also established the Reconfigurable Computing Laboratory
`
`at BYU in 1993. In 1998, I was a visiting scholar at HP Labs in Bristol, England,
`
`where I was part of a group that designed and studied reconfigurable devices for
`
`portable appliances. From 2003 to 2007, I worked as a director at Tabula, an FPGA
`
`1
`
`Petitioners Amazon
`Ex. 1002, p. 1
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`design and manufacturing company that I helped to start. I have published exten-
`
`sively in the reconfigurable-computing community and regularly consult with the
`
`industry. I serve on the committees of many of the conferences related to reconfig-
`
`urable computing and FPGAs. My research interests include programmable devices
`
`and architectures, tool flows, debugging strategies, and parallel computation.
`
`5.
`
`I have over 25 years of experience working with and designing FPGAs.
`
`In that time, I have also taught numerous FPGA-related courses to both undergrad-
`
`uate and graduate students. I have published over 70 articles related to FPGA tech-
`
`nology and am a named inventor on over 60 patents related to FPGA devices and
`
`debugging of FPGA circuits. I have also served as an expert witness in patent-liti-
`
`gation matters related to FPGA technology.
`
`6. My professional background and technical qualifications are reflected
`
`in detail in my Curriculum Vitae, attached as Exhibit A.
`III. COMPENSATION AND RELATIONSHIP WITH PARTIES
`7.
`I am being compensated for my time at my standard rate of $500 per
`
`hour. This compensation is not contingent on my performance, the conclusions I
`
`reach in my analysis, the outcome of this matter, or any issues involved in or related
`
`to this matter.
`
`I have no financial interest in the Petitioners or any related parties.
`8.
`IV. MATERIALS CONSIDERED
`9.
`I have reviewed and considered, in preparation of this declaration, the
`
`2
`
`Petitioners Amazon
`Ex. 1002, p. 2
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`’867 patent (Ex. 1001) and its prosecution file history (Ex. 1010).
`
`10.
`
`I have also reviewed various additional publications as discussed
`
`herein, including the following references:
`
` Holger Lange & Andreas Koch, Memory Access Schemes for Configu-
`
`rable Processors, Field-Programmable Logic and Applications: The
`
`Roadmap to Reconfigurable Computing (2000), Ex. 1003.
`
` Peixin Zhong & Margaret Martonosi, Using Reconfigurable Hardware
`
`to Customize Memory Hierarchies (1996), Ex. 1004.
`
` Integrated Circuit Eng’g Corp., Memory 1997 (1997), Ex. 1005.
`
`11.
`
`I understand that the above references form the basis for the grounds
`
`for cancellation set forth in the Petition for inter partes review of the ’867 patent.
`
`Additionally, I am aware of information generally available to, and relied upon by,
`
`persons of ordinary skill in the art at the relevant times, including technical diction-
`
`aries and technical reference materials (including, for example, textbooks, manuals,
`
`technical papers, articles, and relevant technical standards); some of my statements
`
`below are expressly based on such awareness.
`
`12. Due to procedural limitations for inter partes reviews, the grounds of
`
`invalidity discussed herein are based solely on prior patents and other printed publi-
`
`cations. I understand that Petitioners reserve all rights to assert at a later time other
`
`grounds for invalidity not addressed herein, for instance failure of the application to
`
`3
`
`Petitioners Amazon
`Ex. 1002, p. 3
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`claim patentable subject matter under 35 U.S.C. § 101, failure to meet requirements
`
`under 35 U.S.C. § 112 (e.g., lack of written description support of the claims) and
`
`anticipation/obviousness under 35 U.S.C. §§ 102 and 103 not based solely on patents
`
`and printed publications (e.g., evidence of prior use of combinations of elements
`
`claimed in the ’867 patent). Thus, absence of discussion of such matters here should
`
`not be interpreted as indicating that there are no such additional grounds for invalid-
`
`ity of the ’867 patent.
`
`13.
`
`I reserve the right to supplement my opinions to address any infor-
`
`mation obtained, or positions taken, based on any new information that comes to
`
`light throughout this proceeding.
`V.
`BASIS OF OPINIONS FORMED
`A.
`Legal Standards for Claim Construction
`14. My understanding is that a primary step in determining validity of pa-
`
`tent claims is to properly construe the claims to determine claim scope and meaning.
`
`15.
`
`In an inter partes review proceeding, I understand that claims are to be
`
`given their broadest reasonable construction in light of the patent’s specification.
`
`See 37 C.F.R. § 42.100(b). In other forums, such as in federal courts, different
`
`standards of claim interpretation control, which are not applied by the PTO for inter
`
`partes review. Accordingly, any interpretation or construction of the challenged
`
`claims in this proceeding, either implicitly or explicitly, should not be viewed as
`
`4
`
`Petitioners Amazon
`Ex. 1002, p. 4
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`constituting, in whole or in part, Petitioners’ own interpretation or construction, ex-
`
`cept as regards to the broadest reasonable construction of the claims presented.
`B.
`Anticipation and Obviousness Standards
`16.
`I understand that “anticipation” is a question of fact and that for a
`
`reference to anticipate a claimed invention it must disclose each and every element
`
`set forth in the claim for that invention. I further understand that the requirement of
`
`strict identity between the claim and the reference is not met if a single element or
`
`limitation required by the claim is missing from the applied reference.
`
`17.
`
`It is further my understanding that a prior art reference is anticipatory
`
`only if it discloses each and every limitation of the claim (as properly construed) at
`
`issue. In other words, every limitation of a claim must identically appear in a single
`
`prior art reference for it to anticipate a claim.
`
`18.
`
`It is further my understanding that a claimed invention is unpatentable
`
`as “obvious” if the differences between the invention and the prior art are such that
`
`the subject matter of the claim as a whole would have been obvious, at the time the
`
`invention was made, to a person having ordinary skill in the art to which the subject
`
`matter pertains.
`
`19.
`
`It is my understanding that “obviousness” is a question of law based on
`
`underlying factual issues including (1) the scope and content of the prior art, (2) the
`
`differences between the prior art and the asserted claims, (3) the level of ordinary
`
`5
`
`Petitioners Amazon
`Ex. 1002, p. 5
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`skill in the pertinent art, and (4) the existence of secondary considerations such as
`
`commercial success, long-felt but unresolved needs, and failure of others.
`
`20.
`
`I understand that for a single reference or a combination of references
`
`to render obvious the claimed invention, a person of ordinary skill in the art must
`
`have been able to arrive at the claim by altering or combining the applied references.
`
`21.
`
`In an obviousness evaluation based on a combination of multiple prior
`
`art references, I understand that the prior art references themselves may provide a
`
`suggestion, motivation, or reason to combine, but other times the nexus linking two
`
`or more prior art references is simple common sense. I further understand that
`
`obviousness analysis recognizes that market demand, rather than scientific literature,
`
`often drives innovation, and that a motivation to combine references may be supplied
`
`by the direction of the marketplace.
`C.
`Level of Ordinary Skill in the Art
`22.
`It is my understanding that the ’867 patent is to be interpreted based on
`
`how it would be read by a person of “ordinary skill in the art” at the time of the
`
`effective filing date of the application. It is my understanding that factors such as
`
`the education level of those working in the field, the sophistication of the technology,
`
`the types of problems encountered in the art, the prior art solutions to those problems,
`
`and the speed at which innovations are made in the field may help establish the level
`
`of ordinary skill in the art.
`
`6
`
`Petitioners Amazon
`Ex. 1002, p. 6
`
`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`23.
`
`I am familiar with the technology at issue and the state of the art at the
`
`time the application leading to the ’867 patent was filed. I assume for purposes of
`
`this declaration that the effective filing date of the claims of the ’867 patent is no
`
`earlier than June 18, 2003.
`
`24.
`
`In my opinion, a person having ordinary skill in the art at the time of
`
`the alleged invention of the patents-in-suit would have had a bachelor’s degree in
`
`electrical engineering, computer engineering, or a related field, with two or three
`
`years of experience working with reconfigurable systems. With more education,
`
`such as additional graduate degrees and/or study, less experience is needed to attain
`
`the ordinary level of skill.
`
`25. Both now and at the time of the filing of the patents-in-suit, I possessed
`
`at least ordinary skill in the art. At the relevant time frame, I worked with, taught,
`
`and knew many individuals who would qualify as persons of ordinary skill in the art.
`
`As a result of my education and over twenty-five years of experience in reconfigu-
`
`rable computing, I am very familiar with the state of the art in the area to which the
`
`patents-in-suit relate.
`
`26.
`
`I am not a patent attorney and my opinions on claim construction are
`
`limited to what I believe a person of ordinary skill in the art would have understood
`
`the meaning of certain claim terms to be, based on the patent documents. I use the
`
`principles below, however, as a guide in formulating my opinions.
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`7
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`Petitioners Amazon
`Ex. 1002, p. 7
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`

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`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
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`VI. THE ’867 PATENT
`A.
`Technical Overview and Alleged Invention of the ’867 Patent
`1.
`Reconfigurable Processors
`27. A reconfigurable processor is a device that can be reconfigured to per-
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`form different computations. One type of reconfigurable processor is a field-pro-
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`grammable gate array (FPGA). FPGAs are circuits that include a set of configurable
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`logic blocks, also referred to as “CLBs” or simply “logic blocks.” The logic blocks
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`can each be configured to perform a logic function. For example, one logic block
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`can be first configured as an AND logic gate (a gate that outputs a value of true if its
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`two inputs are true), and then, for a different application, can be reconfigured as an
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`OR logic gate (a gate that outputs a value of true if either of its two inputs are true).
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`In more complex FPGAs, the logic blocks can be configured to perform more com-
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`plex functions. In most FPGAs, each logic block stores a table that says, for each
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`possible set of inputs, the signal that the logic block outputs. This table is referred
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`to as a look-up table or “LUT.”
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`28.
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`FPGAs also include reconfigurable interconnects, which are able to
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`connect the logic blocks together in different configurations. For example, in one
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`configuration, the output of a first logic block is connected to the input of a second
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`logic block. In another configuration, the output of the first logic block is no longer
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`connected to the second logic block, and is instead connected to its own input. The
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`8
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`Petitioners Amazon
`Ex. 1002, p. 8
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`

`

`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`FPGA can be reconfigured to perform different types of calculations by reprogram-
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`ming the logic blocks and reconfiguring the interconnects. For example, a set of
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`logic blocks on an FPGA can be programmed and connected in one configuration to
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`multiply two numbers, and these same logic blocks can be reprogrammed and con-
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`nected in a different configuration to divide two numbers. The number of logic
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`blocks used can vary based on the particular application. For example, programming
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`the FPGA to perform a more complex calculation, or handle larger numbers, requires
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`more blocks than programming the same FPGA to perform simpler calculations or
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`operate on smaller numbers.
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`29. Reconfigurable computing systems typically include a conventional,
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`non-reconfigurable microprocessor along with the reconfigurable FPGA. The mi-
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`croprocessor transmits instructions to the FPGA describing how to program the logic
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`blocks and how to configure the interconnects so that the FPGA can perform a spe-
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`cific computation.
`
`Description of the ’867 Patent
`2.
`The ’867 patent describes a system including a reconfigurable proces-
`
`30.
`
`sor, such as an FPGA, coupled to a “data prefetch unit.” Ex. 1001 at 3:64-4:10, 6:5-
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`11. The data prefetch unit retrieves from main memory data needed by the processor
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`and deposits it into memory within the reconfigurable processor. Id. at 3:64-4:10,
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`7:34-43.
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`9
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`Petitioners Amazon
`Ex. 1002, p. 9
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`

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`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
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`31.
`
`Figure 5 depicts an example reconfigurable processor.
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`32.
`
`The central block 300 is “a simple logic block” that includes computa-
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`tional functional units 301, control functional units (not shown), and data access
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`units 303. Id. at 7:25-28. Outside the central logic block, memory banks 305 and
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`block RAM 307 represent memory that resides on the reconfigurable processor, as
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`opposed to the “external memory” at the top of the diagram, which is located exter-
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`nal to the reconfigurable processor. Id. at 7:28-32.
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`33. Between the external memory and the on-chip memory are the heart of
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`the claimed invention: data prefetch units 501. Id. at 7:67-8:2. Their role, as shown
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`10
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`Petitioners Amazon
`Ex. 1002, p. 10
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`

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`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
`
`in Figure 5, is to transfer data from the external memory to the processor before the
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`computational logic instantiated on the processor requires it. Id. “[M]any types of
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`data prefetch units can be defined so that the prefetch hardware can be configured to
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`conform to the needs of the algorithms currently implemented by the computational
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`logic.” Id. at 7:49-53. And in certain embodiments, the data prefetch units com-
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`municate with an “intelligent memory controller” coupled to the external memory
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`so as to extract only the data required by the computational algorithm. See id. at 8:3-
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`21.
`
`34. According to the ’867 patent, the advantage of its system is that the
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`claimed data prefetch units can increase bandwidth efficiency and utilization. See,
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`e.g., id. at 8:22-25 (describing an embodiment that maximizes both bandwidth effi-
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`ciency and utilization). As defined in the ’867 patent, bandwidth efficiency is the
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`proportion of data transferred that is “contributory data,” or data that is actually used;
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`bandwidth utilization is the proportion of data bandwidth used to transfer contribu-
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`tory data. Id. at 5:51-57. Thus, for example, prefetching data before it is needed
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`purportedly increases bandwidth utilization “by allowing data transfer to continue
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`uninterrupted and in parallel with computation,” and fetching only data that is actu-
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`ally used purportedly increases bandwidth efficiency. See id. at 8:25-28, 8:39-41.
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`35. The ’867 patent includes 17 claims, three of which are independent
`
`(claims 1, 9, and 13). Representative claim 1 is a method claim directed to data
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`11
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`Petitioners Amazon
`Ex. 1002, p. 11
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`

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`U.S. Patent No. 7,149,867- Declaration of Brad L. Hutchings, Ph.D.
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`processing at a reconfigurable computer system:
`
`1. A reconfigurable processor that instantiates an algorithm as hardware comprising:
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`a data prefetch unit coupled to the memory, wherein the data prefetch
`unit retrieves only computational data required by the algorithm from a second
`memory of second characteristic