Petition for Inter Partes Review of U.S. Patent No. 7,149,867
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`Paper No. 1
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`IN THE
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`AMAZON WEB SERVICES, INC.,
`AMAZON.COM, INC., and VADATA, INC.,
`Petitioners
`
`- vs. -
`
`SRC LABS, LLC, and
`SAINT REGIS MOHAWK TRIBE,
`
`_____________
`Patent No. 7,149,867
`Issued: December 12, 2006
`Inventors: Daniel Poznanovic, David E. Caliga, Jeffrey Hammes
`Title: SYSTEM AND METHOD OF ENHANCING EFFICIENCY
`AND UTLILZATION OF MEMORY BANDWITH
`IN RECONFIGURABLE HARDWARE
`
`Inter Partes Review No.
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,149,867
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. §§ 42.1-.80, 42.100-.123
`_____________
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Patent Owners
`
`
`October 19, 2018
`
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`
`2.
`
`Page
`EXHIBIT LIST (37 C.F.R. § 42.63(e)) ...................................................................ix
`I.
`INTRODUCTION .......................................................................................... 1
`II.
`COMPLIANCE WITH REQUIREMENTS FOR A PETITION FOR
`INTER PARTES REVIEW .............................................................................. 1
`A. GROUNDS FOR STANDING (37 C.F.R. § 42.104(A)) .................... 1
`B.
`FEES FOR INTER PARTES REVIEW (37 C.F.R. § 42.15(A)) .......... 1
`C. MANDATORY NOTICES (37 C.F.R. § 42.8(B)) .............................. 1
`III. THRESHOLD FOR REVIEW (35 U.S.C. § 314(A)) .................................... 2
`IV.
`IDENTIFICATION OF CLAIMS BEING CHALLENGED ......................... 3
`V.
`LEVEL OF ORDINARY SKILL IN THE ART ............................................ 3
`VI. OVERVIEW OF THE ’867 PATENT ........................................................... 3
`VII. OVERVIEW OF THE PRIOR ART .............................................................. 8
`A.
`LANGE................................................................................................. 8
`B.
`ZHONG .............................................................................................. 10
`VIII. GROUND 1: CLAIMS 1, 3-9, AND 11-19 ARE ANTICIPATED OR
`RENDERED OBVIOUS BY LANGE. ........................................................ 13
`A.
`CLAIM 1 ............................................................................................ 13
`1.
`Lange discloses and/or renders obvious “[a] reconfigurable
`processor that instantiates an algorithm as hardware.” ........... 13
`Lange discloses and/or renders obvious “a first memory
`having a first characteristic memory bandwidth and/or
`memory utilization.” ................................................................ 15
`Lange discloses and/or renders obvious “a data prefetch unit
`coupled to the memory.” .......................................................... 17
`Lange discloses and/or renders obvious that “the data
`prefetch unit retrieves only computational data required by
`the algorithm from a second memory of second characteristic
`
`3.
`
`4.
`
`i
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`(Continued)
`
`5.
`
`6.
`
`7.
`
`Page
`memory bandwidth and/or memory utilization and places the
`retrieved computational data in the first memory.” ................. 20
`Lange discloses and/or renders obvious that “the data
`prefetch unit operates independent of and in parallel with
`logic blocks using the computional [sic] data.” ....................... 23
`Lange discloses “at least the first memory and data prefetch
`unit are configured to conform to needs of the algorithm.” .... 24
`Lange discloses and/or renders obvious “the data prefetch
`unit is configured to match format and location of data in the
`second memory.” ..................................................................... 25
`CLAIM 3 ............................................................................................ 26
`1.
`Lange discloses that “the data prefetch unit receives
`processed data from on-processor memory and writes the
`processed data to an external off-processor memory.” ........... 26
`CLAIM 4 ............................................................................................ 28
`1.
`Lange discloses “the data prefetch unit comprises at least one
`register from the reconfigurable processor.” ........................... 28
`CLAIM 5 ............................................................................................ 30
`1.
`Lange renders obvious that “the data prefetch unit is
`disassembled when another program is executed on the
`reconfigurable processor.” ....................................................... 30
`CLAIM 6 ............................................................................................ 31
`1.
`Lange discloses and/or renders obvious that “said second
`memory comprises a processor memory and said data
`prefetch unit is operative to retrieve data from a processor
`memory.” ................................................................................. 31
`CLAIM 7 ............................................................................................ 32
`1.
`Lange discloses and/or renders obvious that “said processor
`memory is a microprocessor memory.” ................................... 32
`CLAIM 8 ............................................................................................ 32
`
`B.
`
`C.
`
`D.
`
`E.
`
`F.
`
`G.
`
`
`
`ii
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`(Continued)
`
`H.
`
`I.
`
`J.
`
`K.
`
`1.
`
`4.
`
`Page
`Lange discloses and/or renders obvious that “said processor
`memory is a reconfigurable processor memory.” .................... 32
`CLAIM 9 ............................................................................................ 33
`1.
`Lange discloses “[a] reconfigurable hardware system.” ......... 33
`2.
`Lange discloses “a common memory.” ................................... 33
`3.
`Lange discloses and/or renders obvious “one or more
`reconfigurable processors that can instantiate an algorithm as
`hardware coupled to the common memory.”........................... 34
`Lange discloses and/or renders obvious “at least one of the
`reconfigurable processors includes a data prefetch unit to
`read and write only data required for computations by the
`algorithm between the data prefetch unit and the common
`memory.” ................................................................................. 34
`Lange discloses and/or renders obvious “the data prefetch
`unit operates independent of and in parallel with logic blocks
`using the computational data.” ................................................ 35
`Lange discloses and/or renders obvious “the data prefetch
`unit is configured to conform to needs of the algorithm and
`match format and location of data in the common memory.” . 35
`CLAIM 11 .......................................................................................... 35
`1.
`Lange discloses and/or renders obvious “the at least of [sic]
`the reconfigurable processors also includes a computational
`unit coupled to the data access unit.” ...................................... 35
`CLAIM 12 .......................................................................................... 37
`1.
`Lange discloses and/or renders obvious “the computational
`unit is supplied the data by the data access unit.” ................... 37
`CLAIM 13 .......................................................................................... 37
`1.
`Lange discloses and/or renders obvious “[a] method of
`transferring data comprising transferring data between a
`memory and a data prefetch unit in a reconfigurable
`processor.” ............................................................................... 37
`
`5.
`
`6.
`
`
`
`iii
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`(Continued)
`
`2.
`
`3.
`
`4.
`
`3.
`
`3.
`
`Page
`Lange discloses and/or renders obvious “transferring the data
`between a computational unit and the data access unit.” ........ 38
`Lange discloses and/or renders obvious “the computational
`unit and the data access unit, and the data prefetch unit are
`configured to conform to needs of an algorithm implemented
`on the computational unit and transfer only data necessary
`for computations by the computational unit.” ......................... 38
`Lange discloses and/or renders obvious “the prefetch unit
`operates independent of and in parallel with the
`computational unit.”................................................................. 39
`CLAIM 14 .......................................................................................... 39
`1.
`Lange discloses “the data is written to the memory.” ............. 39
`2.
`Lange discloses “transferring the data from the
`computational unit to the data access unit.” ............................ 39
`Lange discloses “writing the data to the memory from the
`data prefetch unit.” ................................................................... 40
`M. CLAIM 15 .......................................................................................... 40
`1.
`Lange discloses that “the data is read from the memory.” ...... 40
`2.
`Lange discloses and/or renders obvious “transferring only the
`data desired by the data prefetch unit as required by the
`computational unit from the memory to the data prefetch
`unit.” ......................................................................................... 40
`Lange renders obvious “reading the data directly from the
`data prefetch unit to the computational unit through a data
`access unit.” ............................................................................. 41
`CLAIM 16 .......................................................................................... 41
`1.
`Lange discloses and/or renders obvious “all the data
`transferred from the memory to the data prefetch unit is
`processed by the computational unit.” ..................................... 41
`CLAIM 17 .......................................................................................... 42
`
`L.
`
`N.
`
`O.
`
`
`
`iv
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`(Continued)
`
`1.
`
`P.
`
`Q.
`
`Page
`Lange discloses “the data is selected by the data prefetch unit
`based on an explicit request from the computational unit.” .... 42
`CLAIM 18 .......................................................................................... 42
`1.
`Lange renders obvious that “the data transferred between the
`memory and the data prefetch unit is not a complete cache
`line.” ......................................................................................... 42
`CLAIM 19 .......................................................................................... 43
`1.
`Lange renders obvious “a memory controller coupled to the
`memory and the data prefetch unit, controls the transfer of
`the data between the memory and the data prefetch unit.”...... 43
`IX. GROUND 2: CLAIMS 1, 4, 6, 7, AND 9 ARE RENDERED OBVIOUS
`BY ZHONG. ................................................................................................. 44
`A.
`CLAIM 1 ............................................................................................ 44
`1.
`Zhong discloses and/or renders obvious “[a] reconfigurable
`processor that instantiates an algorithm as hardware.” ........... 44
`Zhong discloses and/or renders obvious “a first memory
`having a first characteristic memory bandwidth and/or
`memory utilization.” ................................................................ 46
`Zhong renders obvious “a data prefetch unit coupled to the
`memory.” ................................................................................. 48
`Zhong discloses and/or renders obvious that “the data
`prefetch unit retrieves only computational data required by
`the algorithm from a second memory of second characteristic
`memory bandwidth and/or memory utilization and places the
`retrieved computational data in the first memory.” ................. 51
`Zhong renders obvious that “the data prefetch unit operates
`independent of and in parallel with logic blocks using the
`computional [sic] data.” ........................................................... 53
`Zhong discloses and/or renders obvious “at least the first
`memory and data prefetch unit are configured to conform to
`needs of the algorithm.” ........................................................... 54
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`
`
`v
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`(Continued)
`
`Page
`
`B.
`
`C.
`
`D.
`
`E.
`
`7.
`
`2.
`
`3.
`
`Zhong discloses and/or renders obvious “the data prefetch
`unit is configured to match format and location of data in the
`second memory.” ..................................................................... 55
`CLAIM 4 ............................................................................................ 56
`1.
`Zhong discloses “the data prefetch unit comprises at least
`one register from the reconfigurable processor.” .................... 56
`CLAIM 6 ............................................................................................ 57
`1.
`Zhong discloses “said second memory comprises a processor
`memory and said data prefetch unit is operative to retrieve
`data from a processor memory.” .............................................. 57
`CLAIM 7 ............................................................................................ 58
`1.
`Zhong discloses that “said processor memory is a
`microprocessor memory.” ........................................................ 58
`CLAIM 9 ............................................................................................ 59
`1.
`Zhong discloses and/or renders obvious “[a] reconfigurable
`hardware system.” .................................................................... 59
`Zhong discloses and/or renders obvious “a common
`memory.” ................................................................................. 60
`Zhong discloses and/or renders obvious “one or more
`reconfigurable processors that can instantiate an algorithm as
`hardware coupled to the common memory.”........................... 60
`Zhong discloses and/or renders obvious “at least one of the
`reconfigurable processors includes a data prefetch unit to
`read and write only data required for computations by the
`algorithm between the data prefetch unit and the common
`memory.” ................................................................................. 60
`Zhong discloses and/or renders obvious “the data prefetch
`unit operates independent of and in parallel with logic blocks
`using the computational data.” ................................................ 61
`
`4.
`
`5.
`
`
`
`vi
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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF CONTENTS
`(Continued)
`
`6.
`
`Zhong discloses and/or renders obvious “the data prefetch
`unit is configured to conform to needs of the algorithm and
`match format and location of data in the common memory.” . 61
`CONCLUSION ............................................................................................. 61
`
`Page
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`X.
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`vii
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Johnson Worldwide Assocs., Inc. v. Zebco Corp.,
`175 F.3d 985 (Fed. Cir. 1999) ...................................................................... 18, 50
`Saint Regis Mohawk Tribe v. Mylan Pharms. Inc.,
`896 F.3d 1322, 127 U.S.P.Q.2d 1281 (Fed. Cir. 2018) ........................................ 2
`SRC Labs, LLC v. Amazon Web Services, Inc.,
`No. 2:18-cv-00317 (W.D. Wash.) ........................................................................ 2
`Verizon Cal. Inc. v. Ronald A. Katz Tech. Licensing, L.P.,
`326 F. Supp. 2d 1060 (C.D. Cal. 2003) .................................................. 18, 19, 50
`Statutes
`35 U.S.C. § 311 .................................................................................................... 1, 61
`35 U.S.C. § 102 .................................................................................... 6, 8, 10, 21, 48
`35 U.S.C. § 103 ...................................................................................................... 3, 6
`35 U.S.C. § 112 ...................................................................................................... 6, 7
`35 U.S.C. § 314(A) .................................................................................................... 2
`Other Authorities
`37 C.F.R. § 42.8(b) .................................................................................................... 1
`37 C.F.R. § 42.15(a) ................................................................................................... 1
`37 C.F.R. § 42.100(b) ................................................................................................ 6
`37 C.F.R. § 42.101 ................................................................................................... 61
`37 C.F.R. § 42.104(a) ................................................................................................. 1
`37 C.F.R. § 42.104(b) ................................................................................................ 3
`
`
`viii
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`EXHIBIT LIST (37 C.F.R. § 42.63(e))
`
`Exhibit No.
`1001
`1002
`1003
`
`1004
`
`1005
`
`1006
`1007
`1008
`
`1009
`
`1010
`1011
`
`Description
`U.S. Patent No. 7,149,867 to Poznanovic et al.
`Declaration of Brad L. Hutchings, Ph.D.
`Holger Lange & Andreas Koch, Memory Access Schemes for
`Configurable Processors, Field-Programmable Logic and
`Applications: The Roadmap to Reconfigurable Computing
`(2000) (“Lange”)
`Peixin Zhong & Margaret Martonosi, Using Reconfigurable
`Hardware to Customize Memory Hierarchies (1996)
`(“Zhong”)
`Integrated Circuit Eng’g Corp., Memory 1997 (1997)
`(“Memory 1997”)
`Declaration of Rachel J. Watters regarding Lange Publication
`Declaration of Rachel J. Watters regarding Zhong Publication
`Certified copy of Zhong Publication, obtained from the
`Library of Congress
`Certified copy of Memory 1997 Publication, obtained from the
`Library of Congress
`Prosecution History of U.S. Patent No. 7,149,867
`Houghton Mifflin Co., Dictionary of Computer Words (1999)
`(excerpt)
`
`ix
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`I.
`
`INTRODUCTION
`Petitioners Amazon Web Services, Inc., Amazon.com, Inc., and VADATA,
`
`Inc. (collectively, “Amazon” or “Petitioners”) hereby request inter partes review
`
`under 35 U.S.C. § 311 of United States Patent No. 7,149,867 to Poznanovic et al.,
`
`titled “System and Method of Enhancing Efficiency and Utilization of Memory
`
`Bandwidth in Reconfigurable Hardware” (the “’867 patent”). Petitioners challenge
`
`claims 1, 3-9, and 11-19 of the ’867 patent. This petition demonstrates that there is
`
`a reasonable likelihood that Petitioners will prevail on at least one of the challenged
`
`claims based on prior art that the U.S. Patent and Trademark Office did not have
`
`before it during prosecution. The Patent Trial and Appeal Board (“Board”) should
`
`therefore institute review of the ’867 patent.
`
`II. COMPLIANCE WITH REQUIREMENTS FOR A PETITION FOR
`INTER PARTES REVIEW
`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioners certify that the ’867 patent is available for inter partes review and
`
`that the Petitioners are not barred or estopped from requesting inter partes review of
`
`the ’867 patent.
`
`Fees for Inter Partes Review (37 C.F.R. § 42.15(a))
`B.
`The Director is authorized to charge the fee specified by 37 C.F.R. § 42.15(a)
`
`to Deposit Account No. 19-2555.
`
`C. Mandatory Notices (37 C.F.R. § 42.8(b))
`Petitioners are the real parties-in-interest. No other party had access to the
`
`1
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`Petition, and no other party had any control over, or contributed to any funding of,
`
`the preparation or filing of this Petition.
`
`Patent Owners SRC Labs, LLC and Saint Regis Mohawk Tribe1 assert the
`
`’867 patent against Petitioners in a related case: SRC Labs, LLC v. Amazon Web
`
`Services, Inc., No. 2:18-cv-00317 (W.D. Wash.).
`
`Lead Counsel
`J. David Hadden, Reg. No. 40,629
`FENWICK & WEST LLP
`Silicon Valley Center
`801 California Street
`Mountain View, California 94041
`Tel: 650-335-7684
`Fax: 650-935-5200
`
`Back-Up Counsel
`Saina Shamilov, Reg. No. 48,266
`FENWICK & WEST LLP
`Silicon Valley Center
`801 California Street
`Mountain View, California 94041
`Tel: 650-335-7694
`Fax: 650-935-5200
`
`
`
`Service of any documents may be made to the postal mailing addresses above.
`
`Petitioners consent to electronic service at DHadden-PTAB@fenwick.com,
`
`SShamilov-PTAB@fenwick.com, and Amazon-SRCService@fenwick.com.
`
`III. THRESHOLD FOR REVIEW (35 U.S.C. § 314(A))
`It is reasonably likely that Petitioners will prevail on at least one of the claims
`
`challenged in this Petition because the request shows that the subject matter recited
`
`in claims 1, 3-9, and 11-19 of the ’867 patent is taught in prior art that is uniquely
`
`relevant and not redundant to any art considered during prosecution. Any motivation
`
`
`1 Saint Regis Mohawk Tribe is an owner of the ’867 patent, but “tribal sovereign
`immunity cannot be asserted in IPR.” Saint Regis Mohawk Tribe v. Mylan Pharms.
`Inc., 896 F.3d 1322, 1326-29, 127 U.S.P.Q.2d 1281 (Fed. Cir. 2018).
`
`
`
`2
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`to combine the prior art is provided herein as necessary.
`
`IV.
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`In accordance with 37 C.F.R. § 42.104(b), Petitioners challenge claims 1, 3-
`
`9, and 11-19 (the “challenged claims”) under 35 U.S.C. § 103 on the following
`
`grounds:
`
`Ground 1: Claims 1, 3-9, and 11-19 are rendered obvious by Holger Lange
`
`& Andreas Koch, Memory Access Schemes for Configurable Processors, Field-
`
`Programmable Logic and Applications: The Roadmap
`
`to Reconfigurable
`
`Computing (2000) (“Lange,” Ex. 1003).
`
`Ground 2: Claims 1, 4, 6, 7, and 9 are rendered obvious by Peixin Zhong &
`
`Margaret Martonosi, Using Reconfigurable Hardware to Customize Memory
`
`Hierarchies (1996) (“Zhong,” Ex. 1004).
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`A person having ordinary skill in the art at the time of the alleged invention
`
`would have had a bachelor’s degree in electrical engineering, computer engineering,
`
`or a related field, with two to three years of experience working with reconfigurable
`
`systems. Ex. 1002 at ¶ 24. With more education, such as additional graduate
`
`degrees or study, less experience is needed to attain the ordinary level of skill. Id.
`
`VI. OVERVIEW OF THE ’867 PATENT
`The ’867 patent was filed on June 16, 2004, and claims priority to provisional
`
`application no. 60/479,339, filed on June 18, 2003. As its title, “System and Method
`
`
`
`3
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`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`of Enhancing Efficiency and Utilization of Memory Bandwidth in Reconfigurable
`
`Hardware,” suggests, the patent describes a system for improving memory access in
`
`a reconfigurable-computing architecture, such as an FPGA processor. Ex. 1001 at
`
`3:64-4:10, 6:5-11. According to the specification, the claimed invention seeks to
`
`satisfy a need for “memory hierarchies that have data storage and retrieval
`
`characteristics that are optimized for actual programs executed by a processor” and
`
`thus “limit the overhead of a memory hierarchy without also reducing bandwidth
`
`efficiency and utilization.” Id. at 3:39-41, 3:57-60. It does so by employing a “data
`
`prefetch unit” to “fetch only the required data words from external memory” and
`
`deposit them “into the memory hierarchy within” the reconfigurable processor. Id.
`
`at 7:33-8:41.
`
`
`
`4
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`
`Figure 5,
`
`left,
`
`illustrates
`
`an
`
`exemplary system of the patent. The
`
`system includes a reconfigurable processor
`
`(e.g., an FPGA) which may include all of
`
`blocks 300, 301, 303, 305, and 501. The
`
`central block 300 is “a simple logic block”
`
`that may include computational functional
`
`units 301, control functional units (not
`
`shown), and data access units 303. Id. at
`
`7:25-28. These implement the “user-
`
`defined
`
`computational
`
`logic . . .
`
`constructed by programming an FPGA.” Id. at 6:15-18.
`
`The central logic block can read and write data stored on-chip on “memory
`
`device 305 or block RAM memory 307.” Id. at 7:28-32. Also attached to the
`
`reconfigurable processor is the external memory at the top of Figure 5. Between the
`
`external memory and the on-chip memory is the heart of the claimed invention: data
`
`prefetch units 501. Id. at 7:67-8:2. Their role, as described in the patent, is to transfer
`
`data from the external memory to on-chip memory more directly accessible to the
`
`processor before the computational logic instantiated on the processor requires it.
`
`Id. “[M]any types of data prefetch units can be defined so that the prefetch hardware
`
`
`
`5
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
`
`
`can be configured to conform to the needs of the algorithms currently implemented
`
`by the computational logic.” Id. at 7:49-53.
`
`The terms in the challenged claims are to be given their broadest reasonable
`
`interpretation, as understood by one of ordinary skill in the art and consistent with
`
`the disclosure. See 37 C.F.R. § 42.100(b). Because inter partes reviews are limited
`
`to grounds relating to 35 U.S.C. §§ 102 and 103, Petitioners will raise additional
`
`invalidity grounds in the related proceeding in the district court.
`
`The following claim constructions relevant to this petition were proposed by
`
`Petitioners and Patent Owners in the related proceeding identified above.
`
`Term
`
`Petitioners’ Proposed
`Constructions
`this
`“a data prefetch unit” No construction of
`phrase is necessary in light
`of the fact that a larger
`phrase (see below) must be
`construed.
`
`
`“a data prefetch unit
`coupled
`to
`the
`memory, wherein the
`data prefetch unit
`retrieves
`only
`
`Governed by pre-AIA 35
`U.S.C. § 112, para. 6.
`Indefinite under pre-AIA 35
`U.S.C. § 112.
`
`
`Patent Owners’ Proposed
`Constructions
`that
`functional unit
`“a
`retrieves
`computational
`data needed to complete the
`algorithm instantiated on
`the
`reconfigurable
`processor
`during
`processing”
`
`This term has its plain and
`ordinary meaning and need
`not be construed.
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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
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`
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`Patent Owners’ Proposed
`Constructions
`
`This term has its plain and
`ordinary meaning and need
`not be construed.
`
`Petitioners’ Proposed
`Constructions
`Structure: No
`disclosed
`structure
`
`Function: “retrieves only
`computational data required
`by the algorithm from a
`second memory of second
`characteristic
`memory
`bandwidth and/or memory
`utilization and places the
`retrieved computational data
`in the first memory”
`
`Indefinite under pre-AIA 35
`U.S.C. § 112.
`
`Term
`
`computational data
`required
`by
`the
`algorithm
`from a
`second memory of
`second characteristic
`memory bandwidth
`and/or
`memory
`utilization and places
`the
`retrieved
`computational data
`in the first memory”
`
`the first
`least
`“at
`memory and data
`prefetch unit
`are
`configured
`to
`conform to needs of
`the algorithm”
`
`
`
`
`As noted above, Petitioners identified two terms as indefinite in the district
`
`court litigation; the district court has not yet construed the claims. Accordingly,
`
`because indefiniteness cannot be raised in an inter partes review, for the purposes
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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
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`of this petition, Patent Owners’ proposed constructions for those terms should be
`
`used. Nothing herein constitutes a waiver of Petitioners’ positions with respect to
`
`indefiniteness or claim construction in the district court.
`
`VII. OVERVIEW OF THE PRIOR ART
`The concept of prefetching and caching data required for processing using
`
`reconfigurable compute units, as claimed in the ’867 patent, was known and
`
`described in printed publications before the priority date of the patent.
`
`A. Lange
`Lange is prior art to the ’867 patent under 35 U.S.C. § 102(a) and § 102(b).
`
`Lange was published by Springer-Verlag Berlin Heidelberg
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`in FIELD-
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`PROGRAMMABLE LOGIC AND APPLICATIONS: THE ROADMAP TO RECONFIGURABLE
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`COMPUTING (LECTURE NOTES IN COMPUTER SCIENCE, Vol. 1896), in conjunction
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`with the 10th International Conference on Field Programmable Logic (FPL) that
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`took place on August 27-30, 2000, in Villach, Austria, and it was publicly available
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`no later than November 2000. Ex. 1003 at 1; Ex. 1006 (librarian declaration
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`evidencing receipt, and cataloguing and availability to library patrons, by November
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`2000).
`
`Like the ’867 patent, Lange describes a system for improving memory access
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`in a reconfigurable-computing architecture. Ex. 1003 at 3. It too seeks to improve
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`the performance of “memory hierarchies” using “techniques such as pre-fetching
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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
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`and streaming.” Id. at 5. It describes a Memory Architecture for Reconfigurable
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`Computers (MARC architecture) that provides access to system memory through
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`“abstract front-end interfaces” called “ports,” such as “caching ports” and
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`“streaming ports.” Id. at 7. Using such ports, the reconfigurable chip (RC) can
`
`configure the MARC to “pre-fetch[]/cache[]” accesses to main memory to “reduce
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`the impact of high latencies.” Id.
`
`Figure 4 of Lange, right,
`
`depicts the MARC architecture.
`
`The
`
`computational
`
`logic
`
`instantiated on
`
`the RC
`
`is
`
`represented by the “User Logic”
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`block on the right side of the
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`diagram, which Lange also calls the “datapath.” Id. at 5; id. at 6, Fig. 4. On the left
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`and bottom are the external memories—off-chip DRAM, SRAM, and any memory
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`that may be accessible over an I/O bus—as well as hardware-specific back-ends. Id.
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`at 4-5, 7. Between the two is the MARC core, the “main controller and data
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`switchboard.” Id. at 7. And “[u]sing MARC, the datapath accesses memory
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`through” the caching and streaming ports labeled CachePort and StreamPort in the
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`figure. Id.
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`Much like the data prefetch units in the ’867 patent, the MARC core can be
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`Petition for Inter Partes Review of U.S. Patent No. 7,149,867
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`configured using the front-end ports to “pre-fetch[]” data required by the user logic.
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`Id. at 12. As Lange explains:
`
`Caching ports provide for efficient handling of irregular
`accesses. Streaming ports offer a non-unit stride access to
`regular data structures (such as matrices or images) and
`perform address generation automatically. In both cases,
`data is pre-fetched/cached to reduce the impact of high
`latencies (especially for transfers using the I/O bus).
`Id. at 7.2 Also like the patent, in Lange, the characteristics of pre-fetching—such as
`
`number of cache lines, cache-line length, the stride (or increment) of pre-fetching,
`
`the width of the data words pre-fetched, or the size of the pre-fetch buffer—can be
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`“adapted to the needs of the application.” Id. at 7-8 & Table 2 (listing settable
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`parameters). And by setting these parameters, the MARC core can be configured to
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`“pre-fetch only the precise amount of data required.” Id. at 8.
`
`Zhong
`B.
`Zhong is prior art to the ’867 patent under 35 U.S.C. § 102(a) and § 102(b).
`
`Zhong was published by Society of Photo-Optical Instrumentation Engineers (SPIE)
`
`in HIGH-SPEED COMPUTING, DIGITAL SIGNAL PROCESSING, AND FILTERING USING
`
`RECONFIGURABLE LOGIC (PROCEEDINGS OF SPIE, Vol. 2914), in conjunction with
`
`the SPIE meeting that took place on November 20-21, 1996, in Boston,
`
`
`2 Although Lange sometimes speaks in terms of the front-end ports themselves doing
`the prefetching, elsewhere it makes clear that the ports are “abstract front-end
`interfaces,” id. at 7, and Figure 4 shows that the streaming logic used for pre-fetching
`resides within the MARC core.
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`Petition