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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
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`AMAZON WEB SERVICES, INC.,
`AMAZON.COM, INC., and VADATA, INC.,
`Petitioners,
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`v.
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`SAINT REGIS MOHAWK TRIBE,
`Patent Owner.
`_____________
`
`Case IPR2019-00103
`Patent 7,149,867 B2
`_____________
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`PETITIONERS’ REQUEST FOR REHEARING UNDER 37 C.F.R. § 42.71
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`Pursuant to 37 C.F.R. § 42.71, Petitioners Amazon Web Services, Inc., Ama-
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`zon.com, Inc., and VADATA, Inc. respectfully request rehearing of the Board’s De-
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`cision Denying Institution of Inter Partes Review of U.S. Patent No. 7,149,867 (Pa-
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`per 22) (“Decision”) because the Board “misapprehended or overlooked” matters
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`addressed by the Petition and thus abused its discretion in denying institution. See
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`37 C.F.R. § 42.71(c) and (d).
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`All claims challenged in the Petition require a “data prefetch unit.” See Ex.
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`1001. The Board construed the term as:
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`“‘a functional unit that moves data between members of a
`memory hierarchy. The movement may be as simple as a
`copy, or as complex as an indirect indexed strided copy
`into a unite stride memory,’ wherein a ‘memory hierarchy’
`is ‘a collection of memories.’”
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`Decision at 10. Neither the Board, Patent Owner, nor the patent itself defines “col-
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`lection of memories,” and so the plain and ordinary meaning applies; it is a pair or
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`group of memories, i.e., two or more memories. The Board denied institution solely
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`because it found that the Petition did not specify how each prior art reference—
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`Lange and Zhong—“taught a memory hierarchy and moving data between members
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`of a memory hierarchy,” which under the Board’s construction is “a collection of
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`memories.” Decision at 16-19. In light of the record, this denial is erroneous for at
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`least two reasons.
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`First, the Petition explicitly describes that both Lange and Zhong are directed
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`2
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`to improving the movement of data within “memory hierarchies,” quoting the refer-
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`ences directly:
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`Petition at 8-9: Lange “seeks to improve the performance of ‘memory hierar-
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`chies’ using ‘techniques such as pre-fetching and streaming’”;
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`Petition at 11: Zhong discloses implementing prefetching in “configurable
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`memory hierarchies” to improve application memory behavior.
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`Petition at 36: “The front-end interfaces ‘access a component of a memory
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`hierarchy’: the streaming ports access the FIFO memories, and the caching ports
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`access the BlockSelectRAM.” (emphases added).
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`Second, the Board’s construction of “data prefetch unit” did not add any re-
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`quirements that were not already in the claim, and Petitioners explained in detail
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`how the asserted prior art references met each requirement of the challenged claims.
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`For example, the language of claim 1 already requires that the data prefetch unit
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`moves data between the first memory and the second memory, i.e., members of a
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`collection of memories. Ex. 1001 at claim 1 (“[T]he data prefetch unit retrieves only
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`computational data required by the algorithm from a second memory of second char-
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`acteristic memory bandwidth and/or memory utilization and places the retrieved
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`computational data in the first memory.”) The Board’s construction of the “data
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`prefetch unit” does not add any requirement not already present in the language of
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`the claim itself. And the Petition explained in detail how both Lange and Zhong
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`3
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`disclose a functional unit that moves (i.e., retrieves and places) data between the first
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`memory and the second memory, i.e., members of a collection of memories. See,
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`e.g., Petition at 18-22, 47-52. The Board made no contrary finding. See Decision.
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`Indeed, it acknowledged in its Decision that the Petition explains how both Lange
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`and Zhong teach at least two memories. Decision at 16-17 (“Petitioner asserts that
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`Lange discloses a first memory (i.e., either the FIFO memory in the MARC core or
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`BlockSelectRAM in the FPGA) and a second memory (i.e., SRAM and/or DRAM
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`accessed by the MARC core back-end ports), as recited in the claim.”); id. at 18-19
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`(“Petitioner asserts that Zhong discloses a first memory (i.e., prefetch buffers) and a
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`second memory (i.e., main memory or L2 cache), as recited in the claim”). Thus,
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`the Petition explained how Lange and Zhong disclose the claimed data prefetch unit
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`as construed by the Board. Notably, Patent Owner did not argue otherwise in its
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`preliminary response; it did not address disclosures of Lange and Zhong at all. See
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`Preliminary Response.
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`Petitioners explained in the Petition how Lange and Zhong disclose every as-
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`pect of the “data prefetch unit” as construed by the Board using the very language
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`from the Board’s construction. Petitioners identified in each reference a memory
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`hierarchy with the first and second memories of the claims and upon which the data
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`prefetch unit acts by moving data between the memories. See Petition at 17-22, 47-
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`52. There are no additional or separate requirements in the Board’s construction.
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`4
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`See IPR2018-01600, Paper No. 20 (this same panel of administrative patent judges
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`properly granted institution against the same Patent Owner after construing claim
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`terms differently than Petitioner proposed).
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`Petitioners respectfully request that the Board rehear the Decision and grant
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`institution based on both grounds raised in the Petition. See 37 C.F.R. § 42.71(c)
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`and (d).
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`Dated: June 3, 2019
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`Respectfully submitted,
`FENWICK & WEST LLP
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`
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`/s/ J. David Hadden
`J. David Hadden, Reg. No. 40,629
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`Counsel for Petitioners
`AMAZON WEB SERVICES, INC.,
`AMAZON.COM, INC., and
`VADATA, INC.
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`5
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`CERTIFICATE OF SERVICE
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`The undersigned hereby certifies that a copy of the foregoing Petitioners’ Re-
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`quest for Rehearing Under 37 C.F.R. § 42.71 was served on June 3, 2019, via elec-
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`tronic service on lead and back up counsel.
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`/s/ J. David Hadden
`J. David Hadden
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`10741448.13
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`6
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