DOCKET NO.: 0107131-00573US3
`Filed on behalf of Intel Corporation
`By: David L. Cavanaugh, Reg. No. 36,476
`John V. Hobgood, Reg. No. 61,540
`Benjamin S. Fernandez, Reg. No. 55,172
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Ave., NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
` John.Hobgood@wilmerhale.com
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`INTEL CORPORATION
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED
`Patent Owner
`
`Case IPR2019-00049
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 9,154,356
`CHALLENGING CLAIMS 2-8 and 11
`
`
`
`
`

`

`V. 
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES ............................................................................. 1 
`A. 
`Real Party-in-Interest ............................................................................ 1 
`B. 
`Related Matters ...................................................................................... 1 
`C. 
`Counsel .................................................................................................. 2 
`D. 
`Service Information ............................................................................... 2 
`III.  CERTIFICATION OF GROUNDS FOR STANDING .................................. 2 
`IV.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 3 
`A. 
`Prior Art Patents and Printed Publications ............................................ 3 
`B. 
`Grounds for Challenge .......................................................................... 5 
`BRIEF DESCRIPTION OF TECHNOLOGY ................................................ 6 
`A. 
`Basic Receiver Front End ...................................................................... 7 
`B. 
`Low Noise Amplifiers ......................................................................... 11 
`1. 
`Cascode Configuration .............................................................. 12 
`Carrier Aggregation ............................................................................. 13 
`C. 
`D.  Optional Receiver Circuits .................................................................. 16 
`1. 
`Impedance Matching Circuits ................................................... 16 
`2. 
`Feedback Circuit ....................................................................... 18 
`3. 
`Attenuation Circuit .................................................................... 19 
`4. 
`Inductors .................................................................................... 20 
`VI.  OVERVIEW OF THE ’356 PATENT .......................................................... 21 
`A. 
`Independent Claim 1 ........................................................................... 22 
`B. 
`Summary of the Prosecution History .................................................. 25 
`1. 
`First Office Action ..................................................................... 26 
`2. 
`Second Office Action ................................................................. 27 
`3. 
`Third Office Action ................................................................... 28 
`4. 
`Fourth Office Action ................................................................. 28 
`VII.  CLAIM CONSTRUCTION .......................................................................... 29 
`A. 
`“carrier aggregation” ........................................................................... 30 
`
`i
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`

`

`D. 
`
`X. 
`
`B. 
`C. 
`
`VIII.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 34 
`IX.  OVERVIEW OF PRIOR ART ...................................................................... 34 
`A. 
`A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam
`Phased-Array Receiver in CMOS (“Jeon”) ......................................... 34 
`U.S. Patent Publication No. 2010/0237947 A1 (“Xiong”) ................. 36 
`3GPP TR 36.912 Feasibility study for Further Advancements
`for E-UTRA (LTE-Advanced) (Release 9) (“Feasibility Study”) ...... 38 
`Resistive-Feedback CMOS Low-Noise Amplifiers for Multiband
`Applications (“Perumana”) ................................................................. 40 
`SPECIFIC GROUNDS FOR PETITION ...................................................... 41 
`A.  Ground I: Claims 2-8 and 11 Are Obvious Over Jeon in View
`of Xiong ............................................................................................... 41 
`1. 
`Claim 1 ...................................................................................... 41 
`2. 
`Claim 2 ...................................................................................... 61 
`3. 
`Claim 3 ...................................................................................... 64 
`4. 
`Claim 4 ...................................................................................... 68 
`5. 
`Claim 5 ...................................................................................... 69 
`6. 
`Claim 6 ...................................................................................... 71 
`7. 
`Claim 7 ...................................................................................... 76 
`8. 
`Claim 8 ...................................................................................... 78 
`9. 
`Claim 11 .................................................................................... 79 
`Ground II: Claims 2-8 and 11 Are Obvious Over Jeon in View
`of Xiong and the Feasibility Study ...................................................... 80 
`XI.  CONCLUSION .............................................................................................. 84 
`
`
`B. 
`
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`
`ii
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`

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`I.
`
`INTRODUCTION
`Intel Corporation (“Intel” or “Petitioner”) respectfully requests Inter Partes
`
`Review of 2-8 and 11 of U.S. Patent No. 9,154,356 (the “’356 Patent”) (EX1201-
`
`’356-Patent) pursuant to 35 U.S.C. §§311-19 and 37 C.F.R. §42.1 et seq.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Intel and Apple Inc. (“Apple”) are the real parties-in-interest.
`
`B. Related Matters
`Qualcomm Incorporated (“Qualcomm” or “Patent Owner”) has asserted
`
`the ’356 patent against Apple in Certain Mobile Electronic Devices and Radio
`
`Frequency and Processing Components Thereof, Investigation No. 337-ITC-1093,
`
`currently pending before the International Trade Commission (“ITC 1093
`
`Investigation”).
`
`Qualcomm also has asserted the ’356 patent against Apple in another
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`currently pending case, Qualcomm Inc. v. Apple Inc., No. 3:17-cv-02398 (S.D.
`
`Cal.) (“Related Matter No. 3:17-cv-02398”).
`
`Petitioner is filing the following other petitions for inter partes review of
`
`the ’356 patent: IPR-2019-00047, IPR-2019-00048, IPR-2019-00128, and IPR-
`
`2019-00129.
`
`Petitioner requests that these petitions be assigned to the same panel.
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`1
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`

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`C. Counsel
`Lead Counsel:
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`David L. Cavanaugh (Registration No. 36,476)
`
`Backup Counsel: John V. Hobgood (Registration No. 61,540);
`
`
`
`
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`
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`Benjamin S. Fernandez (Registration No. 55,172).
`
`D.
`Service Information
`E-mail:
`David.Cavanaugh@wilmerhale.com;
`
`John.Hobgood@wilmerhale.com;
`
`
`
`Ben.Fernandez@wilmerhale.com.
`
`Post and hand delivery: Wilmer Cutler Pickering Hale and Dorr LLP
`
`1875 Pennsylvania Ave., NW
`
`Washington, DC 20006
`
`Tel: (202) 663-6000
`
`Fax: (202) 663-6363
`
`Petitioner consents to email delivery on lead and backup counsel.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
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`barred or estopped from requesting an inter partes review challenging the patent
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`claims on the grounds identified in this Petition.
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`2
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`

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`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges 2-8
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`and 11 of the ’356 patent.
`
`A.
`Prior Art Patents and Printed Publications
`The following references are pertinent to the grounds of unpatentability
`
`explained below:1
`
`1.
`
`“A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-
`
`Array Receiver in CMOS,” by Sanggeun Jeon, Yu-Jiu Wang, Hua Wang, Florian
`
`Bohn, Arun Natarajan, Aydin Babakhani, and Ali Hajimiri (“Jeon” (EX1205-
`
`Jeon)), which was published in December 2008 and is prior art under 35 U.S.C.
`
`§102(a) and §102(b).2
`
`2.
`
`U.S. Patent Application Publication No. 2010/0237947 (“Xiong”
`
`(EX1206-Xiong)), which was filed on July 30, 2009, and published on September
`
`23, 2010, and is prior art under 35 U.S.C. §§102(a), (b), and (e).
`
`
`1 The ’356 patent issued from a patent application filed prior to enactment of the
`
`America Invents Act (“AIA”). Accordingly, the pre-AIA statutory framework
`
`applies.
`
`2 See Grenier-Jeon Decl. (EX1231)
`
`3
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`

`

`3.
`
`3GPP TR 36.912 V9.1.0; 3rd Generation Partnership Project;
`
`Technical Specification Group Radio Access Network; Feasibility study for
`
`Further Advancements for E-UTRA (LTE-Advanced) (Release 9) (“Feasibility
`
`Study” (EX1204-Study)), which was published on December 14, 2009, and is prior
`
`art under 35 U.S.C. §102(a) and §102(b).3
`
`4.
`
`“Resistive-Feedback CMOS Low-Noise Amplifiers For Multiband
`
`Applications,” by Bevin G. Perumana, Jing-Hong C. Zhan, Stewart S. Taylor,
`
`Brent R. Carlton, and Joy Laskar (“Perumana” (EX1208-Perumana)), which was
`
`published in May 2008 and is prior art under 35 U.S.C. §§102(a) and (b).4
`
`5.
`
`“Analog integrated circuit design,” by David A. Johns and Ken Martin
`
`(“Johns” (EX1233)), which was published in 1997 and is prior art under 35 U.S.C.
`
`§§102(a) and (b).5
`
`Although the Patent Owner listed Xiong in an Information Disclosure
`
`Statement nearly 16 months before the introduction of the amendment that
`
`ultimately led to the allowance of the claims, Xiong was not cited by the
`
`
`3 See Merias Decl. (EX1226); Rodermund Decl. (EX1227); TR 36.912 Webpage
`
`(EX1228).
`
`4 See Grenier-Perumana Decl. (EX1229)
`
`5 See Johns Decl. (EX1234)
`
`4
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`

`

`Examiner.6 The other references were not before the Patent Office during
`
`prosecution.
`
`B. Grounds for Challenge
`Petitioner requests cancellation of 2-8 and 11 of the ’356 patent as
`
`unpatentable under 35 U.S.C. §103. This Petition, supported by the declaration of
`
`Patrick Fay, Ph.D. (EX1202-Fay-Decl.) filed herewith, demonstrates that there is a
`
`reasonable likelihood that Petitioner will prevail with respect to cancellation of at
`
`least one challenged claim. See 35 U.S.C. §314(a). Petitioner respectfully requests
`
`institution on all challenged claims and on all the challenged grounds. See SAS
`
`Institute Inc. v. Iancu, 138 S. Ct. 1348 (2018).
`
`The ’356 patent is asserted in both the ITC 1093 Investigation and Related
`
`Matter No. 3:17-cv-02398. The Board should not exercise its discretion and deny
`
`the petition based on 35 U.S.C. §314(a) or §325(d) for at least the following
`
`reasons (following the General Plastic Factors)7: First, the petitioner has not filed
`
`petitions other than the series filed within days of the current petition. Second,
`
`
`6 Xiong was included in a set of over 240 references listed in Information
`
`Disclosure Statements filed before the first office action.
`
`7 Gen. Plastic Indus. Co. v. Canon Kabushiki Kaisha, Case IPR2016-01357 et al.,
`
`Paper 19 (Sept. 6 2017)
`
`5
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`

`

`because there are no earlier petitions, Factors 2-5 do not apply. Third, the
`
`presence of other disputes in different fora does not diminish the ability to provide
`
`a Final Written Decision not later than one year after the decision on Institution.
`
`Moreover, the ITC 1093 Investigation does not involve the same remedy, so even a
`
`finding of no violation in the ITC 1093 Investigation would not provide the same
`
`relief that Petitioner seeks in this proceeding. The district court case is not in an
`
`advanced stage and currently has a trial scheduled to start October 21, 2019. For
`
`each of these reasons, the Board should permit this Inter Partes Review proceeding
`
`move forward to trial.
`
`V. BRIEF DESCRIPTION OF TECHNOLOGY
`The ’356 patent issued from U.S. App. No. 13/590,423, filed on August 21,
`
`2012, and claims priority to U.S. Provisional Application No. 61/652,064, filed on
`
`May 25, 2012. In Related Matter No. 3:17-cv-02398, Patent Owner alleged a
`
`conception date of March 25, 2012, for the ’356 patent (“Alleged Conception
`
`Date”). Petitioner disagrees that the ’356 patent is entitled to a priority date earlier
`
`than May 25, 2012. However, even if entitled to a priority date of March 25, 2012,
`
`all challenged claims are unpatentable for the reasons set forth herein. See
`
`EX1202-Fay-Decl. ¶31, 31, n.1.
`
`The ’356 patent relates to a low noise amplifier (LNA) within a radio
`
`frequency (RF) receiver configured to support carrier aggregation (CA). The
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`6
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`

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`patent relies on prior art circuit components and well-known concepts related to
`
`the design of receivers for processing multi-frequency signals. This overview
`
`explains the basic operation and characteristics of such front-end receivers (i.e., the
`
`components between the antenna and the digital baseband system, including the
`
`filters, LNAs, and down conversion mixers that transform signals received at the
`
`antenna into baseband signals). These components were well-established
`
`background knowledge for those of ordinary skill in the art well before the Alleged
`
`Conception Date. EX1202-Fay-Decl. ¶31.
`
`A. Basic Receiver Front End
`A wireless communication system comprises a network of base stations and
`
`mobile devices. A mobile device, such as a cellular phone, has a receiver that
`
`receives radio frequency signals from multiple base stations, such as cell towers.
`
`The radio frequency signals sit within radio frequency bands of the
`
`electromagnetic spectrum. The FCC allocates radio frequency bands to specific
`
`applications, such as FM radio broadcasts. Within a frequency band, different
`
`carrier signals (or “carriers”) carry different information. Each carrier occupies a
`
`certain frequency range when modulated to carry information. EX1202-Fay-Decl.
`
`¶32.
`
`The antenna of a receiver captures desired and undesired signals, including
`
`signals from frequency bands assigned to other applications and “interferer”
`
`7
`
`

`

`signals within the same band as the desired signals. The task of a receiver is to
`
`remove the undesired signals to extract only the carriers (frequencies) that carry
`
`the relevant information. The receiver does so by selectively filtering, amplifying,
`
`and down converting the signal. Figure 1 below shows a typical direct-conversion
`
`receiver (the type used in the ’356 patent, EX1201-’356-Patent at Figure 4B)
`
`where these steps are performed. EX1202-Fay-Decl. ¶33.
`
`Figure 1. A direct-conversion receiver containing an antenna, a band-
`
`pass filter, a low noise amplifier, and two mixers coupled to low-pass
`
`
`
`filters.
`
`The antenna in Figure 1 receives signals on desired and undesired
`
`frequencies. The band-pass filter (BPF) attenuates all frequencies that fall outside
`
`8
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`

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`the desired frequency band.8 The low noise amplifier (LNA) increases the power
`
`of the remaining carriers by a gain factor.9 Finally, the mixers down convert the
`
`frequencies to enable the low-pass filters (LPF) to select the specific carrier
`
`containing the relevant information. Figures 2-5 show a signal undergoing these
`
`various processing steps. EX1202-Fay-Decl. ¶34.
`
`
`
`
`Figure 2. An input RF signal containing multiple frequencies as collected by
`
`the antenna.
`
`
`
`
`8 Attenuation is the opposite of amplifying. Although an amplifier increases the
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`power, or amplitude, of a signal, resulting in a “gain,” a filter decreases the
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`amplitude of undesired frequencies. EX1202-Fay-Decl. ¶34, n.3.
`
`9 “Gain” is the measure of the increase in the amplitude, or power, of a signal as
`
`the result of the amplification. EX1202-Fay-Decl. ¶34, n.4.
`
`9
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`

`

`
`Figure 3. Frequencies in an input RF signal after the BPF attenuates out-of-
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`band carriers and the LNA amplifies the remaining frequencies.
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`
`
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`
`
`Figure 4. Frequencies in an input signal after the mixer down converts the
`
`
`
`carriers.
`
`
`
`10
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`

`

`
`Figure 5. Frequencies in an input signal after the LPF attenuates all but one
`
`
`
`carrier.
`
`The ’356 patent implements the same basic RF receiver structure—including
`
`an antenna, a low noise amplifier, mixers and filters—to process incoming RF
`
`signals, all of which was standard in wireless communication systems before the
`
`Alleged Conception Date. See EX1201-’356-Patent at Figure 4B; EX1202-Fay-
`
`Decl. ¶34.
`
`B.
`Low Noise Amplifiers
`A low noise amplifier (“LNA”) is a long-known component of a front-end
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`receiver used to increase the signal strength of a received radio signal. An LNA
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`increases the amplitude, or power, of a signal. If the amplifier receives an input
`
`voltage and outputs a current proportional to the input voltage, it is called a
`
`“transconductance” amplifier. EX1202-Fay-Decl. ¶35.
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`11
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`

`

`Cascode Configuration
`1.
`A cascode amplifier is a type of LNA. Modern cascode amplifiers include
`
`two transistors: (1) a common source “transconductance” transistor that receives an
`
`input voltage signal and converts it to current with an applied gain, and (2) a
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`common gate “cascode” transistor that couples the current to the output signal. In
`
`Figure 6 below, Q1 is the transconductance transistor, while Q2 is the cascode
`
`transistor. EX1202-Fay-Decl. ¶36.
`
`
`
`I bias
`
`V out
`
`Cascode
`Transistor
`
`Transconductance
`Transistor
`
`Q 2
`
`Q1
`
`V bias
`
`V in
`
`Figure 6. Cascode Amplifier: Q1 is the transconductance transistor and Q2
`
`
`
`is the cascode transistor.
`
`12
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`

`

`This amplifier amplifies the input RF signal (Vin) to produce a current signal (at
`
`Vout). Such amplification requires current to flow through the circuit, which
`
`depends on the voltage signals applied to the gates of both the transconductance
`
`transistor (Vin) and the cascode transistor (Vbias). If the voltage signal to the
`
`cascode transistor (Vbias) is too low—because, for example, the gate of the
`
`cascode transistor is coupled to ground—current will not flow through the
`
`amplifier stage, and the amplifier will be effectively disabled (even if the
`
`transconductance transistor continues to receive the RF input voltage signal).
`
`EX1202-Fay-Decl. ¶37.
`
`The cascode configuration was known to provide benefits decades before the
`
`Alleged Conception Date—e.g., improved isolation between the input and output
`
`signals, higher gain, and higher bandwidth than single stage amplifiers—and had
`
`been a popular choice of radio circuit designers. The ’356 patent uses the cascode
`
`configuration in the same way as it was typically used in RF communication
`
`systems before the Alleged Conception Date. See EX1201-’356-Patent at 7:58-
`
`8:9; EX1202-Fay-Decl. ¶38.
`
`C. Carrier Aggregation
`Carrier aggregation (“CA”) is the transmission or reception of data on
`
`multiple carriers to or from a wireless device at the same time. Rather than
`
`transmitting or receiving data on a single carrier (i.e., a single base frequency that
`
`13
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`

`

`occupies a particular frequency range), a signal employing carrier aggregation
`
`transmits related or unrelated data on multiple carriers (i.e., multiple different base
`
`frequencies occupying different frequency ranges) simultaneously. Transmitting
`
`data on multiple carriers can increase the data rate transmitted from a wireless
`
`transmitter to a wireless receiver by allowing information to be extracted from
`
`multiple carriers simultaneously. EX1202-Fay-Decl. ¶39.
`
`A receiver enabled for carrier aggregation differs from non-carrier
`
`aggregation enabled receivers in that it can extract information from multiple
`
`signals transmitted on different carriers (and thus at different frequencies)
`
`simultaneously. The receiver does this by using multiple receive paths, where each
`
`receive path is configured to extract information from a single carrier frequency.
`
`In the example shown in the figure below, the receiver contains two receive paths
`
`containing two LNAs providing output to two sets of mixers for the extraction of
`
`two frequencies.
`
`
`
`
`
`14
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`

`

`
`
`
`Figure 7. A carrier-aggregation enabled receiver with two receive paths. Source:
`
`
`
`Figure 15 of U.S. Patent No. 8,442,473 (“Kaukovuori”) (EX1225-Kaukovuori))
`
`
`Thus, the multiband receiver can process multiple frequencies at the same time.
`
`EX1202-Fay-Decl. ¶42.
`
`
`
`The ’356 patent follows this known technique of using multiple receive
`
`paths in a receiver to support carrier aggregation. The ’356 patent includes
`
`multiple “amplifier stages,” with each amplifier stage processing a different set of
`
`carriers. See EX1201-’356-Patent at 8:10-12 (“FIG. 6A shows CA LNA 640a
`
`including two amplifier stages 650a and 650b for two sets of carriers.”); id. at
`
`15
`
`

`

`8:32-35 (“In the CA mode, CA LNA 640a receives transmissions on two sets of
`
`carriers and provides two output RF signals to two load circuits, one output RF
`
`signal for each set of carriers.”); EX1202-Fay-Decl. ¶42.
`
`D. Optional Receiver Circuits
`Before the Alleged Conception Date, a variety of circuits to address
`
`impedance matching and other problems in LNA design were well known. Several
`
`of the challenged dependent claims encompass these well-known circuits. These
`
`circuits and the issues they address are discussed below. EX1202-Fay-Decl. ¶43.
`
`Impedance Matching Circuits
`1.
`In addition to configuring the gain to particular input signal strengths, an
`
`LNA must address the problem of impedance matching. Impedance is the
`
`effective resistance of a circuit to current flow when voltage is applied. If the
`
`impedance of the source (the electrical component that provides the signal power)
`
`is not equal to the impedance of the load (the electrical component that receives
`
`the signal) power transfer is not maximized, and some signal may be reflected back
`
`to the source. In the figure below, for example, the source and load impedances
`
`are mismatched with the line impedance, resulting in differences (discontinuities)
`
`in impedance along the transmission line and potentially causing the transmitted
`
`signal to be reflected back toward its origin.
`
`16
`
`

`

`
`
`Figure 8. Impedance mismatch due to discontinuities, which may result in
`
`signal reflection.
`
`
`Impedance matching seeks to maximize power transfer and/or minimize the
`
`amount of noise added to the signal. EX1202-Fay-Decl. ¶44.
`
`An impedance matching circuit optimizes the impedance of a source and a
`
`load. When impedance matching takes place at the input stage, the circuit is called
`
`an input matching circuit or network. A variety of topologies have been developed
`
`for circuits that perform impedance matching. Figure 9 shows one topology. Id.
`
`¶45.
`
`
`
`
`
`Figure 9. An L-network impedance matching circuit.
`
`
`
`17
`
`

`

`A simple matching circuit such as that shown in Figure 9 provides perfect
`
`impedance matching at one frequency. To achieve optimal impedance matching at
`
`different frequencies, a receiver front end can use a tunable matching circuit. A
`
`tunable matching circuit has components with variable electrical characteristics.
`
`Tunable impedance matching circuits were well known in the art before the ’356
`
`patent. EX1202-Fay-Decl. ¶46.
`
`The ’356 patent uses adjustable input matching circuits to provide better
`
`impedance matching across different modes, as was commonly done in the field of
`
`RF communication systems before the Alleged Conception Date. See EX1201-
`
`’356-Patent at 13:47-51 (“Matching circuit 932 may be adjusted based on the
`
`number of enabled amplifier stages and/or which amplifier stage(s) are enabled in
`
`order to obtain good noise/power match in both the CA modes and the non-CA
`
`modes.”); id.
`
`Feedback Circuit
`2.
`A feedback circuit may be installed between the input and the output of an
`
`amplifier to enhance the stability of the amplifier. A feedback circuit functions by
`
`reducing the level of the input to an amplifier based on the level of the amplifier’s
`
`output. Thus, as the output rises, for example, the feedback circuit will mitigate
`
`the increase. This reduces the gain of the signal, but it has the benefit of reducing
`
`the amplifier’s sensitivity to transistor parameter variations. Also, the input and
`
`18
`
`

`

`output impedances can be better matched with feedback, and the bandwidth can be
`
`increased. Thus, overall circuit performance is improved at the expense of gain.
`
`EX1202-Fay-Decl. ¶47.
`
`Feedback circuits were known to improve impedance matching long before
`
`the ’356 patent. The ’356 patent’s use of a feedback circuit to provide input power
`
`matching as an alternative to or in addition to inductors to yield the predictable
`
`result of better impedance matching was thus not novel at the time of the claimed
`
`invention. See EX1201-’356-Patent at 10:35-41; id.
`
`Attenuation Circuit
`3.
`Low-power signals require the LNA to provide high gain to allow proper
`
`down conversion by a mixer. By contrast, high-power signals require a lower gain
`
`to avoid the problem of distortion, or in the extreme case, “clipping.” Clipping
`
`occurs when the amplitude of the input signal is so high that it would exceed the
`
`amplifier’s maximum output current or voltage if amplified. Because the amplifier
`
`cannot exceed its maximum output current or voltage, the output of the amplifier is
`
`“clipped,” or constrained to the maximum limit, as shown below where an input
`
`signal is amplified so much that its peaks are clipped. EX1202-Fay-Decl. ¶48.
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`19
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`
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`Figure 10. Signal clipping from excessive gain.
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`An attenuator is the opposite of an amplifier: an attenuation circuit reduces
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`the power of a signal. Attenuation can therefore help avoid signal clipping.
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`Attenuation circuits also can be used to improve impedance matching. The ’356
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`patent uses an attenuation circuit to attenuate jammer signals (undesired signals of
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`large amplitude and close in frequency to the desired signals) and to provide
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`impedance matching, as was commonly done in the field of RF communication
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`systems before the Alleged Conception Date. See EX1201-’356-Patent at 12:17-24
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`(“Input attenuation circuits . . . may serve a dual purpose of attenuating the
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`jammers in the input RF signal and providing a good input impedance match for
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`CA LNA 840a.”); EX1202-Fay-Decl. ¶49.
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`Inductors
`4.
`An inductor is an electrical component that stores electrical energy when
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`current flows through it. Inductors add little noise and can be used as alternatives
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`or additions to some of the circuits described above (such as with input matching
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`20
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`circuits to help with impedance matching). Inductors used in this way can also be
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`alternatives or additions to a feedback circuit because they improve the linearity of
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`an LNA (i.e., the ability of the LNA to provide an output signal that is directly
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`proportional to the input signal). EX1202-Fay-Decl. ¶50.
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`The ’356 patent uses inductors to provide impedance matching as an
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`alternative to a feedback circuit, as was commonly done in the field of
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`communication systems before the Alleged Conception Date. See EX1201-’356-
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`Patent at 10:35-40 (“In an exemplary design, feedback circuit 660 may be
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`used/enabled for low-band to provide input power match. For mid-band and high-
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`band, feedback circuit 660 may be disabled, and source degeneration inductors
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`652a and 652b may be used with matching circuit 632 for input power match.”);
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`EX1202-Fay-Decl. ¶50.
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`VI. OVERVIEW OF THE ’356 PATENT
`The purported invention of the ’356 patent is an LNA that “support[s] carrier
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`aggregation” with “better performance.” EX1201-’356-Patent at 2:22-25. As
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`described in the claims, specification, and prosecution history, the LNA of the ’356
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`patent has multiple amplifier stages that receive a carrier aggregated signal,
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`amplify it, and provide outputs to multiple load circuits. EX1201-’356-Patent at
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`Abstract. The LNA of the ’356 patent also supports non-carrier aggregated signals
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`21
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`by disabling all but one of the amplifier stages. Id. at 8:45-54. See generally
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`EX1202-Fay-Decl. ¶51.
`
`A.
`Independent Claim 1
`Claim 1 corresponds to the exemplary LNA embodiment shown in Figure
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`4B, as illustrated below.
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`
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`Claim 1 recites an apparatus (shown above as LNA 440x) having two amplifier
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`stages (shown above as the red and blue triangles) to amplify an input radio
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`frequency (RF) signal employing carrier aggregation. EX1201-’356-Patent at
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`20:43-61. The input RF signal includes transmissions sent on multiple carriers at
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`different frequencies. Id. at 20:49-51. The first amplifier stage is configured to be
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`independently enabled or disabled. Id. at 20:44-45. The first amplifier stage
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`22
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`receives and amplifies an input RF signal (RFin) and provides a first output RF
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`signal (RFout1) to a first load circuit (490x) when enabled. Id. at 20:44-48.
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`Likewise, the second amplifier stage is configured to be independently enabled or
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`disabled. Id. at 20:54-55. The second amplifier stage receives and amplifies the
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`input RF signal (RFin) and provides a second output RF signal (RFout2) to a
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`second load circuit (490y) when enabled. Id. at 20:54-58. The first output RF
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`signal (RFout1) includes a first carrier of the multiple carriers, and the second
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`output RF signal (RFout2) includes a second carrier of the multiple carriers
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`different from the first carrier. Id. at 20:51-53, 20:58-61; EX1202-Fay-Decl. ¶52.
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`Figure 6A shows the internal structure of an exemplary LNA 640a.
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`
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`23
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`An input matching circuit 632 receives a receiver input signal, RXin, and provides
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`an input RF signal, RFin, to LNA 640a. EX1201-’356-Patent at 7:47-52. LNA
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`640a “includes two amplifier stages 650a and 650b” (outlined in red and blue). Id.
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`at 7:47-48; EX1202-Fay-Decl. ¶¶53-54.
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`The first amplifier stage 650a (outlined in red) includes a gain transistor
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`654a (i.e., a transconductance transistor)10 coupled to a cascode transistor 656a.
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`EX1201-’356-Patent at 7:58-60. The gate of gain transistor 654a receives the input
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`RF signal (RFin) while its source is coupled to ground via a source degeneration
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`inductor 652a. Id. at 7:49-52, 7:63-66. As discussed in Section V.B.1, the
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`transistor arrangement of the first amplifier stage 650a is a “cascode amplifier,”
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`which was known before the Alleged Conception Date. EX1202-Fay-Decl. ¶53.
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`The drain of the gain transistor 654a is coupled to the source of the cascode
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`transistor 656a, and the drain of cascode transistor 656a is coupled to a first load
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`circuit 690a. EX1201-’356-Patent at 7:66-8:01. A switch 658a selectively couples
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`the gate of cascode transistor 656a to either a bias voltage, Vcasc, or to circuit
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`ground. Id. at 8:01-04. When the switch 658a couples the gate of the cascode
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`transistor 656a to the bias voltage (Vcasc), current can flow through the first
`
`
`10 The ’356 patent refers to the transconductance transistors in a cascode as “gain”
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`transistors. EX1202-Fay-Decl. ¶53, n.8.
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`24
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`amplifier stage 650a, thereby enabling the first amplifier stage 650a. See id. at 8:1-
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`4, 8:12-13, 8:37-42. The gain transistor 654a amplifies the input RF voltage
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`signal, which passes through cascode transistor 656a to the first load circuit, 690a.
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`See id. at 8:52-54. However, when the switch 658a couples the gate of the cascode
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`transistor 656a to circuit ground, current is unable to flow through the first
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`amplifier stage 650a, thereby disabling the first amplifier stage 650a. See id. at
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`8:4-9, 8:47-57. This design allows the LNA of the ’356 patent to support both
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`carrier aggregation and non-carrier aggregation operation in different modes.
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`EX1202-Fay-Decl. ¶¶53-55.
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`LNA 640a has a second amplifier stage 650b (outlined in blue) that also
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`receives the input RF signal (RFin) and is coupled to a second load circuit 690b.
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`EX1201-’356-Patent at 8:4-9, 8:24-28. Switch 658b independently enables or
`