2660
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
`
`A Scalable 6-to-18 GHz Concurrent Dual-Band
`Quad-Beam Phased-Array Receiver in CMOS
`
`Sanggeun Jeon, Member, IEEE, Yu-Jiu Wang, Student Member, IEEE, Hua Wang,
`Florian Bohn, Student Member, IEEE, Arun Natarajan, Aydin Babakhani, Member, IEEE, and
`Ali Hajimiri, Member, IEEE
`
`Abstract—This paperreports a 6-to-18 GHz integrated phased-
`array receiver implemented in 130-nm CMOS. Thereceiver is
`easily scalable to build a very large-scale phased-array system.
`It concurrently forms four independent beams at two different
`frequencies from 6 to 18 GHz. The nominal conversion gain
`of the receiver ranges from 16 to 24 dB over the entire band
`while the worst-case cross-band and cross-polarization rejections
`are achieved 48 dB and 63 dB, respectively. Phase shifting is
`performed in the LO path by a digital phase rotator with the
`worst-case RMS phase error and amplitude variation of 0.5°
`and 0.4 dB, respectively, over the entire band. A four-element
`phased-array receiver system is implemented based on four re-
`ceiver chips. The measured array patterns agree well with the
`theoretical ones with a peak-to-null ratio of over 21.5 dB.
`
`Index Terms—CMOS,concurrent, large-scale phased arrays,
`multi-band, multi-beam, phased arrays, scalable, tritave.
`
`I.
`
`INTRODUCTION
`
`HASEDarrays steer the beam direction electronically,
`bringing many benefits such as high directivity,
`inter-
`ference rejection, signal-to-noise ratio improvement, and fast
`scanning response [1]-[4]. For this reason, phased arrays have
`been extensively employed in radar and communication sys-
`tems in the area of military, space, and radio astronomy since
`their advent in the 1950s [5], [6]. Recently, substantial atten-
`tion is also drawn in civil applications including high-speed
`point-to-point communicationsandcar radars [4], [7].
`Benefits of phased arrays increase with the numberofele-
`ments combined in the array. This gives rise to the desire to
`make very large-scale phased arrays (up to 10° elements) for
`high-precision radars, long-range sensors, or high-directivity
`communication systems. One of the major obstacles in imple-
`menting large-scale phased arrays lies in the high complexity
`and cost to assemble the whole array system. Traditionally,
`phased-array systems have been built using a module-based
`approach. Most
`transmitter/receiver components,
`such as
`
`Manuscript received April 17, 2008; revised June 24, 2008. Current version
`published December 10, 2008. This work was supported by the Office of Naval
`Research under Contract N00014-04-C-0588.
`S. Jeon is with the School of Electrical Engineering, Korea University,
`Seongbuk-gu, Seoul, Korea (e-mail: sgjeon@korea.ac.kr).
`Y.-J. Wang, H. Wang, F. Bohn, A. Babakhani, and A. Hajimiri are with
`the Department of Electrical Engineering, California Institute of Technology,
`Pasadena, CA 91125 USA.
`A. Natarajan is with the IBM T. J. Watson Research Center, Yorktown
`Heights, NY 10598 USA.
`Digital Object Identifier 10.1109/JSSC.2008.2004863
`
`low-noise amplifiers (LNAs), power amplifiers, phase shifters,
`attenuators, filters, mixers, and LO sources, are implemented
`in separate modules and then interconnected to each other
`externally [3], [6]. This approach not only increases the as-
`sembly size and cost, but also degrades the system reliability
`due to the complicated configuration. Furthermore, several
`transmit/receive module components have been implemented
`using expensive compound semiconductors such as GaAs,
`whichtakes a substantial portion of the overall system cost[6],
`[8]. Thus, the size of phased arrays has been limited to a certain
`numberof elements (10+ or 10° at most), makingit difficult to
`take full advantage of very large-scale array systems.
`Integrated CMOSsolutions offer an opportunity for dramatic
`reduction in cost and size of such systems. The high yield and
`repeatability of silicon ICs allowsthe entire transmitter and/or
`receiver to be integrated on a single chip. For example, there
`have been reported a CMOSRF front-end[9], a fully integrated
`Si-based phased-array receiver [10] and a CMOSphased-array
`transmitter [11], all at 24 GHz and a fully integrated Si-based
`phased-array transceiver at 77 GHz [12]. This single-chip ap-
`proachin silicon reduces the overall system cost substantially,
`compared to the conventional module-based counterpart
`in
`compound semiconductors.
`Thereis a trend in radar and communication systemsthat the
`transceiver operates concurrently in multiple modes and mul-
`tiple bands [13]. Furthermore, many applications require the
`transceiver to operate in a wide range of RF frequencies [14].
`These trends also apply to phased arrays when multiple tar-
`gets must be tracked at the same timein radars and electronic
`countermeasure systems or when multi-point communications
`are desired at multiple frequencies in a wide bandwidth. The
`high integration capability of CMOSoffers a promising solu-
`tion to achieve the wideband phased arrays with multiple func-
`tionalities. Several wideband phased (or timed) array receivers
`[15], [16] and transceiver [17] have been reported in silicon.
`However, none of the previous work has implemented a con-
`current multi-band multi-beam phased-array receiver operating
`in a wide range of RF frequencies.
`In this work, we integrated RF front-end components of a
`concurrent dual-band quad-beam phased-array receiver ele-
`menton a single CMOSchip. Thereceiver is programmable to
`concurrently receive two RF frequencies between 6 and 18 GHz
`(a tritave) while forming four independently-controlled beams
`with separate phase shifting operation. The receiver is also
`easily scalable toward very large-scale phased arrays because
`additional receiver chips can be added to increase the number
`
`0018-9200/$25.00 © 2008 IEEE
`
`INTEL 1105
`
`

`

`JEONet al.: SCALABLE 6-TO-18 GHz CONCURRENT DUAL-BAND QUAD-BEAM PHASED-ARRAY RECEIVER IN CMOS
`
`2661
`
`
`
`Fig. 1. Basic phased-array receiver configuration.
`
`of array elements with relatively lower cost and complexity. To
`the authors’ best knowledge,this is the first reported concurrent
`tritave phased-array receiver implemented in CMOS.
`The paperis organized as follows. Section II briefly reviews
`phasedarrays and a conventional approach to implementlarge-
`scale phased arrays. Section III presents a proposed concurrent
`array system architecture as well as the associated advantages.
`In Section IV,the architecture and frequency plan of the CMOS
`phased-array receiver chip is described. Section V presents the
`detailed circuit block design. Section VI provides the exper-
`imental results of the receiver chip and a four-element array
`system that combines four receiver chips.
`
`II. PHASED ARRAYS
`
`A. Overview
`
`Phased-array receivers consist of multiple antenna elements
`spaced with a certain distance (d) and a following separate
`phase shifter per each element for the electronic beamforming
`at a given incident angle (6) in space (Fig. 1). When a RF wave
`arrives at the antenna elements, the arrival time of wavefrontis
`different between two adjacent elements by
`
`_ dsin@
`—
` ¢@
`
`At
`
`()
`
`wherec is the speed oflight. In the narrowband circumstances,
`the arrival time difference results in a phase delay of the received
`signal between two adjacent elements, given by
`
`Ay= ane6
`
`(2)
`
`where \ is the wavelength of the incoming wave. Thus,the fol-
`lowing phase shifter adjusts the phase delay in such a way that
`output signals from each elementare all in-phase with one an-
`other. By summing the signals from each element, a coherent
`output signal can be obtained with a large array gain. On the
`other hand, other incoming wavesat different incident angles
`will not be summed coherently andthuswill be significantly at-
`tenuated at the array output.
`
`B. Benefits of Phased Array
`
`gain than a single element receiver. When the signals are com-
`bined in the amplitude domain (current or voltage) with a same
`output load, the array gain is given by
`
`Garray = Gsingle + 20 logio N (dB)
`
`(3)
`
`where Gingle is the gain of each single element and N is the
`numberof array elements. Again, undesired signals such as the
`interference or jammersarriving at other incident angles are in-
`herently rejected accordingto the established array pattern.
`Furthermore, the signal integrity is enhanced at the array
`output
`through an effective improvement of the output
`signal-to-noise ratio (SNR) by a factor of 10log,) N (dB).
`This is because noise generated from each elementis uncor-
`related with one another while the desired signal is combined
`coherently [10].
`Finally, since phase arrays steer the beam direction electron-
`ically, it is able to receive multiple beamsarriving at different
`incident angles simultaneously. Also, the beam can be steered
`in a faster and morereliable way than that of a mechanically
`steered antenna system.
`
`C. Large-Scale Phased-Array System
`
`The benefits of phased arrays given in Section II-B are more
`noticeable as we increase the numberof array elements. For in-
`stance, if we combinethe signals from one million (10°) el-
`ements without any loss and phase distortion, then the array
`gain given in (3) and the output SNR will be improved by a
`factor of 120 dB and 60 dB, respectively. Although the improve-
`mentfactor will be degraded in a practical array system due to
`the non-ideal signal distribution and combining,it will enhance
`the sensitivity of the receiver to a substantial degree. The capa-
`bility of rejecting undesired signals will also be reinforced with
`a larger number of elements because the main beam narrows
`and a more numberofnull positions are presented in the array
`pattern.
`In spite of the apparent advantages of large-scale phased ar-
`rays, their applications have been limited due to several dif-
`ficulties, mainly, the prohibitive complexity and cost. Fig. 2
`showsone of the conventional ways of building a large-scale
`phased-array receiver system. In order to combinea very large
`numberof elementsefficiently, several elements are groupedto-
`gether into a sub-array, and then several sub-arrays are com-
`bined by a RF distribution network to present a single output
`for down-conversion. It is noteworthy that for active phased ar-
`rays [1], every single element contains an independentreceiver
`module which includesa filter, a LNA, a phase shifter, and an
`attenuator. Usually, these receiver components are implemented
`in separate chips or packages, interconnected to each other, and
`then assembledinto a sub-array system by external transmission
`lines such as microstrips, cables, or waveguides. Therefore, as
`the numberof array elements increases, the cost and complexity
`will also rise dramatically to assemble these componentsinto a
`system. Furthermore, the design of the low-loss RF distribution
`network will be challenging with a large number of elements
`for two reasons. Thefirst reason is that the number of sub-ar-
`
`Since a phased array combinesseveral in-phase signals co-
`herently at the array output, it can achievean effectively higher
`
`rays is also increased accordingly, which requires more depth
`of the signal distribution (or combining) network. The otheris
`
`

`

`2662
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
`
`Concurrent multiple beams
`
`
`HP: Horizontalpolarization,
`VP:Vertical polarization,
`LB: Low band (6 - 10.4 GHz),
`HB: High band (10.4 - 18 GHz)
`
`
`
`
`
`sy JZ
`
`6-18GHz
`CMOSreceiver
`
`Active antenna
`module #1
`HP(fis +fus)
`
`
`
`Mh
`f
`60
`HPreceiver
`
`LB, VPreceiver/omY1
`VP(fis +fue)
`
`
`
`RFfront-end modules
`per each beam
`
`
`
`
`
`fu, 02
`
`Zt
`
`fp, 03
`
`fu, 04
`
`Active antenna
`module #2
`
`
`
`
`HP (fis fis)
`
`VP (fis +0)
`
`module #N
`Active antenna
`
`és 7 HP(fis +s)
`
`
`VP(fis +fuB)
`
`HPreceiver
`VPreceiver
`
`.
`
`Easily scalable :
`:
`
`HPreceiver
`VPreceiver _/
`
`Reference signal
`for PLL (50MHz)
`
`
`
`
`
`eo
`
`BBforfp, 0;
`BBforfup, 92
`BBforfis, 93
`BBfor firs, 94
`(1& Qoutputeach)
`
`|
`:
`
`Fig. 2. A conventional way of building a large-scale phased-array receiver
`system (in the active array configuration) that supports multiple beams.
`
`Fig. 3. A proposed 6-18 GHz phased-array receiver system that receives four
`beams at two frequencies concurrently andis easily scalable towarda very large-
`scale array.
`
`that the signal is distributed (or combined) in the RF domain
`before down-conversion, which givesrise to higher loss than if
`the distribution (or combining) were to be performed in the IF
`or baseband domain.
`
`respectively. On the other hand, each input port is able to re-
`ceive a dual-band signal containing two different frequencies
`concurrently, one in the low band (LB) from 6 to 10.4 GHz
`Another challenge in large-scale phased arrays is the high
`and the other in the high band (HB) from 10.4 to 18 GHz. The
`cost of active circuit components, most of which are fabricated
`dual-band signalis then split into two separate signals on-chip,
`usually in expensive compound semiconductors such GaAs.
`one for each band. Subsequently, each signal is down-converted
`Although the cost of monolithic microwave integrated circuits
`with the independentphase-shifting operation to provide sep-
`(MMICs) in GaAsdecreased recently due to the process matu-
`arate beamforming. Therefore, the proposed array system can
`rity, it still takes a large portion of the total array system cost
`receive and steer four different beamsat two different frequen-
`[6], [8], making a very large-scale array practically difficult to
`cies concurrently.
`implement.
`The baseband outputs from each array element are combined
`Even more challenge arises whenthe array must receive mul-
`off-chip in the current domain, providing the back-end proces-
`tiple beamsat the same time. Since each beam requires a sep-
`sors with one combined baseband signal per beam. Since the
`arate receiver module andadistribution network for the inde-
`signal combining is performed at the baseband rather than the
`RF frequency,it alleviates the difficulty in designing a low-loss
`combining networkfor large-scale arrays.
`It is also noteworthy that the only feed signal which needs
`to be distributed among the elements other than DC suppliesis
`a 50 MHzreference signal for on-chip frequency synthesizers.
`Dueto its low frequency,the reference can be simply distributed
`without adding extra complexity. It also makes the proposed
`array architecture easily scalable.
`The LOsignals generated by the on-chip frequency synthe-
`sizers may haverelatively higher phase noise than those pro-
`vided by off-chip low-noise sources. However, when combining
`N elements (or N chips) in the array, the phase noise origi-
`nating from the on-chip components of each elementis uncor-
`related with one another and thus adds up in power. On the
`other hand, the carrier signal is combined in amplitude in the
`current domain. Therefore, the phase-noise performanceat the
`array output improves by a factor of 10log,) N (dB) as long
`as the phase noise is dominated by on-chip sources, not by an
`off-chip reference signal. This improvementalso makesthe in-
`tegrated solution including on-chip frequency synthesizers suit-
`able for large-scale phased arrays without degrading the array
`performance.
`
`pendent beamforming capability, the associated complexity and
`cost will be further exacerbated.
`
`Ill. PROPOSED LARGE-SCALE PHASED-ARRAY
`SYSTEM ARCHITECTURE
`
`To deal with the challenges discussed in Section I-C, wepro-
`pose an efficient way of building large-scale phased-array re-
`ceiver systems, as shownin Fig. 3. With a single CMOSchip (a
`shaded block in Fig. 3), we integrate all receiver module com-
`ponents on the same die except for the antenna and front-end
`LNA. The CMOSreceiverincludes the tunable concurrent am-
`
`plifiers (TCAs), down-conversion mixers, phase shifters, fre-
`quency synthesizers, and basebandbuffers [18]. This integrated
`solution avoids the costly large number of separate component
`modules and their complicated interconnection for large-scale
`arrays, which results in a dramatic cost reduction. More impor-
`tantly, the chip is implemented in CMOS, which will bring an-
`other substantial cost reduction compared with its compound-
`semiconductor counterpart.
`The CMOSreceiver has two input ports to receive two dif-
`ferent polarization signals fed from an active antenna module,
`i.e., horizontal polarization (HP) and vertical polarization (VP),
`
`

`

`JEONet al.: SCALABLE 6-TO-18 GHz CONCURRENT DUAL-BAND QUAD-BEAM PHASED-ARRAY RECEIVER IN CMOS
`
`2663
`
`HP: Horizontal polarization, VP: Vertical polarization,
`LB: Low band, HB: High band
`
`BBout
`> }
`(HP_HB,1)
`|
`)
`a
`a >
`PLL
`(HP_|
` x ss402.008)|LO2_Q (LB)|—~—|-—>
`
`
`RF (HP_LB)
`
`RF (HP_HB)
`
`tHE’LB)
`—
`
`IF buffer
`HP_LB
`(
`)
`
`IFmixer +
`ase rotator
`
`Baseband
`
`_
`
`Q
`
`[
`
`|)
`
`BB out
`(HP_LB,
`—
`BB out
`(HP_LB, Q)
`
`HP_HB, Q
`
`;
`HPRFinput
`(LB +HB)
`
`Data
`
`CLKLatch
`
`Ref
`(50MHz)
`
`
`
`Aatows)| (VP_HB,I)
`
`BBout
`
`PLL 2
`|+
`
`
`
`VCO (HB, 9 - 12 GHz)
`
`2.8V
`
`Bandgap
`
`RF mixer IF buffer
`
`1.6V 3Bancaar|(VP_HB) (vP_HB) BB out
`
`:
`RF mixer IF buffer
`
`BB out
`(VP_HB, Q)
`
`(VP_LB, I)
`
`VP RFinput
`(LB +HB)
`
`RF (VP_HB)
`
`RF (VP_LB)
`
`(VP_LB)
`
`(VP_LB)
`
`IF mixer +
`Phaserotator
`
`Baseband
`VGA
`
`BBout
`(VP_LB, Q)
`
`Fig. 4. Architecture of the tunable concurrent dual-band quad-beam phased-array receiver in CMOS.
`
`In the complete array system, a separate active antenna
`module, consisting of a broadband antenna and a GaN LNA,
`will be employedin front of the CMOSreceiver.
`
`IV. CMOS PHASED-ARRAY RECEIVER ELEMENT
`
`In this section, the architecture and frequency plan of the
`CMOSconcurrent phased-array receiver element is discussed
`in detail. It should be noted that a single receiver chip operates
`as one receiver elementin the array system, as shownin Fig. 3.
`
`A. Receiver Architecture
`
`A block diagram of the receiver architecture is presented in
`Fig. 4. Since it is a concurrent dual-bandreceiver, the incoming
`RF signal contains two frequencies at LB and HB respectively,
`and feeds a front-end tunable concurrent amplifier (TCA). The
`TCA amplifies, filters, and finally splits the RF signal into two
`separate outputs; one at LB and the other at HB. Each of the
`two signals goes through separate double down-conversion by
`subsequent RF and IF mixers. The IF mixers generate the I and
`Q components of the baseband signal for digital demodulation
`capability. The baseband VGAsadjust the baseband amplitude
`and drive the output load differentially.
`Thereare twosets of RF input (HP RF input and VP RF input
`in Fig. 4) which are down-converted by two samesets of the
`RF signal-path circuitry, respectively. Therefore, the receiver
`presents a total of eight differential baseband outputs, one for
`each combination of two different polarizations (HP and VP),
`two different frequency bands (LB and HB), and I and Q.
`
`The receiver includes two on-chip programmable frequency
`synthesizers in order to support the separate down-conversion
`of the LB and HBsignals, respectively. The frequency synthe-
`sizers generate the first LO (LO) signal between 5-7 GHz for
`LB and between 9-12 GHz for HB with a frequency step of
`200 MHz. The LO, signal drives the RF mixers for two po-
`larizations. The second LO (LOz2) signal, driving the phasero-
`tators and IF mixers, is generated by three static divide-by-2
`dividers and a 2:1 multiplexer. According to the receiver fre-
`quency schemediscussed in Section IV-B, the LO2 frequency
`is selected as either one half or one eighth of the LO, frequency
`by the multiplexer. The LO» signal carries the I and Q com-
`ponents separately to feed the phase rotators in quadrature. A
`50 MHzreference signal for the phase-locked loops (PLLs) is
`generated by an off-chip crystal oscillator.
`The LO phase-shifting architecture is adopted in this phased-
`array receiver in order to circumventthe challenge of designing
`high-resolution wideband phase shifters in the RF signal path
`[19]. The phase shifting is performed in the LO2 signal by a
`10-bit digital phase rotator. Each IF mixeris driven by a separate
`phase rotator to maximize the flexibility of the receiver. This
`not only provides the independent beamforming capability to
`the signals of different bands and polarizations, but also helps
`to minimize the I and Q mismatch of the quadrature baseband
`outputs.
`The receiver includes an on-chip digital serial-bus control
`unit that programs 170 bits to configure the dual RF frequen-
`cies, LO frequencies, phase-shifting angles, baseband gains, and
`
`

`

`2664
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
`
`RF (GHz)
`
`|1
`
`8
`
`|
`
`6
`
`Low band(LB)
`
`7.6
`
`|
`
`10.4
`
`High band (HB)
`
`13.5
`
`5-7GHz
`
`{}
`
`5-7GHz
`
` ({)
`
`9 - 12GHz
`
`9 - 12GHz
`
`LO:(
`
`LO2|
`
`
`
`LO,/8
`93 - 0.88 GHz
`
`LO,/2
`2.5 - 3.5 GHz
`
`LO,/8
`1.13 - 1.5 GHz
`
`LO,/2
`4.5 - 6.0 GHz
`
`Low-band (LB)
`amplifier
`
`|
`
`: V
`
`oito.B}
`
`Vbiti,.B}
`
`Vbitz,L6
`
`Fig. 5. Frequency scheme.
`
`RFinput
`(LB + HB)
`
`bennccncncnnncacce
`
`Impedance
`: transformation
`
`
`
`High-band (HB)
`amplifier
`
`
`
`Vbito.HB] Vit,HB
`
`Vpit2,HB
`
`Fig. 6. Schematic of the TCA with a single input and a dual output.
`
`other functionalities of the receiver. Bias voltages are generated
`by on-chip bandgapreferencecircuitry.
`
`B. Receiver Frequency Scheme
`
`The receiver supports a concurrent dual-band RF signal, such
`that two receive frequencies are tunable simultaneously and in-
`dependently, one from 6 to 10.4 GHz (LB) and the other from
`10.4 to 18 GHz (HB). As shownin Fig. 5, each bandis further
`divided into two sub-bands depending onthe corresponding IF
`frequency. Accordingly, the LO2 frequency switches between
`1/2 and 1/8 of the LO, frequency. For instance, a RF signal be-
`tween 5.625—7.875 GHz is down-converted to the IF between
`
`0.625—0.875 GHz by the LO; between 5—7 GHz. The LOz is
`then selected as 1/8 of LO; to down-convert the IF to the base-
`band. Onthe other hand, for a RF signal between 7.5—10.5 GHz,
`the LO, is selected as 1/2 of LO, to down-convert the IF be-
`tween 2.5—3.5 GHz to the baseband. In this way, the entire RF
`frequencies for LB (6—10.4 GHz) are covered without disconti-
`nuity and so are those for HB as well.
`With the dual-IF frequency scheme, the required VCO tuning
`range is reduced from 54% to 33% and 29% for LB and HB, re-
`spectively. This relaxed tuning range enablesusto further opti-
`mize the other VCO performancesuchas phase noise and power
`consumption [20].
`
`The RF channel spacing depends on which LO2 frequency
`schemeisselected at the given LO; frequency step (200 MHz).
`The channel spacing is 225 MHz whenoperatingin the 1/8 LO;
`scheme and 300 MHzin the 1/2 LO; scheme.
`
`V. CIRCUIT IMPLEMENTATION
`
`Thedetailed circuit design of the CMOSreceiveris presented
`in this section. Mostcircuit blocks including the mixers, base-
`band VGAs, VCOs, LO distribution buffers, and phase rota-
`tors use differential signaling while the TCA amplifies a single-
`endedsignal.
`
`A. Tunable Concurrent Amplifier (TCA)
`
`is split
`Since the incoming concurrent dual-band signal
`on-chip before the down-conversion, the front-end TCA must
`provide a single input and a dual output. Important design
`parameters in the TCA are the wideband input matching,
`noise figure, frequency tunability, and isolation between two
`different outputs. The single input port should provide a good
`input matching performanceoverthe entire tritave, from 6 to
`18 GHz. The two output ports present two separate signals well
`filtered at the desired frequencies that should be tunable over
`the entire LB and HB frequencies, respectively. Also, good
`isolation is needed between the two output ports in terms of
`
`

`

`JEONet al.: SCALABLE 6-TO-18 GHz CONCURRENT DUAL-BAND QUAD-BEAM PHASED-ARRAY RECEIVER IN CMOS
`
`2665
`
`BiasO
`
`BB out+ BB out—
`
`! BB int
`
`BB in—!
`
`
`Fig. 8. Baseband VGA.
`
`
`
`IF out+ IF out—
`(LB)
`(LB)
`
`
`
`
`IF out+ IF out—
`(HB)
`(HB)
`
`Vbias2
`
`Fig. 7. Schematic of the RF mixerand IF buffer for (a) LB and (b) HB.
`
`(b)
`
`Fig. 9. Schematic of the wideband VCO.
`
`signal and noise. Note that the noise figure requirementof the
`TCAis relaxed to a significant degree due to the low-noise
`active antenna module that will be deployed in front of the
`CMOSreceiverin the array system (Fig. 3).
`Throughan in-depth investigation of several potential topolo-
`gies, the TCA is implemented in a parallel cascode configura-
`tion with an active termination [21], as shown in Fig. 6. The
`cascode amplifiers not only enhance the isolation between the
`two output signals, but also minimizethe crosstalk of noise pro-
`duced bythe active blocks.
`The wideband input matching to 50 {2 is achieved by an ac-
`tive termination with shuntresistive feedback and an impedance
`transformation network. The active termination contributes less
`
`noise to the subsequent blocksthan a simple shuntresistive ter-
`mination [22].
`
`The RF signals at two frequencies are then selectively am-
`plified by two separate cascode amplifiers (M,—M>, M3-Mz)
`that have tunable LC output loads. A 3-bit switched capacitor
`bank at each output load is tuned to cover the entire LB and
`HBfrequencies. This allowsfor the digital tuning of the ampli-
`fier so that it can provide the maximumgain atthe desired fre-
`quency while attenuating out-of-band signals prior to the first
`down-conversion.
`
`B. Mixers
`
`Fourdifferent mixer designs are presented in the receiver; RF
`and IF mixers, each for LB and HB, respectively. The current-
`commutating double-balanced topology is adopted for all the
`mixers in order to minimize the LO-to-IF feedthrough. Fig. 7(a)
`shows the schematic of the RF mixer and IF buffer for LB. A
`
`shunt-peaking inductor (3.3 nH) is used to extend the IF 3-dB
`
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`Retime
`
`
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`2N
`
`P| (16 - 63) S|
`
`Fig. 10. Block diagram of the programmable PLL.
`
`LO from
`the frequency
`synthesizer
`
`Voutt
`
`Vint
`64
`
`Vo
`
`To the RF mixer or
`the phaserotator
`(HP)
`
`To the RF mixer or
`the phase rotator
`
`(VP)
`
`Fig. 11. LO distribution and buffers.
`
`bandwidth upto over 3.5 GHz. Since the TCA providesa single-
`ended RF signal to the differential RF mixers, one RF input
`terminal is terminated to a bias voltage by a 2-kQ resistor and a
`bypass capacitor.
`The HB RF mixer employs a tunable LC load with a 3-bit
`switched capacitor bankat the IF output, as shownin Fig. 7(b).
`The resonant frequency of the LC load is tuned in such a way
`that the conversion gain is maximized at the desired IF fre-
`quency. The common-modefeedbackcircuitry ensures a given
`bias voltage (Vpias) set for the subsequent buffer block.
`The schematic of the IF mixers for LB and HBaresimilar to
`that of the LB RF mixer. The difference is that the IF mixers em-
`ploy no shunt-peaking inductors and are degenerated by source
`resistors to improvelinearity of the basebandsignal.
`
`C. Baseband Variable-Gain Amplifier (VGA)
`
`The VGA combinesfive transconductance amplifiers in the
`current domain with digitally switched bias voltages (Fig. 8).
`TA, and TA, TAs and TA,are identical pairs that con-
`stitute current-commutating cells by digital switches (SW,
`
`and SW2). Each transconductance amplifier has a differential
`common-source topology with resistive degeneration. Since the
`output port is configured with open drains, the output signals
`from each array element can be easily combinedin the current
`domain using a passive network which imposeslittle additional
`impact on the nonlinearity performance. The open-drain output
`requires an external DC supply of 1.5 V. The VGAachieves a
`nominal gain of 7 dB with a 11 dB gain variation in five steps
`when driving a 100-2 differential output load.
`
`D. Voltage-Controlled Oscillator (VCO)
`
`Two separate LC VCOsare implemented to generate the LO
`signals for LB and HB, respectively. The schematic is shown
`in Fig. 9. A cross-coupled PMOSpair (M; and Mg) is used
`to improve the phase noise performancein the 1/f* region. In
`order to accomplish a widebandtuning range with relatively low
`VCOgain (resulting in low phase noise), a two-step frequency
`tuning mechanism is adopted [23]. The first coarse tuning is
`fulfilled by 2-bit binary-weighted MIM capacitors (Cyy4 and
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`JEONet al.: SCALABLE 6-TO-18 GHz CONCURRENT DUAL-BAND QUAD-BEAM PHASED-ARRAY RECEIVER IN CMOS
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`2667
`
`2Cwim) in the LC tank. Then, MOSvaractors (Cya,) are used
`for the further fine and continuous frequency tuning.
`Thebiascurrentis controlled digitally (S;—S3) to ensure that
`the VCO operates in the current-limited regime over the wide-
`bandtuning range. Thisis beneficial for further improvementof
`phase noise [24]. The simulated phase noise ranges from — 112
`to — 103 dBc/Hz and from — 108 to —94 dBc/Hz at 1-MHzoffset
`
`for the LB and HB VCOs, respectively.
`
`E. Phase-Locked Loop (PLL)
`
`Two fully-programmable PLLs are implemented to indepen-
`dently synthesize the LO frequenciesfor the two different bands
`[25]. Fig. 10 presents a block diagram of the PLL circuitry com-
`monly used for both LB and HB. The programmable dynamic
`divider takes one quarter of the VCO output frequency and pro-
`vides a further division ratio between 16 and 63. The divided
`
`outputis retimed to the dynamic divider input for noise improve-
`ment and feeds the phase-frequency detector (PFD). To reduce
`the outputjitter, a dead-zone elimination (DZE)circuitry is em-
`ployed, followed by a charge-pumpanda third-orderloopfilter
`to feed the VCOcontrol voltage. The core PLL circuitry draws
`34 mA at 1.2 V DC.
`
`F. Multiplexer
`
`Asthe receiver has a dual-IF frequency schemediscussed in
`Section IV-B, the LO2 frequency needs to switch between 1/8
`(LOz,,,) and 1/2 (LOx,,,) of the LO, frequency by a 2:1 mul-
`tiplexer. Two cascode transconductance stages, each driven by
`either LO2, js OF LO,, jo are combined in the current domain.
`Then,the output signal is selected between the two by comple-
`mentary switches that turn on or off the bias current of each
`transconductance stage. Two separate multiplexers are used for
`the I and Q components of the LOsignal.
`
`G. LO Distribution and Buffers
`
`The LO, and LOz signals generated from the frequency syn-
`thesizers are distributed to the RF mixers and the phaserota-
`tors, respectively, as shown in Fig. 11. Due to the high-level
`of integration in the single receiver chip, the LO distribution
`length becomesas long as 3.7 mm in the worst case (the LO,
`distribution for LB). The LO buffers need to compensate for
`the insertion loss and bandwidth limitation caused by the long
`signal distribution. Each path of the LO distribution includes a
`two-stage buffer, whichis a self-biased cascode asthefirst stage
`followed by a common-source amplifier with shunt peaking.
`The shunt-peaking inductanceis carefully chosen, such that the
`3 dB bandwidth is higher than the maximum LOfrequency in
`the distribution without raising a significant gain peaking and
`instability issue [26].
`The transmission line used for the LO distribution is imple-
`mented by a grounded differential coplanar waveguide (CPW)
`structure, shown in Fig. 11. In order to minimizethe insertion
`loss, the top thick metal layer (4-j4m aluminum)is used for the
`signal lines (S+ and S—). The simulated insertion loss of the
`CPW with Zoaq = 50 Q is 0.35 dB per mm at the highest LO
`frequency, i.e., 12 GHz. The side and bottom groundplanes im-
`prove the isolation between adjacent LO signals in distribution
`[27].
`
`5-bit gain control (A)
`
`at
`COS(oat)
`QD
`sin(@ozt) P|
`
`eo°
`
`A\Cos(ozt)
`+ Agsin(@o2t)
`
`Sin(@o2f)
`
`AQl
`:
`:
`
`
`
`COS( oz)
`
`5-bit gain control (Ag)
`
`(a) Block diagram of the 10-bit digital phase rotator. (b) Unit current-
`Fig. 12.
`commutating cell.
`
`H. Phase Rotator
`
`A block diagram of the digital linear phase rotator is shown
`in Fig. 12(a). It takes the I and Q components of the LO» signal
`as an input and applies a different gain (A; and Aq) indepen-
`dently to each of them using two digitally-controlled VGAs
`[28]. By adding the two VGA outputs in the current domain,
`the desired phase (Your) and amplitude (Aout) can be inter-
`polated in the Cartesian coordinates of the I and Q outputs.
`Each VGAis implemented by combining five binary-weighted
`current-commutating cells. Fig. 12(b) shows the schematic of
`a unit current-commutating cell. M;—My,are transconductance
`transistors with identical dimensions. The output signal (Out+
`and Out—) changesits polarity depending on the bias control
`bit (Vpit). This full-scale current-commutating scheme makes
`the phase interpolating performanceless vulnerable to the PVT
`(process, voltage, and temperature) variations.
`Sincefive bits are assigned to each VGA,the phaserotatoris
`able to interpolate 1024 (21°) different points over all the four
`
`

`

`Phaserotators
`+IF mixers
`(HP, LB)
`
`Phaserotators
`+IF mixers
`(VP, LB)
`
`
`
`
`
`Phaserotators
`Phaserotators
`
`+IF mixers
`+IF mixers
`(HP, HB)
`(VP, HB)
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
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`VP: Vertical polarization
`LB: Low band
`HB: High band
`
`LB Freq.
`
`Baseband
`buffers (HP)
`
`Baseband
`buffers (VP)
`
`HP: Horizont