1218
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 5, MAY 2008
`
`Resistive-Feedback CMOS Low-Noise
`
`Amplifiers for Multiband Applications
`
`Bevin G. Perumana, Student Member, IEEE, Jing-Hong C. Zhan, Member, IEEE, Stewart S. Taylor, Fellow, IEEE,
`Brent R. Carlton, Member, IEEE, and Joy Laskar, Fellow, IEEE
`
`resistive-feedback CMOS
`compact
`Abstract—Extremely
`low-noise amplifiers (LNAs) are presented as a cost-effective
`alternative to multiple narrowband LNAs using high-Q inductors
`for multiband wireless applications. Limited linearity and high
`power consumption of the inductorless resistive-feedback LNAs
`are analyzed and circuit techniques are proposed to solve these
`issues. A 12-mW resistive-feedback LNA, based on current-reuse
`transconductance boosting is presented with a gain of 21 dB and
`a noise figure (NF) of 2.6 dB at 5 GHz. The LNA achieves an
`output third-order intercept point (1P3) of 12.3 dBm at 5 GHz by
`reducing loop-gain rolloff and by improving linearity of individual
`stages. The active die area of the LNA is only 0.012 mm2 .
`A 9.2-mW tuned resistive-feedback LNA utilizing a single com-
`pact low-Q on-chip inductor is presented, showing an improved
`tradeoff between performance, power consumption, and die area.
`At 5.5 GHz, the fully integrated LNA achieves a measured gain
`of 24 dB, an NF of 2 dB, and an output 1P3 of 21.5 dBm. The
`LNA draws 7.7 mA from the 1.2-V supply and has a 3-dB band-
`width of 3.94 GHz (4.04—7.98 GHz). The LNA occupies a die area
`of 0.022 mm2. Both LNAs are implemented in a 90-nm CMOS
`process and do not require any costly RF enhancement options.
`
`Index Terms—CMOS low-noise amplifier (LNA), feedback am-
`plifiers, multiband wireless receivers.
`
`I.
`
`INTRODUCTION
`
`OW-NOISE amplifiers (LNAs) occupy a significant per-
`L centage of the total die area in wireless front-ends today.
`This is because the performance of the LNA is dependent on the
`Q’s of the multiple on-chip inductors. Since the area require-
`ment of high-Q on-chip inductors is high, the die area occu-
`pied by the LNA is also high. Often, costly process steps are
`required to enhance the Q of the on-chip inductors to further
`improve the performance of RF circuits. The design of these
`circuits usually requires a higher number of simulation and veri-
`fication iterations. Cascode amplifiers with inductive source de-
`generation [l], the predominant LNA implementation used in
`
`Manuscript received September 1, 2007; revised January 18, 2008.
`B. G. Perumana was with the Communications Circuits Laboratory, Intel Cor-
`poration, Hillsboro, OR 97124 USA. He is now with the Georgia Electronic De-
`sign Center, School of Electrical and Computer Engineering, Georgia Institute
`of Technology, Atlanta, GA 30332 USA (e-mail: beving@ece.gatech.edu).
`J.-H. C. Zhan was with the Communications Circuits Laboratory, Intel Corpo-
`ration, Hillsboro, OR 97124 USA. He is now with the RF Division, MediaTek,
`HsinChu, 300 Taiwan, R.O.C.
`S. S. Taylor and B. R. Carlton are with the Communications Circuits Labo-
`ratory, Intel Corporation, Hillsboro, OR 97124 USA.
`J. Laskar is with the Georgia Electronic Design Center, School of Electrical
`and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
`USA.
`Color versions of one or more of the figures in this paper are available online
`at http://ieeexplore.ieee.org.
`Digital Object Identifier 10.1109/TMTT.2008.920181
`
`Mum-Band Antenna
`
`Multi-Band I
`Mde-Band LNA
`
`
`
`Fig. 1. Multiband receiver implementation using a multiband/wideband LNA.
`
`Band 1
`
`Wide-Band Mixer
`
`
`
`Fig. 2. Multiband receiver implementation using multiple narrowband LNAs.
`
`CMOS wireless front-ends, require three high-Q inductors for
`achieving input impedance matching, high gain, and low noise
`figure (NF). In spite of the high die area requirements, cascode
`LNAs have been used extensively in narrowband wireless ap-
`plications because they provide high gain, low noise, and high
`linearity at relatively low power consumption. With the advent
`of multiple-input multiple-output (MIMO), multistandard, and
`multiband wireless systems; however, the use of the area inten-
`sive cascode LNAs is becoming increasingly expensive, leading
`to the pursuit of alternative LNA implementations.
`A multiband receiver can be implemented by using a single
`multiband or wideband LNA, as shown in Fig. l . Cascode LNAs
`based on inductive source degeneration are not suitable for this
`implementation since it is extremely difficult to switch the three
`on-chip inductors to make the same cascode LNA work across
`all the required frequency bands without compromising perfor-
`mance. Multiband receivers can also be implemented by using
`multiple narrowband LNAs, each designed for a different fre-
`quency band, as shown in Fig. 2. If cascode LNAs with induc-
`tive degeneration are used for this implementation, the die area
`and cost will both be prohibitively high.
`Inductorless resistive-feedback CMOS LNAs [2]—[4] have
`been shown to be a viable option for implementing multiband
`receivers, as shown in Fig. 1. These circuits require very small
`die area and can be implemented in a digital CMOS process
`without any additional RF enhancements. Hence, this approach
`can potentially significantly reduce the cost of the wireless
`front-end implementation. Resistive-feedback LNAs achieve
`
`0018-9480/$25.00 © 2008 IEEE
`
`INTEL 1008
`
`

`

`PERUMANA et al.: RESISTIVE-FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1219
`
`
`
`the shunt—shunt feedback. R5 is the source resistance and
`R31 is used for biasing along with do blocking capacitors
`031,6'32, and 033. The equivalent small-signal model of
`the transimpedance amplifier is shown in Fig. 3(b), where gm
`
`represents the transconductance of M1. Cgs represents the
`capacitance to ground at the gate of M1. For frequencies well
`below 1/ (ZTCgSRs), the effect of Cgs can be neglected.
`
`(b)
`
`A. Voltage Gain
`
`(a)
`
`Fig. 3. Simplified schematic and small-signal model of a shunt-shunt feedback
`amplifier.
`
`high gain and reasonably low NF [4]. However, novel circuit
`techniques are required to reduce power consumption and
`improve linearity.
`This paper presents an inductorless resistive-feedback LNA
`in which a current-reuse transconductance-boosting technique
`[5] is utilized to reduce the power consumption to 12 mW. The
`LNA has a gain of 21 dB and an NF of 2.6 dB at 5 GHz. The
`active die area of this circuit is only 0.012 mm2. The combi-
`nation of small die area, broad bandwidth and moderate power
`consumption make this LNA architecture suitable for low-cost
`multistandard wireless front-ends, as shown in Fig. 1. By main-
`taining a moderate loop-gain across the frequency band and re-
`ducing the nonlinearities of individual stages, the LNA achieves
`an output third-order intercept point (IP3) of 12.3 dBm at 5 GHz.
`Techniques to further improve IP3 by nonlinearity cancellation
`[6]—[9] are also presented.
`A resistive-feedback cascode LNA using a single com-
`pact on-chip load inductor is presented next. It has a max-
`imum gain of 24.4 dB, and a 3-dB bandwidth of 3.94 GHz
`(4.04—7.98 GHz). At 5.5 GHz, the NF is 2 dB, and the output
`IP3 is 21.5 dBm. Since the inductor Q is not required to be
`high, the area of this LNA is only 0.022 mm2. This makes it
`suitable for multiband receiver implementations, as shown in
`Fig. 2. This LNA can also be easily modified to operate across
`multiple frequency bands (as in Fig. 1) since the single low-Q
`tuned load can be switched to resonate at different frequencies.
`The gain,
`input
`impedance, NF, and linearity of resis-
`tive-feedback LNAs are discussed in Section II. Section III
`
`describes circuit techniques to improve linearity and lower
`power consumption. The design of the inductorless LNA
`with current-reuse transconductance boosting and the tuned
`resistive-feedback LNA (using a compact low-Q inductor) are
`described in Section III. The implementation details of these
`circuits are discussed in Section IV. The measurement results of
`
`both the LNAs are given in Section V along with performance
`comparison to other reported circuits. Finally, conclusions are
`presented in Section VI.
`
`11. RESISTIVE-FEEDBACK LNA THEORY
`
`Consider a simplified resistive-feedback amplifier, as shown
`in Fig. 3(a). M1 represents the input transconductance device,
`which could be a single transistor or a cascode pair. RL repre-
`sents the load resistance including the output resistance of the
`input transconductance stage. RF is the resistor implementing
`
`Using the small-signal model in Fig. 3(b), the voltage gain of
`the amplifier can be derived as
`
`'Uout
`
`AU 2
`
`u...
`
`= —
`
`(g
`
`1
`m — — R R .
`
`RF)( L” F)
`
`1
`
`()
`
`Feedback analysis [10] can be done by opening the loop and
`determining the open-loop transresistance gain (a) and the feed-
`back factor (f), shown as follows:
`
`a = —(RS || RF)9m(RL || RF)
`1
`f = _—RF.
`
`The voltage gain given by feedback analysis is
`
`Av(Feedback Theory) : _gm(RL ll RF)
`
`(2)
`
`(3)
`
`(4)
`
`The discrepancy between (1) and (4) is because the feedfor—
`ward path through RF is ignored in the feedback analysis. This
`difference is negligible if gm >> 1/RF.
`
`B. Input Impedance Matching
`
`Shunt—shunt feedback reduces the input impedance of the
`amplifier by a factor of (1 + a f ) The input resistance (Rm)
`of the amplifier is given by
`
`
`R : (RS IIRF) N RS
`m
`1+af
`1+af
`
`(5)
`
`since RF > R5 (for reasons related to NF, which will ex-
`plained later). For input impedance matching, Rm has to be
`equal to Rs / 2. From (5), input matching is achieved with a
`loop gain (a f ) just below 1, which also ensures circuit sta-
`bility. Using (3), the open-loop transresistance gain has to be
`approximately equal to the value of the feedback resistance for
`achieving input impedance matching
`
`Input Impedance Match Condition: |a| 3 RF.
`
`(6)
`
`C. NF
`
`The contribution of each noise source to the total output noise
`is evaluated. The NF is then calculated by evaluating the ratio of
`the total output noise to the output noise due to Rs as follows:
`
`79m
`
`NF 2 1+
`
`1
`+ —
`RSRLQEn
`
`Rng
`
`2
`
`—1
`4R5
`_ — 7
`+ RF
`1 +
`RF + RS
`(
`
`)
`
`

`

`1 220
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 5, MAY 2008
`
`where 71;... is the noise excess factor of M1 [11]. Equation (7)
`shows that having a large feedback resistance can lower the NF.
`From (6), a higher RF requires a higher open-loop gain for input
`matching, usually leading to higher power consumption.
`
`D. Linearity
`
`Consider a nonlinear amplifier modeled by the power series
`[12]
`
`3
`2
`_
`vout — alvin + 112% + aavin.
`
`(8)
`
`
`
`Negative feedback improves its input 1P3 by the following
`factor:
`
`Fig. 4. Schematic of the current-reuse transconductance-boosting resis-
`tive-feedback LNA.
`
`
`
`w (1 + MD”
`
`(9)
`
`where 2fa§ << (13(1 + a1 f), IP3|CL, and IP3|OL represent the
`close-loop and open-loop 1P3, respectively. Equation (9) shows
`that linearity is not significantly improved by feedback at high
`frequencies if the open-loop gain of the amplifier rolls off [2].
`
`III. LOW-POWER HIGH-LINEARITY
`RESISTIVE—FEEDBACK LNAs
`
`As discussed in Section II, a high open-loop gain is required
`to simultaneously achieve low NF and good input matching.
`The open-loop bandwidth also has to be high to achieve high
`linearity at high frequencies. These requirements usually lead
`to high power consumptions in resistive-feedback LNAs [2],
`[4]. We now present circuit techniques to improve linearity and
`lower power consumption in resistive-feedback LNAs.
`
`A. Current-Reuse Resistive-Feedback LNA
`
`The schematic of the restive feedback LNA with current-
`
`reuse transconductance boosting is shown in Fig. 4. Cascode
`transistors M1 and M3 form the input transconductance stage.
`A significant portion of the bias current in M1 is diverted away
`from the load resistor RL by transistor M2. This reduces the dc
`voltage drop across RL. Moreover, the transconductance gener-
`ated by M2 adds to that of M1 , increasing the effective gm of the
`input stage. The current mirror formed by M7 and M8 controls
`the amount of current shunted away from BL. The amplified
`signal is fed back to the input transconductance stage through
`feedback resistor RF and the source follower formed by M4,
`M5, and R1. The diode connected M5 is used in the source fol-
`lower to generate gate bias voltages for M1, M2, and M3. The
`dc and ac feedback loops are thus combined, making it possible
`to remove the dc blocking capacitors required in earlier reports
`[4]. This reduces the total area requirement, and avoids loading
`of the source follower by the parasitic capacitance of the dc
`blocking capacitor to the substrate. The latter improves the LNA
`linearity. An additional source follower, formed by M6 and R2,
`is incorporated to improve reverse isolation and output driving
`capability. As discussed in Section II, the linearity at high fre-
`quencies can be improved by increasing open-loop bandwidth.
`This is achieved by device sizing and reducing layout para-
`sitics as much as possible. The overall linearity of the LNA is
`
`improved by making each block of the LNA more linear. Re-
`moving the dc block capacitors reduces the loading of the source
`follower, making it more linear, as explained earlier. Resistors
`R1 and R2 replace active current mirrors, which are nonlinear
`and have greater capacitance.
`In all resistive-feedback LNAs with gm-enhanced cascode
`structure, the width/length (W/L) ratio of the cascode transistor
`is kept low to achieve a higher bandwidth. The cascode device
`also has a lower bias current than the input transistor so as to re-
`duce the voltage drop across the load resistor, as explained ear-
`lier. The lower W/L ratio and bias current makes the transcon-
`
`ductance of the common-gate cascode transistor significantly
`lower than the common-source input transistor. The gain of the
`common-source stage is the ratio of these transconductances.
`The high gain in the common-source input stage preceding the
`cascode stage makes the gm nonlinearity in the cascode stage
`limit the overall circuit linearity. This is because the IIP3 of
`the combined stages (IIP3CS_Cg) is related to the IIP3 of the
`common-source stage (1113305), its gain (Gog), and the IIP3 of
`the common-gate stage (IIP30G) by the following equation:
`
`
`1
`_
`1
`+
`003
`(IIP3CS_CG)2 _ (IIP3CS)2
`IIP3CG
`
`2
`
`(10)
`
`Hence, significant improvement in linearity can be obtained
`if the nonlinearity of the cascode stage is reduced by nonlin-
`earity cancellation. This can be achieved by using derivative
`superposition [6], [13], as shown in Fig. 5(a). Here, the gmg
`(63]D /6Vés) of the common-gate stage (M3) is cancelled
`by the gmg of the subthreshold transistor M6. The measured
`input 1P3 of the gm -enhanced cascode LNA is plotted against
`the gate voltage of M3 (V0) in Fig. 5(b). Though significant
`improvements in 1P3 have been demonstrated with derivative
`superposition at the cost of increased NF (no.6 dB) [9], such
`cancellation techniques may have potential issues in volume
`applications due to process and temperature variations.
`
`B. Tuned Resistive-Feedback LNA with a Compact
`Low-Q Load Inductor
`
`Linearity issues due to the high gain in the common-source
`stage preceding the common-gate cascode stage can be avoided
`by replacing the load resistance with a low-Q resonant load,
`
`

`

`PERUMANA et al.: RESISTIVE-FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1221
`
`IP3(dBm)
`
`Input
`
`
`
`
`
`0.2 0.4 0.6 0.8
`
`1
`
`1.2
`
`(a)
`
`Vc(V)
`(b)
`
`Fig. 5. Nonlinearity cancellation in a 9m -enhanced cascode LNA with deriva-
`tive superposition.
`
`
`
` Low-Q Inductor
`
`Fig. 6. Schematic of the tuned resistive-feedback LNA utilizing a compact
`low-Q load inductor.
`
`using a compact on-chip inductor. The bias current of the cas-
`code device can be made equal to that of the input device be-
`cause the dc voltage drop across the resonant load is negligible.
`Since all the capacitance at the output node can be resonated out
`with the inductive load, it is not necessary to make the W/L ratio
`of the cascode device small.
`The schematic of a tuned resistive-feedback LNA is shown in
`
`Fig. 6. Transistor M1 is used as the common-source transcon-
`ductance stage and M2 is used as the cascode common-gate
`stage. A compact low-Q on—chip spiral inductor L1 and the total
`capacitance at the output node form the resonant load. The par-
`asitic capacitance of the dc block capacitors (002 and Cog) to
`substrate and the drain capacitance of M2 can, therefore, be res-
`onated out along with the load capacitance at the output node.
`Resistors RFBl, RFBz, and RFB3 form the shunt-shunt feed-
`back path. Capacitors 031 and C132 and resistor RB1 are used
`for biasing the cascode transistors.
`Since this LNA utilizes only a single low-Q load inductor,
`it can be made extremely compact. Hence, low-cost multiband
`receivers can be implemented by using multiple tuned resistive-
`feedback LNAs each designed for a different frequency band,
`as shown in Fig. 2.
`This circuit can be easily modified to operate across different
`frequency bands for the multiband receiver implementation
`
`
`
`
`
`Fig. 7. Schematic of the modified super source follower output buffer.
`
`shown in Fig. 1. The band-switching scheme enabling this
`implementation is shown in Fig. 6. The resonant frequency
`f. can be shifted by using the capacitors Cl and 02 and the
`switches 301 and Sag. At resonance, the load impedance is
`purely resistive and given by
`
`RL,f7° : 27Tf7°Lfr (er +
`
`
`1
`
`er
`
`> -
`
`(11)
`
`Here, Lf,. and Q fr are the inductance and Q of the load inductor
`at the resonant frequency fr. All the equations from Section II
`are still valid if BL is replaced by RL7fr, and if gm represents
`the effective transconductance of the cascode stage.
`If the switches 501 and 502 are used to shift fr, the value of
`RL7fr, given by (11), will not be the same in different frequency
`bands. Thus,
`the open-loop transimpedance gain (a) given
`by (2), will also vary from one frequency band to another.
`To satisfy the input matching condition in (6) across all the
`frequency bands, the feedback resistance RFB will also have to
`be switched, as shown in Fig. 6, using switches SR1 and 532.
`
`IV.
`
`IMPLEMENTATION OF THE RESISTIVE—FEEDBACK LNAs
`
`Both of the resistive-feedback LNAs are implemented in a
`90-nm seven-metal CMOS process. The only RF enhancement
`option used is the high-resistivity substrate under RF signal
`paths. All the capacitors were implemented as inter-digitated
`metal finger capacitors. Since the output impedance of the
`LNAs are not 50 Q, a modified super source follower [4] was
`used to facilitate measurements. The schematic of this circuit is
`
`shown in Fig. 7.
`The current-reuse transconductance-boosting resistive-feed-
`back LNA draws 6.7 mA from the 1.8—V supply, thus consuming
`12 mW of power. The chip micrograph of this LNA is shown in
`Fig. 8. The chip is pad limited and the actual LNA dimensions
`are 40 um x 310 Mm (Area: 0.012 mg). This implementation
`is a very low-cost alternative to the conventional inductor-based
`circuits for multiband multistandard radios.
`
`The tuned resistive-feedback LNA has a power consump-
`tion of 9.2 mW, drawing 7.7 mA from the 1.2-V supply. Band
`switching is not implemented and the LNA is designed to op-
`erate in a single frequency band around 5.5 GHz. The chip mi-
`crograph of this circuit is shown in Fig. 9. The LNA dimensions
`are 155 pm X 145 um (Area: 0.022 mm2).
`
`

`

`1 222
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 5, MAY 2008
`
`35
`
`.
`
`
`
`- -LNA Measured Gain (dB)
`--1--Buffer Measured Loss (dB)
`-0-LNA+Buf Measured Gain (dB)
`----- LNA+Buffer Simulated Gain (dB)
`
`,
`
`A 30 »
`%
`‘5 25
`
`20
`
`O i
`
`O=
`
`
`
`._
`g 10 .
`E 5 .....................r-.--q---n---n--Aei-i'*l
`
`'5 15
`c:
`Q,
`
`0
`
`0.6 0.8 1
`
`3
`
`5
`
`7
`
`9
`
`Frequency (GHz)
`
`Fig. 10. Measured and simulated gain of the current-reuse transconductance-
`boosting resistive-feedback LNA and output buffer.
`
`
`
`
`j - -Measured 811 (dB)
`
`
`I - - 'Simulated 511 (dB)
`
`511(dB)
`
`'8
`
`
` : _"'
`_15 ~———————
`
`
`i—-20 '
`
`0.6 0.8 1
`
`3
`
`5
`
`7
`
`9
`
`Frequency (GHz)
`
`Fig. 11. Measured and simulated input matching of the resistive-feedback
`LNA.
`
`
`
`—Measured LNA Noise Figure (dB)
`45 , — Measured LNA+Bufter Noise Figure $ng .
`-----Simulated LNA+Buffer Noise Figure dB
`
`
`
`
`
`
`
`NoiseFigure(dB)
`
`Frequency (GHz)
`
`Fig. 12. Measured and simulated NF of the LNA and output buffer.
`
`The input 1P3 of the LNA is plotted in Fig. 13 after deembed-
`ding the effects of the output buffer. It varies from —2.3 dBm at
`500 MHZ to —8.8 dBm at 5.8 GHz. The degradation of linearity
`
`
`
`Fig. 8. Chip micrograph of the current-reuse transconductance-boosting resis-
`tive-feedback LNA.
`
`
`
`
`
`Fig. 9. Chip micrograph of the tuned resistive-feedback LNA.
`
`V. MEASUREMENT RESULTS
`
`The measurements for both of the resistive-feedback LNAs
`
`were performed with on-wafer probing. Standalone output
`buffers were measured to deembed their effect on the measure-
`ment results of the LNAs.
`
`A. Measurement Results of the Current-Reuse
`Resistive-Feedback LNA
`
`The standalone output buffer used with the current-reuse
`transconductance boosting LNA has an insertion loss of 7 dB.
`Its input IP3 is 15.6 dBm at 5.8 GHZ, 18 dBm at 5 GHZ, and
`higher at lower frequencies. The buffer NF is 10 dB, including
`the noise added by a 50-9 resistor added at the input for
`impedance matching.
`The measured and simulated gain of the LNA and output
`buffer is shown in Fig. 10. Also plotted in Fig. 10 are the buffer
`loss and the deembedded LNA gain. The gain falls from 22 dB
`at low frequencies to 21 dB at 5 GHz. The 3-dB bandwidth is
`7.5 GHz.
`
`The measured and simulated input matching of the LNA are
`plotted in Fig. 11. It is —10 dB at 5 GHz and better at lower
`frequencies. The measured NF is plotted against frequency
`in Fig. 12. The NF is 2.6 dB at 5 GHz and varies between
`2.3—2.9 dB from 500 MHz to 7 GHz. The 1.5-dB increase in
`
`gain in the measured results is due to slightly higher values
`for RL and RF. This increase in gain leads to improved input
`matching and noise performance compared to the simulated
`results.
`
`

`

`PERUMANA et al.: RESISTIVE—FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1223
`
`
`
`IIP3(dBm)
`
`— —LNA IIP3
`
`
`
`
`-4 \
`-5 \
`
`
`
`
`0.6
`
`0.8
`
`1
`
`3
`
`5
`
`7
`
`9
`
`Frequency (GHz)
`
`i
`
`2
`
`3
`
`is
`5
`4
`Frequency (GHz)
`
`7'
`
`s
`
`9
`
`Fig. 13. Measured input IP3 of the current-reuse transconductance-boosting
`LNA.
`
`Fig. 15. Measured and simulated input matching of the tuned LNA.
`
`
`
`35 .
`
`30 ,
`
`25
`
`20
`
`.
`
`
`
`- -LNA Measured Gain (dB)
`--1--Buffer Measured Loss dB)
`+LNA+Buffer Measured ain (dB)
`----- LNA+Bulfer Simulated Gain (dB)
`/
`'\
`/ /<—3-dB BW —\> ~
`
`
`
`VoltageGainorLoss(dB)
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`Frequency (GHz)
`
`Fig. 14. Measured and simulated gain of the tuned resistive-feedback LNA and
`output buffer.
`
`with frequency is due to the loop gain rolloff with frequency, as
`explained earlier.
`
`B. Measurement Results of the Tuned Resistive-Feedback LNA
`
`The standalone output buffer used with the tuned resistive-
`feedback LNA is similar to the one used with the current-reuse
`
`LNA and has a loss of 8 dB, and an NF of 9.8 dB (including the
`noise added by the 50-9 resistor at the input). The output buffer
`has an input l-dB compression point of 6.5 dBm and an input
`IP3 of 18 dBm at 5.5 GHZ.
`
`The measured and simulated gain of the LNA and output
`buffer is plotted in Fig. 14. The buffer loss and the deembedded
`gain of the LNA without the buffer are also plotted in Fig. 14.
`The LNA has a maximum gain of 24.4 dB and a 3-dB band-
`width of 3.94 GHz from 4.04 to 7.98 GHZ. The measured input
`matching is plotted in Fig. 15. The input matching is better than
`— 10 dB from 5 to 6.85 GHZ.
`
`Fig. 16 shows the measured and simulated NF of the tuned
`resistive-feedback LNA and the output buffer. The deembedded
`NF of the LNA without the output buffer is also plotted. The
`tuned resistive-feedback LNA has an NF of approximately 2 dB
`between 4—6 GHZ.
`
`The IP3 of the LNA and output buffer is plotted in Fig. 17.
`The input IP3 of the tuned resistive-feedback LNA and output
`
`‘
`
`0 ’
`l:
`" ‘ - ~ - _ v
`-5 e
`
`V
`
`A
`3":
`v-
`5
`
`-10
`
`-15 e
`
`-20
`
`-25 »
`
`-30
`
`- -Measured 511 (dB)
`----- Simulated S11 (dB)
`-'
`".""(N 2
`I.
`I
`,- f
`,-
`.'
`
`‘
`
`i
`
`'u
`I
`‘-.\
`II.
`I:
`.
`".
`'-..-'w
`t
`
`—Measured LNA Noise Figure (dB)
`—Measured LNA+Buffer Noise Figure (dB)
`----- Simulated LNA+Buffer Noise Figure (dB)
`
`(dB)
`
`NoiseFigure
`
`‘
`
`Frequency (GHz)
`
`Fig. 16. Measured and simulated NF of the tuned resistive-feedback LNA and
`output buffer.
`
`20
`
`.
`
`.
`
`.
`
`,
`
`:
`
`.
`
`A 0 7
`g
`d.)
`‘: -20
`g
`8..
`3D.
`‘5
`° -60
`
`-4o
`
`1‘ ' ‘ I ‘1‘
`
`v T
`
`a
`
`_______ " :
`I,
`
`,
`
`I
`
`
`
`-80
`-4o
`
`-35
`
`-é.o
`
`"
`
`.'
`
`-
`5
`Input IP3 = -7.7 dBm g
`( \:
`-15
`4'0.
`-2o
`:25
`Input Power (dBm)
`
`45
`
`0
`
`Fig. 17.
`
`Input [P3 of the tuned resistive—feedback LNA.
`
`buffer is —7.7 dBm at 5.5 GHZ. The IIP3 of the LNA is found to
`
`be —2.6 dBm after deembedding the output buffer nonlinearity
`using the IIP3 of the standalone buffer (18 dBm) and the gain
`of the LNA (24.1 dB). Therefore, the output IP3 of the LNA
`is 21.5 dBm. The measured input l-dB compression point of
`the LNA and buffer is — 18 dBm at 5.5 GHZ. The input l-dB
`compression point of the LNA without the output buffer is found
`to be —7.2 dBm after deembedding.
`
`

`

`1 224
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 5, MAY 2008
`
`TABLE I
`WIDEBAND LNA PERFORMANCE COMPARISON
`
`consumption makes this LNA architecture a compelling choice
`for low-cost multistandard wireless front-ends.
`
`This Work
`Current-Reuse Tuned
`
`LNA LNA
`
`90-nm
`90-nm
`CMOS
`Process CMOS
`
`
`
`Freq.
`4-8
`
`(GHz)
`0.5 — 7
`
`Power
`(mW)
`
`
`
`
`
`
`Area
`(mmz)
`
`Voltage
`Gain
`
`(dB)
`Noise
`Figure
`((113)
`
`OIP3
`(dBm)
`
`8.8 (5.8
`GHZ)
`
`7 (5
`GHZ)
`
`The performance of the two resistive-feedback LNAs are
`tabulated and compared with others reported in Table I. The
`current-reuse
`transconductance-boosting resistive-feedback
`LNA provides comparable performance at lower power con-
`sumption while occupying very small die area. The tuned
`resistive-feedback LNA, though requiring slightly larger die
`area than the inductorless LNA, provides very high linearity,
`low noise, and high gain while dissipating low power. This
`LNA presents a much improved tradeoff between performance,
`power consumption, and cost, especially for multiband multi-
`standard wireless receivers.
`
`VI. CONCLUSION
`
`Extremely compact LNA circuits based on resistive feedback
`are presented as a cost-effective alternative to multiple tuned
`LNAs requiring many high-Q inductors for multiband wireless
`applications. The relationships between the feedback resistance,
`NF, input matching, and open-loop gain are presented. The ef-
`fect of the open-loop bandwidth on the close-loop linearity is
`also explained. A current-reuse transconductance boosting tech-
`nique is used to reduce the power consumption in a resistive-
`feedback LNA to 12 mW. The inductorless LNA achieves a gain
`of 21 dB and an NF of 2.6 dB at 5 GHz. The rolloff of loop
`gain and the nonlinearities in the feedback loop are reduced to
`improve the output IP3 to 12.3 dBm at 5 GHz. The active die
`area of this LNA is only 0.012 mm2. A tuned resistive-feed-
`back LNA, using a compact resonant load, is also presented.
`It achieves a maximum gain of 24.4 dB and a 3-dB bandwidth
`of 3.94 GHz using a single low-Q on-chip inductor and con-
`suming 9.2 mW of power. The LNA has an active die area of
`0.022 mm2. The NF of the tuned resistive-feedback LNA is ap-
`proximately 2 dB between 4—6 GHz. At 5.5 GHz, the LNA has
`an output IP3 of 21.5 dBm. The combination of high linearity,
`low NF, high broadband gain, small die area, and low power
`
`ACKNOWLEDGMENT
`
`The authors would like to thank the following colleagues
`at the Communication Circuit Laboratory, Intel Corporation,
`Hillsboro, OR: D. Steele for layout assistance; R. Bishop for
`measurement setup, J. S. Duster
`for useful discussions; and
`K. Soumyanath for support and encouragement.
`
`REFERENCES
`
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`[10] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
`Design ofAnalog Integrated Circuits, 4th ed. New York: Wiley, 2001.
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`
`
`
`Bevin G. Perumana (8’04) was born in Kerala,
`India, in 1980. He received the B.Tech. degree in
`electrical engineering from the Indian Institute of
`Technology, Kharagpur, India, in 2002, the M.S. de-
`gree in electrical engineering from Georgia Institute
`of Technology, Atlanta,
`in 2005, and is currently
`working toward the Ph.D. degree in electrical and
`computer engineering at the Georgia Institute of
`Technology. His doctoral dissertation concerns
`low-power CMOS front-ends for wireless personal
`area networks.
`
`

`

`PERUMANA et al.: RESISTIVE—FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1225
`
`From 2002 to 2003, he was a Research Consultant with the Advanced Very
`Large Scale Integration (VLSI) Design Laboratory, Indian Institute of Tech-
`nology, Kharagpur, India. From 2003 to 2005, he was a Graduate Research
`Assistant with the Microwave Application Group, Georgia Electronic Design
`Center, Georgia Institute of Technology. From 2005 to 2006, he was an Intern
`with the Communication Circuits Laboratory, Intel Corporation, Hillsboro, OR.
`
`
`
`Jing-Hong C. Zhan (S’977M’04) received the B.S.
`and M.S. degrees in electrical engineering from
`Tsing-Hua University, HsinChu, Taiwan, R.O.C., in
`1996 and 1997, respectively, and the Ph.D. degree
`in electrical engineering and computer science in
`Cornell University, Ithaca, NY, in 2004. His M.S.
`thesis concerned side-polished fiber fabrication and
`theoretical analysis. His doctoral research focused on
`voltage-controlled oscillator (VCO) and high-speed
`clock and data recovery circuitry using BiCMOS
`and CMOS.
`Upon completion of compulsory services with the Taiwanese Army, where
`he served as a Secondary Lieutenant from 1997 to 1999, he joined MediaTek,
`HsinChu, Taiwan, R.O.C., where he was a Logic Design Engineer until 2001.
`He developed the data path and spindle motor control circuitry for MediaTek’s
`optical storage products. In 2004, hejoined the Communications Circuit Labora-
`tory, Intel Corporation, Hillsboro, OR, where he was a Senior Design Engineer.
`His research focused on fabricating low-cost radios on CMOS technologies for