1218
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES,VOL. 56, NO. 5, MAY 2008
`
`Resistive-Feedback CMOS Low-Noise
`Amplifiers for Multiband Applications
`
`Bevin G. Perumana, Student Member, IEEE, Jing-Hong C. Zhan, Member, IEEE, Stewart S. Taylor, Fellow, IEEE,
`Brent R. Carlton, Member, IEEE, and Joy Laskar, Fellow, IEEE
`
`__resistive-feedback CMOS
`compact
`Abstract—Extremely
`low-noise amplifiers (LNAs) are presented as a cost-effective
`alternative to multiple narrowband LNAsusing high-Q inductors
`for multiband wireless applications. Limited linearity and high
`power consumption of the inductorless resistive-feedback LNAs
`are analyzed and circuit techniques are proposed to solve these
`issues. A 12-mWresistive-feedback LNA, based on current-reuse
`transconductanceboosting is presented with a gain of 21 dB and
`a noise figure (NF) of 2.6 dB at 5 GHz. The LNA achieves an
`output third-orderintercept point (IP3) of 12.3 dBm at 5 GHz by
`reducing loop-gain rolloff and by improving linearity of individual
`stages. Theactive die area of the LNAis only 0.012 mm”.
`A 9.2-mW tunedresistive-feedback LNA utilizing a single com-
`pact low-Q on-chip inductor is presented, showing an improved
`tradeoff between performance, power consumption, and die area.
`At 5.5 GHz, the fully integrated LNA achieves a measured gain
`of 24 dB, an NF of 2 dB, and an output IP3 of 21.5 dBm. The
`LNA draws 7.7 mA from the 1.2-V supply and has a 3-dB band-
`width of 3.94 GHz (4.04-7.98 GHz). The LNA occupies a die area
`of 0.022 mm?. Both LNAsare implemented in a 90-nm CMOS
`process and do not require any costly RF enhancementoptions.
`
`Index Terms—CMOSlow-noise amplifier (LNA), feedback am-
`plifiers, multiband wireless receivers.
`
`I.
`
`INTRODUCTION
`
`OW-NOISEamplifiers (LNAs) occupy a significant per-
`
`Lcentage of the total die area in wireless front-ends today.
`
`This is because the performance of the LNAis dependenton the
`Q’s of the multiple on-chip inductors. Since the area require-
`ment of high-Q on-chip inductors is high, the die area occu-
`pied by the LNAisalso high. Often, costly process steps are
`required to enhance the Q of the on-chip inductors to further
`improve the performance of RF circuits. The design of these
`circuits usually requires a higher numberof simulation and veri-
`fication iterations. Cascode amplifiers with inductive source de-
`generation [1], the predominant LNA implementation used in
`
`Manuscript received September 1, 2007; revised January 18, 2008.
`B.G.Perumanawaswith the Communications Circuits Laboratory, Intel Cor-
`poration, Hillsboro, OR 97124 USA.Heis now with the Georgia Electronic De-
`sign Center, School of Electrical and Computer Engineering, Georgia Institute
`of Technology, Atlanta, GA 30332 USA (e-mail: beving @ece.gatech.edu).
`J.-H. C. Zhan was with the Communications Circuits Laboratory, Intel Corpo-
`ration, Hillsboro, OR 97124 USA.Heis now with the RF Division, MediaTek,
`HsinChu, 300 Taiwan, R.O.C.
`S. S. Taylor and B. R. Carlton are with the Communications Circuits Labo-
`ratory, Intel Corporation, Hillsboro, OR 97124 USA.
`J. Laskar is with the Georgia Electronic Design Center, Schoolof Electrical
`and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332
`USA.
`Color versions of one or moreof the figures in this paper are available online
`at http://ieeexplore.ieee.org.
`Digital Object Identifier 10.1109/TMTT.2008.920181
`
`Multi-Band Antenna
`
`Multi-Band /
`
`Wide-Band LNA
`
`Fig. 1. Multiband receiver implementation using a multiband/wideband LNA.
`
`Band 1
`
`Wide-Band Mixer
`
`Fig. 2. Multiband receiver implementation using multiple narrowband LNAs.
`
`CMOSwireless front-ends, require three high-Q inductors for
`achieving input impedance matching, high gain, and low noise
`figure (NF). In spite of the high die area requirements, cascode
`LNAshavebeen used extensively in narrowband wireless ap-
`plications because they provide high gain, low noise, and high
`linearity at relatively low power consumption. With the advent
`of multiple-input multiple-output (MIMO), multistandard, and
`multiband wireless systems; however, the use of the area inten-
`sive cascode LNAsis becoming increasingly expensive, leading
`to the pursuit of alternative LNA implementations.
`A multiband receiver can be implemented byusing a single
`multiband or wideband LNA,as shownin Fig. 1. Cascode LNAs
`based on inductive source degeneration are notsuitable for this
`implementation since it is extremely difficult to switch the three
`on-chip inductors to make the same cascode LNA workacross
`all the required frequency bands without compromising perfor-
`mance. Multiband receivers can also be implemented by using
`multiple narrowband LNAs,each designed for a different fre-
`quency band, as shownin Fig. 2. If cascode LNAs with induc-
`tive degeneration are used for this implementation, the die area
`and cost will both be prohibitively high.
`Inductorless resistive-feedback CMOS LNAs [2]-[4] have
`been shownto be a viable option for implementing multiband
`receivers, as shownin Fig. 1. These circuits require very small
`die area and can be implemented in a digital CMOSprocess
`without any additional RF enhancements. Hence,this approach
`can potentially significantly reduce the cost of the wireless
`front-end implementation. Resistive-feedback LNAs achieve
`
`0018-9480/$25.00 © 2008 IEEE
`
`INTEL 1008
`
`

`

`PERUMANAetal.: RESISTIVE-FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1219
`
`Fig. 3. Simplified schematic and small-signal model of a shunt-shunt feedback
`amplifier.
`1
`Vout
`
`
`
`m==(gm—5) (Fle)
`
`Ay = — =- (gm —- ——|(RL||Rr). 1
`
`the shunt-shunt feedback. Rg is the source resistance and
`Regi
`is used for biasing along with dc blocking capacitors
`Cp1,Cp2, and Cg3. The equivalent small-signal model of
`the transimpedance amplifier is shown in Fig. 3(b), where gm
`represents the transconductance of Mj. Cz. represents the
`capacitance to groundat the gate of M,. For frequencies well
`below 1/(27C,, Rg), the effect of Cz, can be neglected.
`
`A. Voltage Gain
`
`Using the small-signal model in Fig. 3(b), the voltage gain of
`the amplifier can be derived as
`
`Feedback analysis [10] can be done by opening the loop and
`determining the open-loop transresistance gain (a) and the feed-
`back factor (f), shown as follows:
`
`= —(Rs || Rr)gm(Rx || Rr)
`1
`f= Rp
`The voltage gain given by feedback analysis is
`
`Ay (Feedback Theory) = —9m(Rr || Rr).
`
`(2)
`(3)
`
`(4)
`
`The discrepancy between (1) and (4) is because the feedfor-
`ward path through Ap is ignored in the feedback analysis. This
`differenceis negligible if gm >> 1/Rr.
`
`B. Input Impedance Matching
`
`Shunt-shunt feedback reduces the input impedance of the
`amplifier by a factor of (1 + af). The input resistance (Rin)
`of the amplifier is given by
`
`Rin =
`
`(Rs||Rr) Rs
`l+af
`l+af
`
`(5)
`
`since Rr >> Rg (for reasons related to NF, which will ex-
`plained later). For input impedance matching, Ri, has to be
`equal to Rg/2. From (5), input matching is achieved with a
`loop gain (af) just below 1, which also ensures circuit sta-
`bility. Using (3), the open-loop transresistance gain has to be
`approximately equal to the value of the feedback resistance for
`achieving input impedance matching
`
`Input Impedance Match Condition: |a| & Rr.
`
`(6)
`
`C. NF
`
`geo
`
`
`Vbiast
`
`=
`
`(a)
`
`(b)
`
`high gain and reasonably low NF [4]. However, novel circuit
`techniques are required to reduce power consumption and
`improvelinearity.
`This paper presents an inductorless resistive-feedback LNA
`in which a current-reuse transconductance-boosting technique
`[5] is utilized to reduce the power consumption to 12 mW. The
`LNAhasa gain of 21 dB and an NFof 2.6 dB at 5 GHz. The
`active die area of this circuit is only 0.012 mm?. The combi-
`nation of small die area, broad bandwidth and moderate power
`consumption make this LNAarchitecture suitable for low-cost
`multistandard wireless front-ends, as shownin Fig. 1. By main-
`taining a moderate loop-gain across the frequency band andre-
`ducing the nonlinearities of individual stages, the LNA achieves
`an outputthird-order intercept point (IP3) of 12.3 dBm at 5 GHz.
`Techniquesto further improve IP3 by nonlinearity cancellation
`[6]-[9] are also presented.
`A resistive-feedback cascode LNA using a single com-
`pact on-chip load inductor is presented next. It has a max-
`imum gain of 24.4 dB, and a 3-dB bandwidth of 3.94 GHz
`(4.04—7.98 GHz). At 5.5 GHz, the NF is 2 dB, and the output
`IP3 is 21.5 dBm. Since the inductor Q is not required to be
`high, the area of this LNA is only 0.022 mm?. This makesit
`suitable for multiband receiver implementations, as shown in
`Fig. 2. This LNA can also be easily modified to operate across
`multiple frequency bands(as in Fig. 1) since the single low-Q
`tuned load can be switchedto resonate at different frequencies.
`The gain,
`input
`impedance, NF, and linearity of resis-
`tive-feedback LNAs are discussed in Section II. Section HI
`describes circuit techniques to improve linearity and lower
`power consumption. The design of the inductorless LNA
`with current-reuse transconductance boosting and the tuned
`resistive-feedback LNA (using a compact low-Q inductor) are
`described in Section III. The implementation details of these
`circuits are discussed in Section IV. The measurementresults of
`
`both the LNAsare given in Section V along with performance
`comparison to other reported circuits. Finally, conclusions are
`presented in Section VI.
`
`II. RESISTIVE-FEEDBACK LNA THEORY
`
`The contribution of each noise sourceto the total output noise
`is evaluated. The NFis then calculated by evaluating the ratio of
`the total output noise to the output noise due to fg as follows:
` Vom
`TR39m
`
`NF x1
`
`1
`———
`RsRzg?2,
`
`Consider a simplified resistive-feedback amplifier, as shown
`in Fig. 3(a). M1 represents the input transconductancedevice,
`-1
`ARs
`which could bea single transistor or a cascode pair. Rz repre-
`aes yp 7
`Rp
`Rr + Rs
`7)
`sents the load resistance including the output resistance of the
`1+ ——"|
`input transconductancestage. Rp is the resistor implementing
`(1 + gmRs)Rr
`
`2
`
`

`

`1220
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES,VOL. 56, NO. 5, MAY 2008
`
`where 7g, is the noise excess factor of M/[11]. Equation (7)
`showsthat having a large feedback resistance can lower the NF.
`From (6), a higher PRrequires a higher open-loop gain for input
`matching, usually leading to higher power consumption.
`
`D. Linearity
`
`Consider a nonlinear amplifier modeled by the powerseries
`[12]
`
`Vout = 41 Vin + A2V:n + a3Vins
`
`(8)
`
`
`
`Negative feedback improves its input IP3 by the following
`factor:
`
`Fig. 4. Schematic of the current-reuse transconductance-boosting resis-
`tive-feedback LNA.
`
`
`IP3len
`IP3loL
`
`2
`
`_
`
`=G+aly
`~(1+a,f)?/
`
`a3
`
`layup =e
`
`(9)
`
`where 2fa3 < a3(1+a1f), IP3|cr, and IP3|oxrepresentthe
`close-loop and open-loop IP3, respectively. Equation (9) shows
`that linearity is not significantly improved by feedback at high
`frequencies if the open-loop gain of the amplifierrolls off [2].
`
`II. LOw-POWER HIGH-LINEARITY
`RESISTIVE-FEEDBACK LNAs
`
`Asdiscussed in Section II, a high open-loop gain is required
`to simultaneously achieve low NF and good input matching.
`The open-loop bandwidth also has to be high to achieve high
`linearity at high frequencies. These requirements usually lead
`to high power consumptionsin resistive-feedback LNAs [2],
`[4]. We nowpresentcircuit techniques to improvelinearity and
`lower power consumptionin resistive-feedback LNAs.
`
`A. Current-Reuse Resistive-Feedback LNA
`
`The schematic of the restive feedback LNA with current-
`
`reuse transconductance boosting is shown in Fig. 4. Cascode
`transistors M1 and M3 form the input transconductancestage.
`A significant portion of the bias current in MMis diverted away
`from the load resistor Rz by transistor M2. This reduces the dc
`voltage drop across R,. Moreover, the transconductance gener-
`ated by M2 addsto that of Mj, increasingthe effective g,, of the
`input stage. The current mirror formed by M7 and Mg controls
`the amount of current shunted away from R;. The amplified
`signal is fed back to the input transconductancestage through
`feedback resistor Ry and the source follower formed by Mg,
`Ms, and R;. The diode connected Ms is used in the source fol-
`lower to generate gate bias voltages for M,, M2, and M3. The
`dc and ac feedback loops are thus combined, makingit possible
`to removethe dc blocking capacitors required in earlier reports
`[4]. This reducesthe total area requirement, and avoids loading
`of the source follower by the parasitic capacitance of the dc
`blocking capacitor to the substrate. The latter improves the LNA
`linearity. An additional source follower, formed by Mg and Ro,
`is incorporated to improvereverse isolation and output driving
`capability. As discussed in Section II, the linearity at high fre-
`quencies can be improved by increasing open-loop bandwidth.
`This is achieved by device sizing and reducing layout para-
`sitics as muchas possible. The overall linearity of the LNA is
`
`improved by making each block of the LNA morelinear. Re-
`movingthe de block capacitors reducesthe loading of the source
`follower, making it more linear, as explained earlier. Resistors
`Ry and Rp replace active current mirrors, which are nonlinear
`and have greater capacitance.
`In all resistive-feedback LNAs with g,,-enhanced cascode
`structure, the width/length (W/L)ratio of the cascodetransistor
`is kept low to achieve a higher bandwidth. The cascode device
`also has a lowerbias current than the inputtransistor soas to re-
`duce the voltage drop acrossthe load resistor, as explained ear-
`lier. The lower W/L ratio and bias current makes the transcon-
`
`ductance of the common-gate cascode transistor significantly
`lower than the common-sourceinputtransistor. The gain of the
`common-source stage is the ratio of these transconductances.
`The high gain in the common-source input stage preceding the
`cascode stage makes the g,, nonlinearity in the cascode stage
`limit the overall circuit linearity. This is because the IIP3 of
`the combined stages (IIP3cg_cq) is related to the IIP3 of the
`common-sourcestage (IIP3cs), its gain (Gos), and the IIP3 of
`the common-gate stage (IIP3cq) by the following equation:
`
` 1 _ 1 1 ( Ges )
`
`(IP3cs_ce)?
`
`
`
`(IIP3cs)?
`
`
`
`
`
`IIP3cq
`
`(10)
`
`Hence, significant improvementin linearity can be obtained
`if the nonlinearity of the cascode stage is reduced by nonlin-
`earity cancellation. This can be achieved by using derivative
`superposition [6], [13], as shown in Fig. 5(a). Here, the gn3
`(6°Ip/5Vas) of the common-gate stage (M3) is cancelled
`by the gm3 of the subthreshold transistor Mg. The measured
`input IP3 of the g,,-enhanced cascode LNAis plotted against
`the gate voltage of M3 (Vc) in Fig. 5(b). Though significant
`improvements in IP3 have been demonstrated with derivative
`superposition at the cost of increased NF (0.6 dB) [9], such
`cancellation techniques may havepotential issues in volume
`applications due to process and temperature variations.
`
`B. Tuned Resistive-Feedback LNA with a Compact
`Low-Q Load Inductor
`
`Linearity issues due to the high gain in the common-source
`stage preceding the common-gate cascode stage can be avoided
`by replacing the load resistance with a low-@ resonant load,
`
`

`

`PERUMANAetal.: RESISTIVE-FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1221
`
`
`
`
`
`(a)
`
`IP3(dBm)
`
`0.2 04 06 08 1
`
`1.2
`
`Input
`
`VM
`(b)
`
`Fig. 5. Nonlinearity cancellation in a g,,,-enhanced cascode LNA with deriva-
`tive superposition.
`
`Low-Q Inductor
`
`
`
`
`Cop
`|e output
`
`
`
`
`
`Fig. 6. Schematic of the tuned resistive-feedback LNA utilizing a compact
`low-Q load inductor.
`
`using a compacton-chip inductor. The bias current of the cas-
`code device can be madeequal to that of the input device be-
`causethe dc voltage drop across the resonantloadis negligible.
`Sinceall the capacitanceat the output node can be resonated out
`with the inductive load,it is not necessary to make the W/Lratio
`of the cascode device small.
`The schematicof a tuned resistive-feedback LNA is shown in
`
`Fig. 6. Transistor M, is used as the common-source transcon-
`ductance stage and Mz is used as the cascode common-gate
`stage. A compact low-Q on-chipspiral inductor L, andthetotal
`capacitance at the output node form the resonantload. The par-
`asitic capacitance of the dc block capacitors (Cc¢2 and Ce3) to
`substrate and the drain capacitance of MMcan, therefore, be res-
`onated out along with the load capacitance at the output node.
`Resistors Rrpi, Rrpe2, and Rrp3 form the shunt-shunt feed-
`back path. Capacitors C'g; and C’g2 andresistor Rg, are used
`for biasing the cascodetransistors.
`Since this LNA utilizes only a single low-Q load inductor,
`it can be made extremely compact. Hence, low-cost multiband
`receivers can be implemented by using multiple tunedresistive-
`feedback LNAseach designed for a different frequency band,
`as shownin Fig. 2.
`This circuit can be easily modified to operate across different
`frequency bands for the multiband receiver implementation
`
`
`
`
`
`Fig. 7. Schematic of the modified super source follower output buffer.
`
`shown in Fig. 1. The band-switching scheme enabling this
`implementation is shown in Fig. 6. The resonant frequency
`f, can be shifted by using the capacitors C, and C> and the
`switches Sc, and Sc2. At resonance, the load impedance is
`purely resistive and given by
`
`Rrgr = 2af,Lys (en + a)
`
`Qfr
`
`(11)
`
`Here, Ly, and Qf, are the inductance and Q of the load inductor
`at the resonant frequency f,. All the equations from Section II
`are still valid if Az is replaced by Rz,f,, and if g represents
`the effective transconductance of the cascodestage.
`If the switches So and Sz are used to shift f,, the value of
`Rr,fr, given by (11), will not be the samein different frequency
`bands. Thus,
`the open-loop transimpedance gain (a) given
`by (2), will also vary from one frequency band to another.
`To satisfy the input matching condition in (6) across all the
`frequency bands, the feedback resistance Rpg will also have to
`be switched, as shownin Fig. 6, using switches Sp; and Sro.
`
`IV.
`
`IMPLEMENTATION OF THE RESISTIVE-FEEDBACK LNAs
`
`Both of the resistive-feedback LNAs are implemented in a
`90-nm seven-metal CMOSprocess. The only RF enhancement
`option used is the high-resistivity substrate under RF signal
`paths. All the capacitors were implementedasinter-digitated
`metal finger capacitors. Since the output impedance of the
`LNAsare not 50 2, a modified super source follower [4] was
`usedto facilitate measurements. The schematic of this circuit is
`shownin Fig. 7.
`The current-reuse transconductance-boosting resistive-feed-
`back LNA draws6.7 mAfrom the 1.8-V supply, thus consuming
`12 mW of power. The chip micrograph of this LNA is shown in
`Fig. 8. The chip is pad limited and the actual LNA dimensions
`are 40 xm X 310 yum (Area: 0.012 mm?). This implementation
`is a very low-costalternative to the conventional inductor-based
`circuits for multiband multistandard radios.
`
`The tuned resistive-feedback LNA has a power consump-
`tion of 9.2 mW,drawing 7.7 mA from the 1.2-V supply. Band
`switching is not implemented and the LNA is designed to op-
`erate in a single frequency band around 5.5 GHz. The chip mi-
`crographofthis circuit is shown in Fig. 9. The LNA dimensions
`are 155 ym x 145 yum (Area: 0.022 mm’).
`
`

`

`1222
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES,VOL. 56, NO. 5, MAY 2008
`
`35
`
`.
`
`— —LNA Measured Gain (dB)
`--#--Buffer Measured Loss (dB)
`— 30)
`—e—/NA+Buf Measured Gain (dB)
`S
`
`20
`
`o =
`
`oc
`
`g 254}HHaseLNA+Buffer Simulated Gain (dB) }
`
`
`
`
`
`
`15
`
`‘we
`oS
`@®
`ys
`& 10)
`Ss
`5 eeed+eeeeeeesyoocnntpaestonanaysteat
`
`06 08 1
`
`3
`
`5
`
`7
`
`#9
`
`Frequency (GHz)
`
`Fig. 10. Measured and simulated gain of the current-reuse transconductance-
`boosting resistive-feedback LNA andoutput buffer.
`
`
`
` |
`
`
` | ~—2-"
`-15 ee ae ee
`
`Pre
`
`-20 |
`
`06 08 1
`
`3
`
`5
`
`7
`
`9
`
`Frequency (GHz)
`
`Fig. 11. Measured and simulated input matching of the resistive-feedback
`LNA.
`
`Fig. 8. Chip micrographof the current-reuse transconductance-boostingresis-
`tive-feedback LNA.
`
`Fig. 9. Chip micrograph ofthe tuned resistive-feedback LNA.
`
`V. MEASUREMENT RESULTS
`
`The measurements for both of the resistive-feedback LNAs
`
`were performed with on-wafer probing. Standalone output
`buffers were measured to deembedtheir effect on the measure-
`mentresults of the LNAs.
`
`
`
`|= Measured S11 (dB)
`
`||——*=Simulated $11 (dB)
`
`A. Measurement Results of the Current-Reuse
`Resistive-Feedback LNA
`
`5.
`
`
`:
`
`——— Vieasured LNANoise Figure (dB)
`45 |
`——— Measured LNA+Buffer Noise Figure {aBy |
`The standalone output buffer used with the current-reuse
`
`‘ ===== Simulated LNA+Buffer Noise Figure (dB)|*
`transconductance boosting LNA hasan insertion loss of 7 dB.
`oO
`Its input IP3 is 15.6 dBm at 5.8 GHz, 18 dBm at 5 GHz,and
`Ss
`higher at lower frequencies. The buffer NF is 10 dB, including
`2S
`a
`the noise added by a 50-() resistor added at the input for
`iz
`impedance matching.
`3o
`The measured and simulated gain of the LNA and output
`=
`buffer is shownin Fig. 10. Also plotted in Fig. 10 are the buffer
`loss and the deembedded LNAgain. Thegain falls from 22 dB
`at low frequencies to 21 dB at 5 GHz. The 3-dB bandwidth is
`7.5 GHz.
`The measured and simulated input matching of the LNA are
`plotted in Fig. 11. It is —10 dB at 5 GHz andbetter at lower
`frequencies. The measured NF is plotted against frequency
`in Fig. 12. The NF is 2.6 dB at 5 GHz and varies between
`2.3-2.9 dB from 500 MHz to 7 GHz. The 1.5-dB increase in
`gain in the measuredresults is due to slightly higher values
`for Rz and Rp. This increase in gain leads to improved input
`matching and noise performance compared to the simulated
`results.
`
`
`
`0.6 08 1
`
`3
`
`5
`
`7
`
`9
`
`Frequency (GHz)
`
`Fig. 12. Measured and simulated NF of the LNA andoutput buffer.
`
`Theinput IP3 of the LNAis plotted in Fig. 13 after deembed-
`ding the effects of the output buffer. It varies from —2.3 dBm at
`500 MHzto —8.8 dBm at 5.8 GHz. The degradationof linearity
`
`

`

`PERUMANAetal.: RESISTIVE-FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1223
`
`— — Measured S11 (dB)
`te Simulated $11 (dB)
`° wer
`»
`f t
`>
`\ if
`L1}
`:
`;
`
`|
`
`|
`
`+i
`
`w
`
`f
`
`0}
`POO Oe ew)
`&
`-10 |
`Ss
`= 715 |
`an
`
`-20
`
`-25 |
`
`
`
`— —LNA IIP3
`
`
`
`-2
`
`-4 Bases
` lIP3(dBm)
`==
`~N
`
`-—
`
`
`
`
`-30
`290@AA$dTTT___—__
`1
`2
`3
`4
`5
`6
`7
`8
`Q
`06
`08 1
`3
`5
`7
`#9
`Frequency (GHz)
`
`Frequency (GHz)
`
`Fig. 13. Measured input IP3 of the current-reuse transconductance-boosting
`LNA.
`
`Fig. 15. Measured and simulated input matching of the tuned LNA.
`
`—-—LNA Measured Gain (dB)
`--#-=Buffer Measured Loss (dB)
`—e— LNA+Buffer Measured Gain (dB)
`5. LNA+Buffer Simulated Gain (dB)
`—_—
`~~
`20“4—-3-4B BW-—> ~
`
`
`
`——— Measured LNANoise Figure (dB)
`—~—— Measured LNA+Buffer Noise Figure (dB)
`aaa Simulated LNA+Buffer Noise Figure (dB)
`
`|
`
`(dB)
`
`NoiseFigure
`
`Frequency (GHz)
`
`Fig. 16. Measured and simulated NF ofthe tuned resistive-feedback LNA and
`output buffer.
`
` 20
`
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`
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`LT -20
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`Input IP3 = -7.7 dBm :
`
`-80
`-40
`
`-35
`
`-30
`
`-25
`
`-20
`
`-15
`
`MAL
`-10
`-5
`
`O
`
`Input Power (dBm)
`
`Fig. 17.
`
`Input IP3 ofthe tuned resistive-feedback LNA.
`
`buffer is —7.7 dBm at 5.5 GHz. The IIP3 of the LNAis found to
`
`be —2.6 dBm after deembedding the output buffer nonlinearity
`using the IIP3 of the standalone buffer (18 dBm) and the gain
`of the LNA (24.1 dB). Therefore, the output IP3 of the LNA
`is 21.5 dBm. The measured input 1-dB compression point of
`the LNA and buffer is —18 dBm at 5.5 GHz. The input 1-dB
`compression point of the LNA withoutthe outputbuffer is found
`to be —7.2 dBm after deembedding.
`
`
`
`VoltageGainorLoss(dB)
`
`30 |
`
`35 |
`
`|
`
`
`
`
`Frequency (GHz)
`
`Fig. 14. Measured and simulated gain of the tuned resistive-feedback LNA and
`output buffer.
`
`with frequencyis dueto the loop gain rolloff with frequency, as
`explained earlier.
`
`B. Measurement Results of the Tuned Resistive-Feedback LNA
`
`The standalone output buffer used with the tunedresistive-
`feedback LNAis similar to the one used with the current-reuse
`
`LNAandhasa loss of 8 dB, and an NFof 9.8 dB (including the
`noise added by the 50-2 resistor at the input). The output buffer
`has an input 1-dB compression point of 6.5 dBm and an input
`IP3 of 18 dBm at 5.5 GHz.
`The measured and simulated gain of the LNA and output
`buffer is plotted in Fig. 14. The buffer loss and the deembedded
`gain of the LNA without the buffer are also plotted in Fig. 14.
`The LNA has a maximum gain of 24.4 dB and a 3-dB band-
`width of 3.94 GHz from 4.04 to 7.98 GHz. The measured input
`matchingis plotted in Fig. 15. The input matchingis better than
`—10 dB from 5 to 6.85 GHz.
`
`Fig. 16 shows the measured and simulated NF of the tuned
`resistive-feedback LNA andthe output buffer. The deembedded
`NF of the LNA without the output buffer is also plotted. The
`tuned resistive-feedback LNAhas an NFof approximately 2 dB
`between 4-6 GHz.
`
`The IP3 of the LNA andoutput buffer is plotted in Fig. 17.
`The input IP3 of the tuned resistive-feedback LNA and output
`
`

`

`1224
`
`IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES,VOL. 56, NO. 5, MAY 2008
`
`TABLEI
`WIDEBAND LNA PERFORMANCE COMPARISON
`
`This Work
`Current-Reuse Tuned
`LNA LNA
`
`
`90-nm
`90-nm
`CMOS
`Process CMOS
`
`
`
`Freq.
`4-8
`(GHz)
`0.5-7
`
`
`Power
`(mW)
`
`consumption makes this LNA architecture a compelling choice
`for low-cost multistandard wireless front-ends.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank the following colleagues
`at the Communication Circuit Laboratory, Intel Corporation,
`Hillsboro, OR: D. Steele for layout assistance; R. Bishop for
`measurement setup, J. S. Duster
`for useful discussions; and
`K. Soumyanath for support and encouragement.
`
`REFERENCES
`
`VI. CONCLUSION
`
`
`
`Bevin G. Perumana (S’04) was born in Kerala,
`India, in 1980. He received the B.Tech. degree in
`electrical engineering from the Indian Institute of
`Technology, Kharagpur,India, in 2002, the M.S. de-
`gree in electrical engineering from Georgia Institute
`of Technology, Atlanta,
`in 2005, and is currently
`working toward the Ph.D. degree in electrical and
`computer engineering at the Georgia Institute of
`Technology. His doctoral dissertation concerns
`low-power CMOSfront-ends for wireless personal
`area networks.
`
`
`
`
`
`
`Area
`(mm’)
`
`Voltage
`Gain
`(dB)
`Noise
`Figure
`(dB)
`OIP3
`(dBm)
`
`8.8 (5.8
`GHz)
`
`76
`GHz)
`
`[1] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOSlow noise
`amplifier,’ JEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745-759,
`May 1997.
`[2] B.G. Perumana,J.-H. C. Zhan, S. Taylor, and J. Laskar, “A 0.5-6 GHz
`improvedlinearity, resistive feedback 90-nm CMOS LNA,”in Proc.
`IEEE Asian Solid-State Circuits Conf., 2006, pp. 263-266.
`[3] H. M. Adiseno and H. Olsson, “A 1.8-V wideband CMOS LNAfor
`multiband multistandard front-end receiver,’ Proc. ESSCIRC, pp.
`141-144, 2003.
`[4] J.-H. C. Zhan andS. Taylor, “A 5 GHz resistive-feedback CMOS LNA
`for low-cost multi-standard application,’ in IEEE ISSCC Tech. Dig.,
`2006, pp. 200-201.
`[5] B. G. Perumana, J.-H. C. Zhan, S. Taylor, and J. Laskar, “A 12 mW,
`7.5 GHz bandwidth, inductorless CMOS LNAfor low-power, low-cost,
`multi-standardreceivers,” in Proc. IEEE RFIC Symp., 2007, pp. 57-60.
`[6] D. R. Webster, D. G. Haigh, J. B. Scott, and A. E. Parker, “Deriva-
`The performance of the two resistive-feedback LNAs are
`tive superposition—Alinearization technique for ultra broadband sys-
`tems,” in IEE Wideband Circuits, Modeling, Technol. Collog., May
`tabulated and compared with others reported in Table I. The
`1996, pp. 3/1-3-3/1-14.
`
`current-reuse transconductance-boosting—resistive-feedback
`[7] V. Aparin and L. E. Larson, “Modified derivative superposition method
`LNAprovides comparable performance at lower power con-
`for linearizing FET low-noise amplifiers,” JEEE Trans. Microw. Theory
`Tech, vol. 53, no. 2, pp. 571-581, Feb. 2005.
`sumption while occupying very small die area. The tuned
`[8] N. Kim,V. Aparin, K. Barnett, and C. Persico, “A cellular-band CDMA
`resistive-feedback LNA, though requiring slightly larger die
`0.25-j4m CMOSLNAlinearized using active post-distortion,” JEEE J.
`area than the inductorless LNA, provides very high linearity,
`Solid-State Circuits, vol. 41, no. 7, pp. 1530-1534, Jul. 2006.
`[9] B. G. Perumana, J.-H. C. Zhan, S. Taylor, and J. Laskar, “A 5 GHz, 21
`low noise, and high gain while dissipating low power. This
`dBm output-IP3resistive feedback LNA in 90-nm CMOS,”presented
`LNApresents a much improvedtradeoff between performance,
`at the ESSCIRC,2007.
`power consumption, and cost, especially for multiband multi-
`[10] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
`Design ofAnalog Integrated Circuits, 4thed. New York: Wiley, 2001.
`standard wireless receivers.
`[11] Y. Cui, G. Niu, Y. Li, S. S. Taylor, Q. Liang, and J. D. Cressler, “On
`the excess noise factors and noise parameter equations for RF CMOS,”
`in Silicon Monolithic Integr. Circuits RF Syst. Top. Meeting, Jan. 2007,
`pp. 40-43.
`[12] W. Sansen, “Distortion in elementary transistor circuits,’ JEEE Trans.
`Extremely compact LNAcircuits based onresistive feedback
`Circuits Syst. II, Analog, Digit. Signal Process., vol. 46, no. 3, pp.
`are presented as a cost-effective alternative to multiple tuned
`315-325, Mar. 1999.
`[13] T. W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end
`LNAsrequiring many high-@ inductors for multiband wireless
`adopting MOSFETtransconductancelinearization by multiple gated
`applications. The relationships between the feedbackresistance,
`transistors,” JEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 223-229,
`Jan. 2004.
`NF, input matching, and open-loop gain are presented. The ef-
`[14] J. Borremans, P. Wambacq, and D. Linten, “An ESD-protected
`fect of the open-loop bandwidth on the close-loop linearity is
`DC-to-6 GHz 9.7 mW LNAin 90 nm digital CMOS,” in IEEE ISSCC
`also explained. A current-reuse transconductance boosting tech-
`Tech. Dig., 2007, pp. 422-423.
`nique is used to reduce the power consumptioninaresistive-
`[15] M. T. Reiha, J. R. Long, and J. J. Pekarik, “A 1.2 V reactive-feedback
`3.1-10.6 GHz ultrawideband low-noise amplifier in 0.13 sm CMOS,”
`feedback LNAto 12 mW.The inductorless LNA achievesa gain
`in Proc. IEEE RFIC Symp., 2006, pp. 41-44.
`of 21 dB and an NF of 2.6 dB at 5 GHz. Therolloff of loop
`[16] R. Salerno, M. Tiebout, H. Paule, M. Streibl, C. Sandner, and K. Kropf,
`gain and the nonlinearities in the feedback loop are reduced to
`“ESD-protected CMOS 3-5 GHz wideband LNA+PGAdesign for
`UWB,”in Proc. ESSCIRC, 2005, pp. 219-222.
`improve the output IP3 to 12.3 dBm at 5 GHz. Theactive die
`area of this LNA is only 0.012 mm?. A tuned resistive-feed-
`back LNA, using a compact resonant load, is also presented.
`It achieves a maximum gain of 24.4 dB and a 3-dB bandwidth
`of 3.94 GHz using a single low-Q on-chip inductor and con-
`suming 9.2 mW of power. The LNA has an active die area of
`0.022 mm?. The NFofthe tunedresistive-feedback LNAis ap-
`proximately 2 dB between 4—6 GHz. At 5.5 GHz, the LNA has
`an output IP3 of 21.5 dBm. The combination of high linearity,
`low NF, high broadband gain, small die area, and low power
`
`

`

`PERUMANAetal.: RESISTIVE-FEEDBACK CMOS LNAs FOR MULTIBAND APPLICATIONS
`
`1225
`
`From 2002 to 2003, he was a Research Consultant with the Advanced Very
`Large Scale Integration (VLSI) Design Laboratory, Indian Institute of Tech-
`nology, Kharagpur, India. From 2003 to 2005, he was a Graduate Research
`Assistant with the Microwave Application Group, Georgia Electronic Design
`Center, Georgia Institute of Technology. From 2005 to 2006, he was an Intern
`with the Communication Circuits Laboratory, Intel Corporation, Hillsboro, OR.
`
`
`
`Jing-Hong C. Zhan (S’97—M’04)received the B.S.
`and M.S. degrees in electrical engineering from
`Tsing-Hua University, HsinChu, Taiwan, R.O.C., in
`1996 and 1997, respectively, and the Ph.D. degree
`in electrical engineering and computer science in
`Cornell University, Ithaca, NY, in 2004. His MLS.
`thesis concerned side-polished fiber fabrication and
`theoretical analysis. His doctoral research focused on
`voltage-controlled oscillator (VCO) and high-speed
`clock and data recovery circuitry using BiCMOS
`and CMOS.
`Upon completion of compulsory services with the Taiwanese Army, where
`he served as a Secondary Lieutenant from 1997 to 1999, he joined MediaTek,
`HsinChu, Taiwan, R.O.C., where he was a Logic Design Engineeruntil 2001.
`He developed the data path and spindle motorcontrolcircuitry for MediaTek’s
`optical storage products. In 2004, hejoined the Communications Circuit Labora-
`tory, Intel Corporation, Hillsboro, OR, where he was a Senior Design Engineer.
`His research focused on fabricating low-cost radios on CMOStechnologies for
`microprocessors production. In 2006, he joined the RF Division, MediaTek, as
`a Technical Manager, where heleda silicon tuner front-end design team. He
`codeveloped an all-digital phase-locked loop (PLL) for wireless applications.
`H