Exhibit F-11: Chunky SLD
`
`An article entitled, “Automated Target Recognition on SPLASH 2,” by Rencher et al., (“Chunky SLD”), was published in the IEEE
`Symposium on Field-Programmable Custom Computer Machines, pp. 192-200 in 1997, and is therefore prior art to U.S. Patent No.
`7,620,800 (“’800 Patent”) at least under 35 U.S.C. §§ 102(a) and (b).
`
`As described in detail below, Chunky SLD anticipates the asserted claim(s) of the ’800 Patent. To the extent it is found that Chunky
`SLD does not expressly disclose certain limitations in the asserted claim, such limitations are inherent. Furthermore, to the extent it is
`found that Chunky SLD does not anticipate the asserted claim, Chunky SLD renders the asserted claim obvious, either alone or in
`combination with other prior art identified in the cover pleading or herein.
`
`This chart is subject to all reservations, objections, and disclaimers in Microsoft’s Invalidity Contentions and any amendment,
`supplement, or modification thereof, which are incorporated herein by reference in their entirety.
`
`
`Exemplary Disclosure of Chunky SLD
`
`Asserted Claim of ’800
`Patent
`[1A] A method for data
`processing in a reconfigurable
`computing system, the
`reconfigurable computing
`system comprising at least one
`reconfigurable processor, the
`reconfigurable processor
`comprising a plurality of
`functional units, said method
`comprising:
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at Abstract: “Automated target recognition is an application area that requires special-
`purpose hardware to achieve reasonable performance. FPGA-based platforms can provide a high
`level of performance for ATR systems if the implementation can be adapted to the limited FPGA
`and routing resources of these architectures. This paper discusses a mapping experiment where a
`linear-systolic implementation of an ATR algorithm is mapped to the SPLASH2 platform. Simple
`column-oriented processors were used throughout the design to achieve high performance with
`limited nearest-neighbor communication. The distributed SPLASH2 memories are also exploited to
`achieve a high degree of parallelism. The resulting design is scalable and can be spread across
`multiple SPLASH2 boards with a linear increase in performance.”
`
`Chunky SLD at 196: “The actual SPLASH2 platform consists of a board with 16 Xilinx 4010 chips
`(plus one for control) arranged in a linear systolic array. Each chip has a limited 36-bit connection to
`its two nearest neighbors. Each Xilinx 4010 is connected to a 512 kbyte memory (16-bit word size).
`The memory can handle back-to-back reads, or back-to-back writes, but requires one ‘dead’ (or turn
`around) cycle when changing from write to read. There is also a crossbar connected to all of the
`
`SRC Labs, LLC, et al. v. Microsoft Corp.,
`Case No. 18-cv-321 (JLR) (W.D. Wash.)
`
`1
`
`July 9, 2018
`
`

`

`Exhibit F-11: Chunky SLD
`
`chips that allows some level of random connection between chips. Up to 16 boards can be daisy-
`chained together to provide a large linear-systolic array of 256 elements.”
`
`Chunky SLD at Figure 6:
`
`
`
`Chunky SLD at Figure 7:
`
`
`
`
`2
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`Chunky SLD at Figure 8:
`
`
`
`
`3
`
`

`

`Exhibit F-11: Chunky SLD
`
`[1B] transforming an algorithm
`into a data driven calculation
`that is implemented by said
`reconfigurable computing
`system at the at least one
`reconfigurable processor;
`
`
`
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at Abstract: “Automated target recognition is an application area that requires special-
`purpose hardware to achieve reasonable performance. FPGA-based platforms can provide a high
`level of performance for ATR systems if the implementation can be adapted to the limited FPGA
`and routing resources of these architectures. This paper discusses a mapping experiment where a
`linear-systolic implementation of an ATR algorithm is mapped to the SPLASH2 platform. Simple
`column-oriented processors were used throughout the design to achieve high performance with
`limited nearest-neighbor communication. The distributed SPLASH2 memories are also exploited to
`achieve a high degree of parallelism. The resulting design is scalable and can be spread across
`multiple SPLASH2 boards with a linear increase in performance.”
`
`4
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`Chunky SLD at 195: “Chunky SLD was implemented on the SPLASH2 board. SPLASH2 has
`shown itself to be a useful platform and has had numerous applications mapped to it [4, 5, 6, 7, 8, 9,
`10, 111. The implementation was done in VHDL and simulated/synthesized using Synopsis. All
`place and route was done automatically using Xilinx place and route tools.”
`
`Chunky SLD at 196: “The actual SPLASH2 platform consists of a board with 16 Xilinx 4010 chips
`(plus one for control) arranged in a linear systolic array. Each chip has a limited 36-bit connection to
`its two nearest neighbors. Each Xilinx 4010 is connected to a 512 kbyte memory (16-bit word size).
`The memory can handle back-to-back reads, or back-to-back writes, but requires one ‘dead’ (or turn
`around) cycle when changing from write to read. There is also a crossbar connected to all of the
`chips that allows some level of random connection between chips. Up to 16 boards can be daisy-
`chained together to provide a large linear-systolic array of 256 elements.”
`
`Chunky SLD at Figure 6:
`
`
`
`
`5
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`Chunky SLD at Figure 7:
`
`
`
`Chunky SLD at Figure 8:
`
`
`
`
`6
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`Chunky SLD at 193-94: “The first step of the Chunky SLD algorithm is to correlate the chip and the
`Bright template. This correlation value is used to compute a value that will be used to threshold the
`incoming chip data, converting the 8-bit chip image into a binary image. The equations describing
`this process are shown below.
`
`
`
`
`
`
`
`The values obtained by correlating the Bright and Surround templates with the binarized chip (Bsum
`and Ssum) are checked against minimum values to generate a “hit value” for each offset in the chip.
`The threshold value is also checked to see if it falls in an acceptable range when generating the hit
`values.”
`
`Chunky SLD at Figure 5:
`
`
`7
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`
`
`Chunky SLD at 196-97: “4.3 ATR Implementation on Splash 2
`Similar to the example, the SPLASH2 implementation processes one pixel at a time and loads them
`in column order so that the partial sums can be generated and passed from column to column. All
`template data are stored in the memories adjacent to the FPGAs on the SPLASH2 boards. Each
`memory can hold several thousand templates thus making it possible to store all of the templates for
`a single class (5760) on a single SPLASH2 board. There is sufficient room in the FPGA design to
`store a single template. The templates are switched by reading the new template data out of the
`
`8
`
`

`

`Exhibit F-11: Chunky SLD
`
`231424 compute cycles=0.14%.
`318 flush cycles
`
`memory and storing it within the FPGA. However, because this implementation is deeply pipelined,
`it is necessary to flush all current data from the system when switching to a new template. The
`overhead from the flushing operation is
`
`During each clock cycle, a new pixel arrives at the FPGA. If the template bit corresponding to this
`pixel is on then the incoming pixel is added to the current partial sum. Each 16 clock cycles, this
`partial sum is then passed on to the next column and a new partial sum is received from the previous
`column. The last column computes a complete Shapesum every 16 cycles (one column). The final
`correlation of the Bright and Surround templates with the thresholded chip data works similarly
`except there are two correlations (one for each template).
`
`Intermediate hit values are stored in a table, referred to as the hit-table, in one of the local memories.
`Each location in the table corresponds to an x-y offset of a chip, the origin of a single correlation.
`For each offset, if a chunk “hits”, then the corresponding location in this table is incremented. Thus
`the table contains the accumulated hit values for all chunks and all offsets that have been computed
`to that point. Hits are computed according to Equation 1. First, each Bsum and Ssum value is
`compared to its corresponding minimum value. Second, the threshold value corresponding to each
`Bsum and Ssum is checked to see if it is between a certain minimum and maximum value. For reasons
`of efficiency, the threshold value is actually examined earlier in the process and a zero for the
`threshold is stored in lookup-table memory if it is out of bounds. This works correctly because if the
`threshold is zero, it will cause the Bsum to be zero, which will in turn cause the Bsum comparison to
`fail. Otherwise, if all three of these tests come back true then a hit has been found for the
`corresponding offset (see Equation 1) and the corresponding location in the hit-table is incremented.
`After the 40 templates are tested against the same chip the two offsets with the highest accumulated
`hit values are written into memory where the host computer can read them. This is accomplished by
`examining the hit values during this process and retaining the top two values in special memory
`locations. These final two hit values (which represent the top two orientations for a specific class)
`are used in the FI step.
`
`For the SPLASH2 board, as with most FPGA systems, partitioning is a major issue. The design
`needed to be modular so that different design modules could be reassigned to different FPGAs as
`necessary. This is where the column modules were so valuable (see Figure 8).”
`
`
`9
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`Chunky SLD at 197: “4.4.1 Distributed Control
`The control in this system is distributed throughout the array. Each column module has it's own state
`machine based control. Module synchronization is achieved by distributing a control token through
`the pipeline along with the data. When a module receives this signal, it resets its internal state
`machines and retrieves template data from its local memory. A memory controller resides in each
`processing element (FPGA) to retrieve template data and give memory access to all other modules.”
`
`Chunky SLD at 197: “4.4.2 Modular Design (Design for Partitioning)
`Each column in both the Shapesum and final correlation use totally self-contained modules that can
`be easily migrated from processing element to processing element. This was done to simplify the
`partitioning onto SPLASH2 [13]. Memory data had to be carefully partitioned as well so that the
`data could follow the module to which it applied. The regularity of the design was an important
`concern; it allowed the placement of specific circuit modules to be dictated by the requirements of
`the algorithm and not by the limited interconnect of the platform. There are 16 identical modules in
`the Shapesum and 16 more identical modules in the final correlation. Along with these there is a
`divide, a hit accumulator and 2 delay modules (see Figure 8).”
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`
`
`
`10
`
`

`

`Exhibit F-11: Chunky SLD
`
`[1C] forming at least two of
`said functional units at the at
`least one reconfigurable
`processor to perform said
`calculation
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`
`Chunky SLD at Figure 8:
`
`
`
`
`
`Chunky SLD at 198: “On one SPLASH 2 board two processing units can be installed yielding the
`ability to process 1 orientation (40 chunks) every .244 seconds (.350 seconds at 13.2 MHz).”
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`
`11
`
`

`

`Exhibit F-11: Chunky SLD
`
`[1D] wherein only functional
`units needed to solve the
`calculation are formed and
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`
`Chunky SLD at Figure 8:
`
`
`
`
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at Figure 8:
`
`12
`
`[1E] wherein each formed
`functional unit at the at least
`one reconfigurable processor
`interconnects with each other
`formed functional unit at the at
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`
`least one reconfigurable
`processor based on
`reconfigurable routing
`resources within the at least
`one reconfigurable processor
`as established at formation
`
`
`
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at Figure 8:
`
`
`[1F] wherein lines of code of
`said calculation are formed as
`clusters of functional units
`within the at least one
`reconfigurable processor;
`
`13
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`
`
`Chunky SLD at 198: “On one SPLASH 2 board two processing units can be installed yielding the
`ability to process 1 orientation (40 chunks) every .244 seconds (.350 seconds at 13.2 MHz).”
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at 195: “Note that valid output comes every three cycles because the template is three
`rows tall. All processing elements are actively processing 3 pixel values at all times. The SPLASH2
`implementation works just like the example except for the size of the columns (16 pixels instead of
`three) and the data format (eight-bit instead of one-bit).”
`
`Chunky SLD at Figure 5:
`
`
`14
`
`[1G] utilizing a first of said
`formed functional units to
`operate upon a subsequent data
`dimension of said calculation
`forming a first computational
`loop; and substantially
`concurrently utilizing a second
`of said formed functional units
`to operate upon a previous data
`dimension of said calculation
`
`

`

`Exhibit F-11: Chunky SLD
`
`forming a second
`computational loop
`
`
`
`
`Chunky SLD at 196-97: “4.3 ATR Implementation on Splash 2
`Similar to the example, the SPLASH2 implementation processes one pixel at a time and loads them
`in column order so that the partial sums can be generated and passed from column to column. All
`template data are stored in the memories adjacent to the FPGAs on the SPLASH2 boards. Each
`memory can hold several thousand templates thus making it possible to store all of the templates for
`a single class (5760) on a single SPLASH2 board. There is sufficient room in the FPGA design to
`store a single template. The templates are switched by reading the new template data out of the
`
`15
`
`

`

`Exhibit F-11: Chunky SLD
`
`231424 compute cycles=0.14%.
`318 flush cycles
`
`memory and storing it within the FPGA. However, because this implementation is deeply pipelined,
`it is necessary to flush all current data from the system when switching to a new template. The
`overhead from the flushing operation is
`
`During each clock cycle, a new pixel arrives at the FPGA. If the template bit corresponding to this
`pixel is on then the incoming pixel is added to the current partial sum. Each 16 clock cycles, this
`partial sum is then passed on to the next column and a new partial sum is received from the previous
`column. The last column computes a complete Shapesum every 16 cycles (one column). The final
`correlation of the Bright and Surround templates with the thresholded chip data works similarly
`except there are two correlations (one for each template).
`
`Intermediate hit values are stored in a table, referred to as the hit-table, in one of the local memories.
`Each location in the table corresponds to an x-y offset of a chip, the origin of a single correlation.
`For each offset, if a chunk “hits”, then the corresponding location in this table is incremented. Thus
`the table contains the accumulated hit values for all chunks and all offsets that have been computed
`to that point. Hits are computed according to Equation 1. First, each Bsum and Ssum value is
`compared to its corresponding minimum value. Second, the threshold value corresponding to each
`Bsum and Ssum is checked to see if it is between a certain minimum and maximum value. For reasons
`of efficiency, the threshold value is actually examined earlier in the process and a zero for the
`threshold is stored in lookup-table memory if it is out of bounds. This works correctly because if the
`threshold is zero, it will cause the Bsum to be zero, which will in turn cause the Bsum comparison to
`fail. Otherwise, if all three of these tests come back true then a hit has been found for the
`corresponding offset (see Equation 1) and the corresponding location in the hit-table is incremented.
`After the 40 templates are tested against the same chip the two offsets with the highest accumulated
`hit values are written into memory where the host computer can read them. This is accomplished by
`examining the hit values during this process and retaining the top two values in special memory
`locations. These final two hit values (which represent the top two orientations for a specific class)
`are used in the FI step.
`
`For the SPLASH2 board, as with most FPGA systems, partitioning is a major issue. The design
`needed to be modular so that different design modules could be reassigned to different FPGAs as
`necessary. This is where the column modules were so valuable (see Figure 8).”
`
`
`16
`
`

`

`Exhibit F-11: Chunky SLD
`
`
`Chunky SLD at Figure 8:
`
`
`
`
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at 195: “Note that valid output comes every three cycles because the template is three
`rows tall. All processing elements are actively processing 3 pixel values at all times. The SPLASH2
`implementation works just like the example except for the size of the columns (16 pixels instead of
`three) and the data format (eight-bit instead of one-bit).”
`
`
`17
`
`[1H] wherein said
`implementation of said
`calculation enables said first
`computational loop and said
`second computational loop to
`execute concurrently and pass
`computed data seamlessly
`between said computational
`loops.
`
`

`

`Exhibit F-11: Chunky SLD
`
`Chunky SLD at Figure 5:
`
`
`
`Chunky SLD at 196-97: “4.3 ATR Implementation on Splash 2
`Similar to the example, the SPLASH2 implementation processes one pixel at a time and loads them
`in column order so that the partial sums can be generated and passed from column to column. All
`template data are stored in the memories adjacent to the FPGAs on the SPLASH2 boards. Each
`memory can hold several thousand templates thus making it possible to store all of the templates for
`
`
`
`18
`
`

`

`Exhibit F-11: Chunky SLD
`
`231424 compute cycles=0.14%.
`318 flush cycles
`
`a single class (5760) on a single SPLASH2 board. There is sufficient room in the FPGA design to
`store a single template. The templates are switched by reading the new template data out of the
`memory and storing it within the FPGA. However, because this implementation is deeply pipelined,
`it is necessary to flush all current data from the system when switching to a new template. The
`overhead from the flushing operation is
`
`During each clock cycle, a new pixel arrives at the FPGA. If the template bit corresponding to this
`pixel is on then the incoming pixel is added to the current partial sum. Each 16 clock cycles, this
`partial sum is then passed on to the next column and a new partial sum is received from the previous
`column. The last column computes a complete Shapesum every 16 cycles (one column). The final
`correlation of the Bright and Surround templates with the thresholded chip data works similarly
`except there are two correlations (one for each template).
`
`Intermediate hit values are stored in a table, referred to as the hit-table, in one of the local memories.
`Each location in the table corresponds to an x-y offset of a chip, the origin of a single correlation.
`For each offset, if a chunk “hits”, then the corresponding location in this table is incremented. Thus
`the table contains the accumulated hit values for all chunks and all offsets that have been computed
`to that point. Hits are computed according to Equation 1. First, each Bsum and Ssum value is
`compared to its corresponding minimum value. Second, the threshold value corresponding to each
`Bsum and Ssum is checked to see if it is between a certain minimum and maximum value. For reasons
`of efficiency, the threshold value is actually examined earlier in the process and a zero for the
`threshold is stored in lookup-table memory if it is out of bounds. This works correctly because if the
`threshold is zero, it will cause the Bsum to be zero, which will in turn cause the Bsum comparison to
`fail. Otherwise, if all three of these tests come back true then a hit has been found for the
`corresponding offset (see Equation 1) and the corresponding location in the hit-table is incremented.
`After the 40 templates are tested against the same chip the two offsets with the highest accumulated
`hit values are written into memory where the host computer can read them. This is accomplished by
`examining the hit values during this process and retaining the top two values in special memory
`locations. These final two hit values (which represent the top two orientations for a specific class)
`are used in the FI step.
`
`
`19
`
`

`

`Exhibit F-11: Chunky SLD
`
`For the SPLASH2 board, as with most FPGA systems, partitioning is a major issue. The design
`needed to be modular so that different design modules could be reassigned to different FPGAs as
`necessary. This is where the column modules were so valuable (see Figure 8).”
`
`
`Chunky SLD at Figure 8:
`
`
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`
`
`
`[8] The method of claim 1
`wherein said calculation
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`
`20
`
`

`

`comprises a JPEG image
`compression calculation.
`
`[9] The method of claim 1
`wherein said calculation
`comprises an MPEG image
`compression calculation.
`
`[17] The method of claim 1
`wherein said calculation
`comprises a search algorithm
`for an image search
`
`Exhibit F-11: Chunky SLD
`
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Chunky SLD alone
`or in combination with one or more references, discloses:
`
`Chunky SLD at 192 (“2 Automatic Target Recognition
`he goal of a typical ATR system is to analyze a digital representation of a scene and locate/identify
`objects that are of interest. Although this goal is conceptually simple, ATR systems have extremely
`demanding I/0 and computational requirements: image data are large, can be generated in real-time,
`and must be processed quickly so that results remain relevant in a dynamic environment. The
`common use of special-purpose hardware in nearly all high-performance ATR systems is a clear
`indication of the computational complexity of these systems.
`
`This paper details the implementation of an existing ATR algorithm on SPLASH2. The algorithm in
`question was developed at Sandia National Laboratories and was designed to detect partially
`obscured targets in Synthetic Aperture Radar (SAR) images. It is commonly referred to as Chunky
`SLD, so named for the second step of the algorithm that differentiates this algorithm from others
`developed at Sandia. This algorithm consists of the following three steps: (1) Focus of Attention
`(FOA), (2) Second-Level Detection (SLD), and (3) Final Identification (FI). Each of these steps will
`now be introduced so that the algorithm implementation can be understood in its operating
`context.”)
`
`Chunky SLD at Figure 1:
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`21
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`

`

`Exhibit F-11: Chunky SLD
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`
`Chunky SLD at 193: “2.1 Focus of Attention (FOA)
`Focus of attention is the first step of the ATR process and uses image morphology techniques to
`detect potential targets in SAR data. FOA operates on “down-sampled” SAR images that are
`approximately 600-1000 pixels on a side. Once FOA detects a potential target, it determines the
`approximate center of the potential target and creates 2 x down-sampled subimages of the original
`SAR data where each subimage contains a single target centered within the subimage. These
`subimages are referred to as chips and are 128 x 128 pixels.”
`
`Chunky SLD at 193: “Each pair of templates consists of a Bright template and a Surround template.
`The Bright template is a representation of expected reflections directly from surfaces of a salient
`target feature while the Surround template represents expected absorption in the immediate area
`surrounding the target feature. Each pair of a Bright and Surround template is referred to as a chunk,
`so called because each pair of templates represents a “chunk” of the overall target. Each set of 40
`chunks represents a single target at a specific rotation. There are 72 orientations, each representing a
`different target orientation and radar incidence angle. Each set of 72 orientations is referred to as a
`class and is the complete set of templates that must be correlated with a chip to detect the presence
`of a specific target.”
`
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`22
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`

`

`Exhibit F-11: Chunky SLD
`
`Chunky SLD at 193-94: “The first step of the Chunky SLD algorithm is to correlate the chip and the
`Bright template. This correlation value is used to compute a value that will be used to threshold the
`incoming chip data, converting the 8-bit chip image into a binary image. The equations describing
`this process are shown below.
`
`
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`
`
`The values obtained by correlating the Bright and Surround templates with the binarized chip (Bsum
`and Ssum) are checked against minimum values to generate a “hit value” for each offset in the chip.
`The threshold value is also checked to see if it falls in an acceptable range when generating the hit
`values.”
`
`Chunky SLD at Figure 5:
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`23
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`

`

`Exhibit F-11: Chunky SLD
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`
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`Chunky SLD at 196-97: “4.3 ATR Implementation on Splash 2
`Similar to the example, the SPLASH2 implementation processes one pixel at a time and loads them
`in column order so that the partial sums can be generated and passed from column to column. All
`template data are stored in the memories adjacent to the FPGAs on the SPLASH2 boards. Each
`memory can hold several thousand templates thus making it possible to store all of the templates for
`a single class (5760) on a single SPLASH2 board. There is sufficient room in the FPGA design to
`store a single template. The templ