Asserted Claim of ’800
`Patent
`[1A] A method for data
`processing in a
`reconfigurable
`computing system, the
`reconfigurable
`computing system
`comprising at least one
`reconfigurable
`processor, the
`reconfigurable processor
`comprising a plurality of
`functional units, said
`method comprising:
`
`Exemplary Disclosure of Splash 2
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in alleging that
`any of Defendant’s accused products satisfy this claim limitation, Buell alone or in combination with one
`or more references, discloses:
`
`Buell at 11: “The basic building block from which Splash 2 is made is the Xilinx XC4010 FPGA [3, 4]. As
`mentioned in Chapter 1, the XC4010 contains a 20 × 20 array of Configurable Logic Blocks (CLBs).”
`
`Buell at 11: “Figure 2.2 illustrates the routing structure of the XC4000 series FPGA. Connecting the CLBs
`are three types of signal routing resources including a single-length interconnect between adjacent switch
`boxes: “S" in Figure 2.2), a double-length interconnect between alternate switch boxes, and a set of long
`lines that span the width and height of the chip. The switch boxes contain programmable switches that
`allow each segment to connect to three others. Configuration of the FPGA is done by loading a bit file into
`on-chip RAM; the hardware to do this in Splash 2 is implicit in our description in this chapter of the
`general architecture and is discussed in greater length in Chapter 6.”
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 1
`
`

`

`Asserted Claim of ’800
`Patent
`
`
`Exemplary Disclosure of Splash 2
`
`Buell at FIG. 2.2:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 2
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`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at FIG. 2.4
`
`
`
`Buell at 16: “The Splash 2 Array Board is detailed in Figure 2.4. Each Array Board contains 17 Xilinx
`XC4010 FPGA chips as processing elements. Sixteen of these, X1 through X16, form the processing array
`and are connected with a 36-bit-wide data path linearly and via a crossbar. To each FPGA is connected
`512 Kbytes of memory. Throughout the Splash 2 system, the normal data object has been assumed to be
`32 bits, augmented where possible and sensible with four tag bits. Here, in the connection from FPGA to
`memory, we find the one instance in which this design has been compromised. Three 36-bit-wide data
`paths, 18 bits for a memory address, and 32 bits for memory data would have left far too few of the 160
`total pins for controlling each FPGA. The compromise was to reduce the memory data width to 16 bits.”
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 3
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 97: “With the onset of the Human Genome Initiative [3] and constant advances in genetic
`sequencing technology, genetic sequence data are being generated at an ever increasing rate. As a result,
`biologists are faced with an influx of new sequences that they would like to classify and study by
`comparing them to existing databases. The analysis of a newly generated sequence typically involves
`searching the databases for similar sequences. With the enormous size of the databases, fast methods are
`needed for comparing sequences [11].
`
`Buell at Figure 8.1:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 4
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 97: “ln this chapter, we describe two systolic array architectures for sequence comparison and
`their implementations on the Splash 2 programmable logic array.”
`
`Buell at 100: “The locality of reference shown in Figure 8.3 can be exploited to produce systolic
`algorithms in which communication is limited to adjacent processors….
`
`The systolic architecture and data flow shown in Figure 8.5 were used in the design of P-NAC of Lipton
`and Lopresti [12], a custom VLSI chip for DNA sequence comparison. Each processing element (PE)
`computes the distances along a particular diagonal of the distance matrix.”
`
`Buell at 107: “8.3.3 Bidirectional Array
`For the DNA version of the bidirectional array, each of the 16 array FPGAs (Xl to X16) contains 24 PEs,
`making a total of 384 PEs in a one-board Splash 2 system. The protein version packs 64 PEs into a one-
`board Splash 2 system. Timing results from XDELAY give a theoretical maximum throughput of 5.5
`million characters per second for the DNA version and 3.5 million characters per second for the protein
`version.”
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 5
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`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at Figure 8.5:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 6
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`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at Figure 8.6:
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`
`Buell at Figure 8.7:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 7
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 104: “The unidirectional PE is diagrammed in Figure 8.10. In this configuration, each PE
`computes the distances in one row of the distance matrix. At each time step, the PEs compute the distances
`along a single antidiagonal in the distance matrix, as depicted in Figure 8.4. Each PE stores two distances,
`DST and PDST.”
`
`Buell at 107: “8.3.4 Unidirectional Array
`In the DNA version of the unidirectional array, each of the 16 array FPGAs (X1 to X16) holds 14 PEs. In
`addition, the two interface FPGAs contain 12 PEs each, making a total of 248 PEs in a one-Array-Board
`Splash 2 system. Timing results from XDELAY give a theoretical maximum throughput of 12 million
`characters per second for the DNA version and 8 million characters per second for the protein version.”
`
`Buell at 108: “…the programmability and reprogrammability of Splash 2 allowed for experimentation and
`incremental refinement that could not have been afforded on a less flexible system.”
`
`Buell at 108: “On uniprocessor machines, a straightforward implementation of the dynamic programming
`algorithm in the C language is used in the benchmark. On multiprocessor machines, a parallel
`implementation of the dynamic programming algorithm is used.”
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 8
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at Figure 8.9:
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`
`Buell at Figure 8.10:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 9
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at Figure 8.12:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 10
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have been
`obvious to a person of ordinary skill in the art considering this reference in combination with the
`knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the disclosures in
`one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 11
`
`

`

`Asserted Claim of ’800
`Patent
`[1B] transforming an
`algorithm into a data
`driven calculation that is
`implemented by said
`reconfigurable
`computing system at the
`at least one
`reconfigurable
`processor;
`
`Exemplary Disclosure of Splash 2
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in alleging that
`any of Defendant’s accused products satisfy this claim limitation, Buell alone or in combination with one
`or more references, discloses:
`
`Buell at 47: “The success of Splash 2, and of custom computing in general, has been made possible by the
`confluence of two important technologies: infinitely reprogrammable logic arrays (static RAM-based
`FPGAs) and high-level CAD software. Over the past few years the CAD industry has made significant
`advances in automatic generation of hardware design from high level specification. This process may be
`divided into two steps: logic synthesis and physical mapping. Logic synthesis is the process by which
`procedural descriptions of algorithms are mapped into Boolean logic gates, bypassing traditional structural
`techniques such as schematic capture. The physical mapping process converts the resulting gate list into a
`specific hardware technology, such as the static RAM- (SRAM-) based FPGAs used in Splash 2. Together,
`these technologies move the task of application development for custom computing from the realm of
`hardware design into the realm of software programming.”
`
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 12
`
`

`

`Asserted Claim of ’800
`Patent
`
`
`Exemplary Disclosure of Splash 2
`
`Buell at FIG. 5.3
`
`
`
`
`Buell at 53: “A mix of logic synthesis and standard compilation techniques are used to compile the VHDL
`programs into FPGA configurations, as shown in Figure 5.3. The VHDL Code that was developed in the
`simulation environment (Figure 5.2) is compiled with the same VHDL Library used to produce the Splash
`2 object module. The logic synthesis tools from Synopsys Inc.[13, 14] map the VHDL code into a gate list.
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 13
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`During the course of the Splash 2 project we used two different generations of Synopsys logic synthesis
`tools: the version 2.2 Design Compiler [12] and the version 3.0 FPGA Compiler [14].”
`
`Buell at 70: “6.4 COMPILATION
`A mix of logic synthesis and standard compilation techniques are used to compile VHDL programs into
`FPGA configurations. The logic synthesis tools from Synopsys Inc. [3] are used to map the VHDL code
`into a gate list. A custom peephole optimizer is then applied to the gate list to perform a variety of Xilinx-
`specific and Splash 2-specific optimizations. The resulting gate list is then mapped into the CLB structures
`and placed and routed using the Xilinx [4] tool package. The Xilinx tools are also used to extract the
`detailed timing information from the placed and routed design. This information may be used directly to
`manually optimize the design, or it may be used to construct a new structural VHDL model for each chip,
`which may be resimulated by the Splash 2 simulator to provide detailed timing analysis.”
`
`Buell at 70: “6.4.1 Logic Synthesis
`In 1991, FPGA technology was still quite new and confined mainly to board-level "glue logic"
`applications. Consequently, very few commercial CAD tool vendors were targeting FPGAs for logic
`synthesis. After evaluating the few tools on the market, we chose to base our compiler on the Synopsys
`Design Compiler. This choice required the development of a custom technology library that allowed the
`Design Compiler to produce a technology-independent gate list. It was also necessary to write a net list
`conversion program to translate that generic gate list into a technology-dependent form suitable for the
`physical mapping tools.”
`
`Buell at 71: “The physical mapping of the design from XNF to a loadable bitstream is handled by the
`Xilinx-provided tools. The placement and routing tool, PPR, reads the XNF net list and produces an
`"LCA" file, which contains all of the configuration information in an ASCII format. The program makebits
`converts the LCA file into a bitstream format, called a "BIT" file. Makebits also produces an "LL" file that
`contains a table-mapping CLB and lOB flip-flops to positions in the readback bitstream. Another Unix
`shell script (xnf2bit) provides a convenient interface to the physical mapping tools and the symbol table
`creation.”
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 14
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 98: “8.1.2 Dynamic Programming Algorithm
`
`The edit distance can be computed with a well-known dynamic programming algorithm, which has an
`interesting history of independent discovery as devised by Sankoff and Kruskal [17]. We use the following
`formulation.”
`
`
`
`
`
`Buell at 98: “A straightforward sequential implementation of the dynamic programming algorithm requires
`O (mn) time and O (min (m, n)) space to compute the edit distance.”
`
`Buell at 100: “Masek and Patterson (16) give an algorithm with time performance of O (n2/log n) for
`sequences of length n, provided that the sequence alphabet is finite and all costs are integers. However, for
`a particular implementation, they observe that their algorithm performs faster than the basic dynamic
`programming algorithm only for sequences of length 262,419 or longer. Better time performance can be
`achieved by exploiting the inherent parallelism in Equation (8.2). One notable property of the dynamic
`programming recurrence is that each entry in the distance matrix depends on adjacent entries, as
`diagrammed in Figure 8.3. This property has been the basis for many parallel algorithms for computing the
`edit distance…”
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 15
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 100: “8.2 SYSTOLIC SEQUENCE COMPARISON
`
`The locality of reference shown in Figure 8.3 can be exploited to produce systolic algorithms in which
`communication is limited to adjacent processors.
`
`There are several ways to map the edit distance computation onto a linear systolic array. We describe two
`such mappings [bidirectional and unidirectional]. Both exploit the locality of reference by computing the
`entries along each antidiagonal in parallel, as shown in Figure 8.4….
`
`Buell at Figure 8.4:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 16
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 100: “The systolic architecture and data flow shown in Figure 8.5 were used in the design of P-
`NAC of Lipton and Lopresti [12], a custom VLSI chip for DNA sequence comparison….
`
`Each processing clement (PE) [of the bi-directional array] computes the distances along a particular
`diagonal of the distance matrix.”
`
`Buell at Figure 8.5:
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`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 17
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 100: “A block diagram of the [bidirectional] PE and a listing of the algorithm it executes are
`shown in Figures 8.6 and 8.7, respectively.”
`
`Buell at Figure 8.6:
`
`
`
`Buell at Figure 8.7:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 18
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 101: “The source and target sequences are streamed through the [bidirectional] array in opposite
`directions. A comparison is performed [only] when a source character and a target character meet in a
`PE.”
`
`Buell at 102: “The source and target sequences enter the [bidirectional] array on opposite ends and flow in
`opposite directions at the same speed. Successive characters in the source and target sequences are
`separated by a null character for proper timing. In addition, there is one distance stream associated with
`each character stream. At each step, the contents of the streams represent the characters to be compared
`and the distances along one of the antidiagonals of the distance matrix. At the end of the computation, the
`resulting edit distance is transported out of the array on the distance streams.”
`
`Buell at 104: “Both the bidirectional and unidirectional systolic arrays have been implemented on
`the Splash 2 programmable logic array, with versions for DNA and protein sequences”
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 19
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 103: “The architecture and data flow of the unidirectional array are shown in Figure 8.9. As the
`name suggests, data flows through the unidirectional array in one direction. The source sequence is loaded
`once and stored in the array starting from the leftmost PE. The target sequences arc streamed through the
`array…”
`
`Buell at Figure 8.9:
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`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 20
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 104: “The algorithm executed by each PE in the unidirectional array is listed in Fig. 8.12. As
`shown, the algorithm compares one source sequence to a single target sequence.”
`
`Buell at Figure 8.12:
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`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 21
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 104: “The unidirectional PE is diagrammed in Figure 8.10. In this configuration, each PE
`computes the distances in one row of the distance matrix. At each time step, the PEs compute the distances
`along a single antidiagonal in the distance matrix, as depicted in Figure 8.4. Each PE stores two distances,
`DST and PDST. Denoting the previously computed value of DST and PDST as DST' and PDST',
`respectively, the computation graph for the ith PE is shown in Figure 8.11.”
`
`Buell at FIGS. 8.10 and 8.11
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 22
`
`

`

`Asserted Claim of ’800
`Patent
`
`[1C] forming at least
`two of said functional
`units at the at least one
`reconfigurable processor
`to perform said
`calculation
`
`Exemplary Disclosure of Splash 2
`
`Buell at 107: “In order to make a uniform comparison between Splash 2 and implementations of the
`dynamic programming algorithm on other architectures, we measure the performance of a solution in
`terms of the number of cells (entries in the DP distance table) updated per second (CUPS). When
`comparing two sequences of lengths n and m, a total of nm cells needs to be calculated.”
`
`Buell at 108: “Two systolic arrays for computing the edit distance between two genetic sequences have
`been presented and their implementations on Splash 2 described. The bidirectional and unidirectional
`arrays have maximum throughputs or 5.5 and 12 million characters per second, respectively, for DNA
`database search. Compared to implementations of the dynamic programming algorithm on several
`contemporary workstations and minicomputers, the Splash 2 implementations promise to deliver several
`orders of magnitude better performance”
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have been
`obvious to a person of ordinary skill in the art considering this reference in combination with the
`knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the disclosures in
`one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in alleging that
`any of Defendant’s accused products satisfy this claim limitation, Buell alone or in combination with one
`or more references, discloses:
`
`Buell at 12: “In order to reduce the signal propagation time for the carries, one would normally want to
`have the CLBs physically adjacent to one another in the final design. The Xilinx-supplied tools attempt to
`do this, and the "Hard Macros" supplied by Xilinx can be used to guarantee that a logic object is placed
`into contiguous CLBs.”
`
`Buell at 12: “Splash 2 is designed to execute either synchronously with the host or asynchronously as an
`attached processor. Programs for Splash 2 are loaded on the system by the host through the SBus
`connection.”
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 23
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`Buell at 47: “Once the partitioned implementation is determined to be functionally correct in simulation, it
`is compiled and optimized to produce a network of logic gates. This gate list is then mapped onto the
`FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module.”
`
`Buell at 53: “At the beginning of the project we chose what was then the state-of-the-art Synopsys Design
`Compiler as the basis of our compiler. This tool was not tailored specifically to the FPGA technology and
`therefore required some customization to suit our needs. We developed a technology library that allowed
`the Design Compiler to produce a generic gate list from a reasonable subset of VHDL, and a net list
`conversion program called edif2xnf. Edif2xnf parsed the hierarchical EDIF net list, flattened the structure,
`and produced another file in Xilinx Net list Format (XNF) that was suitable for mapping onto the physical
`hardware by the Xilinx-provided bitstream generation tools [17].”
`
`Buell at 72: “6.5 RUNTIME SYSTEM
`There are two host software interfaces to the Splash 2 system: a C language library that can be linked into
`an application-specific driving program, and an interactive symbolic debugger. Both interfaces are built
`upon the same underlying runtime system, and both provide the same basic functionality. The runtime
`system allows the user to open the Unix device, to map the Splash 2 memory into the host address space,
`to configure the FPGA devices and crossbar, to establish DMA data streams, and to control the system
`clock. The clock may be single-stepped, multiply-stepped, or allowed to run free. The user may also read
`and write various control registers, including the "handshake" registers.”
`
`Buell at 106: “8.3.2 Configurable Parameters
`The designs of both systolic arrays are not specific to a particular alphabet or cost function. The sequence
`alphabet and cost function are defined in an VHDL configuration file and can be customized for a
`particular sequence comparison application. A change in the parameters, however, would require a
`recompilation of the VHDL code. Versions for comparing DNA and protein sequences have been
`implemented.”
`
`Buell at 107: “8.3.3 Bidirectional Array
`For the DNA version of the bidirectional array, each of the 16 array FPGAs (Xl to X16) contains 24 PEs,
`making a total of 384 PEs in a one-board Splash 2 system. The protein version packs 64 PEs into a one-
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 24
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`board Splash 2 system. Timing results from XDELAY give a theoretical maximum throughput of 5.5
`million characters per second for the DNA version and 3.5 million characters per second for the protein
`version.”
`
`
`
`Buell at 107: “8.3.4 Unidirectional Array
`In the DNA version of the unidirectional array, each of the 16 array FPGAs (X1 to X16) holds 14 PEs. In
`addition, the two interface FPGAs contain 12 PEs each, making a total of 248 PEs in a one-Array-Board
`Splash 2 system. Timing results from XDELAY give a theoretical maximum throughput of 12 million
`characters per second for the DNA version and 8 million characters per second for the protein version.”
`
`Buell at Figure 8.8:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 25
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`
`
`Buell at 104: “Each PE stores two distances, DST and PDST. Denoting the previously computed value of
`DST and PDST as DST' and PDST', respectively, the computation graph for the ith PE is shown in Figure
`8.11.”
`
`Buell at Figure 8.11:
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 26
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`[1D] wherein only
`functional units needed
`to solve the calculation
`are formed
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have been
`obvious to a person of ordinary skill in the art considering this reference in combination with the
`knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the disclosures in
`one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in alleging that
`any of Defendant’s accused products satisfy this claim limitation, Buell alone or in combination with one
`or more references, discloses:
`
`Buell at 47: “With these goals in mind we chose to base the Splash 2 programming environment on the
`VHSIC1 Hardware Description Language (VHDL) [6, 10] and modem Computer Aided Design (CAD)
`tools such as simulation and logic synthesis. Applications for Splash 2 are developed by writing behavioral
`descriptions of algorithms in VHDL, which are then iteratively refined and debugged within the Splash 2
`simulator. During the course of this iteration, the VHDL implementation is manually partitioned by the
`programmer into a set of individual FPGA programs. Once the partitioned implementation is determined to
`be functionally correct in simulation, it is compiled and optimized to produce a network of logic gates.
`This gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form
`a loadable FPGA object module.”
`
`Buell at 101: “The source and target sequences are streamed through the [bidirectional] array in opposite
`directions. A comparison is performed [only] when a source character and a target character meet in a
`PE.”
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 27
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`
`Buell at 103: “At each computational step, at most half of the PEs are active.”
`
`Buell at 106: “The designs of both systolic arrays are not specific to a particular alphabet or cost function.
`The sequence alphabet and cost function are defined in an VHDL configuration file and can be customized
`for a particular sequence comparison application. A change in the parameters, however, would require a
`recompilation of the VHDL code. Versions for comparing DNA and protein sequences have been
`implemented.”
`
`Buell at 120: “The goal of this chapter is threefold. First, it describes a successful application using Splash
`2. Second, we demonstrate that a suitable mapping of an algorithm to a given architecture results in
`excellent performance. Third, we illustrate how FPGAs can facilitate this mapping process without
`sacrificing speed and flexibility. In fact, FPGAs offer greater flexibilty since the hardware is customized to
`meet the requirements of the algorithm.”
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have been
`obvious to a person of ordinary skill in the art considering this reference in combination with the
`knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the disclosures in
`one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 28
`
`

`

`Asserted Claim of ’800
`Patent
`[1E] and wherein each
`formed functional unit at
`the at least one
`reconfigurable processor
`interconnects with each
`other formed functional
`unit at the at least one
`reconfigurable processor
`based on reconfigurable
`routing resources within
`the at least one
`reconfigurable processor
`as established at
`formation
`
`
`Exemplary Disclosure of Splash 2
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in alleging that
`any of Defendant’s accused products satisfy this claim limitation, Buell alone or in combination with one
`or more references, discloses:
`
`Buell at 4: “Connecting the CLBs to one another and to special Input Output Blocks (IOBs) on the
`periphery of the chip are routing resources running from CLB to CLB, skipping one CLB, or running the
`full length of the chip. Configuration of the FPGA is done by loading a bit file onto on-chip RAM.”
`
`Buell at 11: “Figure 2.2 illustrates the routing structure of the XC4000 series FPGA. Connecting
`the CLBs are three types of signal routing resources including a single-length interconnect between
`adjacent switch boxes: “S" in Figure 2.2), a double-length interconnect between alternate switch boxes,
`and a set of long lines that span the width and height of the chip. The switch boxes contain programmable
`switches that allow each segment to connect to three others. Configuration of the FPGA is done by loading
`a bit file into on-chip RAM; the hardware to do this in Splash 2 is implicit in our description in this chapter
`of the general architecture and is discussed in greater length in Chapter 6.”
`
`Buell at FIG. 2.2
`
`
`
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 29
`
`

`

`Asserted Claim of ’800
`Patent
`
`
`Exemplary Disclosure of Splash 2
`
`Buell at FIG. 2.4
`
`
`
`
`Buell at 16: “The crossbar for Splash 2 is a truly unique feature. The 36-bit-wide path is made by
`aggregating nine 4-bit Texas Instruments SN74ACT8841 crossbar chips [2]. Each such chip can be loaded
`at startup with as many as eight different configurations, with the particular configuration in effect being
`chosen under program control during execution of a computation. Furthermore, this choice can be made
`almost on a tick-by-tick basis. The potential thus existed at the beginning of the design of this machine for
`each of the nine nibbles to have up to eight sources and destinations independent of the other nibbles and
`varying among the eight possibilities during the computation. This rather formidable choice of possibilities
`was only slightly reduced when pin constraints on the FPGAs X1 through X16 forced the low-eight
`nibbles to be paired so that only five independent sources and destinations actually exist on the machine as
`built. The crossbar, however, permits most "reasonable" configurations to be realized relatively simply.”
`
`Buell at 48: “The physical mapping [3, 16] process converts the generic gate list produced by logic
`synthesis into a configuration bitstream for the particular FPGA by partitioning the gates into logic blocks,
`placing the logic blocks into the FPGA, and routing the signal nets between the blocks.”
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2055, p. 30
`
`

`

`Asserted Claim of ’800
`Patent
`
`Exemplary Disclosure of Splash 2
`
`
`Buell at 70: “6.4 COMPILATION
`A mix of logic synthesis and standard compilation techniques are used to compile VHDL programs into
`FPGA configurations. The logic synthesis tools from Synopsys Inc. [3] are used to map the VHDL code
`into a gate list. A custom peephole optimizer is then applied to the gate list to perform a variety of Xilinx-
`specific and Splash 2- specific optimizations. The resulting gate list is then mapped into the CLB
`structures and placed and routed using the Xilinx [4] tool package. The Xilinx tools are also used to extract
`the detailed timing information from the placed and routed design. This information may be used directly
`to manually optimize the design, or it may be used to construct a new structural VHDL model for each
`chip, which may be resimulated by the Splash 2 simulator to provide detailed timing analysis.”
`
`Buell at 102: “The source and target sequences enter the [bidirectional] array on opposite ends and flow in
`opposite directions at the same speed.”
`
`Buell at 103: “As the name suggests, data flows through the unidirectional array in one direction. The
`source sequence is loaded once and s