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`Petitioner Microsoft Corporation - EX. 1066, p. 523
`
`

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`
`Petitioner Microsoft Corporatio . EX. 1066, p. 524
`
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`Petitioner Microsoft Corporation - EX. 1066, p. 525
`
`

`

`
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`!
`
`l
`
`
`
`
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 526
`Petitioner Microsoft Corporatio ; EX. 1066, p. 526
`
`

`

`Index
`
`
`
`Ada, 36, 50
`AFIS, see Automatic Fingerprint
`Identification System
`Algotronix, Ltd., 4, 7, 95
`Analytic Instruments Inc., 24
`Aptix, 181
`arch, fingerprint, 123
`Array Board, 12, 13, 19
`architecture, 16—17
`
`implementation, 25—30
`programming, 29
`Atmel Corp, 4
`attached processors, 6, 169, 171
`Automatic Fingerprint Identification
`System, 119
`
`band-pass pyramids, 145
`Bank Register. 21
`Batley’s formula, 119
`broadcast, 17
`Brown University, 3, 95, 183
`Burroughs Corp.
`B1700, 2, I74
`bypass mode, 25
`
`C*, 80
`Center for Computing Sciences, see
`Supercomputing Research Center
`CERN, 177
`CHAMP, 6, 174
`CLB, see Configurable Logic Block
`
`clock, 18
`free—running, 57
`hardware, 24
`implementation. 24
`regulation of system, 18
`setting frequency, 58
`SIMD, 57
`.
`single—step, 18
`software, 24, 57
`variable frequency, 24
`comp . arch . fpga newsgroup, 3
`compression, 177
`Concurrent Logic, Inc., 4
`CLi6005 FPGA, 37
`Configurable Logic Block, 4
`flip-flops, I69
`configuration register, 30
`Control Element, 20
`entity declaration. 62
`implementation, 28
`programming view, 56—57
`controlfstatus register, see CSR
`convolutional filtering, 177
`coprocessors, 5—6, 169, 173474
`core point, fingerprint, 123
`corner turning, 24
`Cray Research
`YMP processor, 2
`cross-correlation example, 81
`crossbar, 16-17, 181
`configuration of, 30, 68—69
`
`201
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 527
`Petitioner Microsoft Corporation - EX. 1066, p. 527
`
`

`

`
`
`202
`
`Index
`
`crossbar continued
`dataflow modes, 170
`implementation, 28—29
`programming view, 56
`CSR, 25
`
`data—driven model, 175
`Datacube MaxVideo 200, 162
`dbC, 49, 77—95, 174, 176
`De La Rue Printrak,
`l 19
`DEC, see Digital Equipment Corp.
`Department of Defense, 180
`Development Board, 19, 57
`implementation, 21
`device driver, 74—75
`diagnostic software, 75—76
`Digital Equipment Corp., see Paris
`research lab, DEC’s
`digital signal processor. 172
`dilation, 146
`direct memory access, see DMA
`discrete Fourier transform. 147
`DMA, I2, 19
`DMA Channel
`
`daughterboard, 20
`implementation, 23
`DNA sequence, see sequence comparison
`DOD, see Department of Defense
`double loop, fingerprint, 123
`DSP, see digital signal processor
`
`edge detection, 16
`edif2xnf, 53, 56, 70
`edit distance, 98
`dynamic programming algorithm, 98
`modular encoding, 105
`erOsion, 146
`
`FBI, see Federal Bureau of Investigation
`Federal Bureau of Investigation,
`118, 183
`
`Field Programmable Gate Array, 2, 4—5,
`11, 20, 37
`architecture, 172
`fingerprint
`matching algorithm, 125—128
`performance, 137—139
`registration, 1'26
`FIR filter, 186—189
`FPGA, see Field Programmable Gate
`Array
`Futurebus+, 12, 19, 181
`
`Ganglion, 5
`Gaussian pyramid. 145, 154
`generic SIMD instructions, 82, 84
`genetic database search, see sequence
`comparison
`global 0R signal, 18, 43
`global tri—state signal, 23, 54
`Gordon Bell prize
`1989, 34
`GTS signal, see global tri-state signal
`
`handshake register, 30, 58
`hard macros, 12, 52, 61
`Henry formula, 117
`high-pass filters, 145
`host computer
`programming view, 57—58
`Hough transform, 2, 147
`Human Genome Initiative, 97
`
`IDA, see Institute for Defense Analyses
`Identification register. 25
`IEEE, 3, 50
`image expansion, 158
`image processing, 141—163, 177
`fingerprint, 119
`perfomance, 159~162
`image pyramid, 153
`image pyramid generation. 153
`image subtraction, 158
`Input Output Block, 4
`exploiting flip—flops, 56, 187
`Institute for Defense Analyses, 183
`instruction set synthesis, 84
`Intel Corp.
`8086 processor, 173
`Interface Board, 12, 19
`architecture, 17—18
`implementation, 21—25
`memory, 24
`programming view, 5'7
`interrupt register, 30
`interrupts. 24
`IOB, see Input Output Block
`
`Laplacian pyramid, 146, 157
`LDG, 32. 46, 78, 179
`LED register, 26
`LEXIS, 110
`libsplash . a, see runtime library
`Light—Emitting Diodes, see LED register
`linear data path, 13—14, 20
`
`-
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 528
`Petitioner Microsoft Corporation - EX. 1066, p. 528
`_.-‘
`
`

`

`Index
`
`203
`
`_
`Lockheed Sanders, 174
`Logic Description Generator, see LDG
`logic synthesis, 6, 48
`Logica, 119
`loop, fingerprint, 123
`low-pass filter, 144
`low-pass pyramids, 145
`
`macro instructions, 92-94
`mask register, 30
`mathematical morphology, 146
`median filtering, 146, 150453
`MEDLARS, 110
`memory
`architecture of, 44, 167—168
`host access to, 21, 28
`initialization, 69
`mapped into address space, 58
`Michigan State University, 183
`minutia, 118, 123
`matching, 126
`Model Technologies. Inc., 182
`MPL, 80
`
`National Cancer Institute
`
`Dept. of Mathematical Biology, 180
`National Center for Biotechnology
`Information, 183
`National Semiconductor Corp, 4
`NC], see National Cancer Institute
`nearest—neighbor communication, 88
`NBC Information Systems,
`1 19
`North American Morpho, 119
`
`opPar, see generic SIMD
`instructions
`
`Oxford University, 95
`
`P-NAC, 31, 97
`PAM, see Paris research lab, DEC’s
`Paris research lab, DEC’s, 166, 174
`PeRLe, 2
`PeRLe—l, 6, 171, 177
`Paris research lab, DEC‘s
`PeRLe—O, 6
`pattern recoginition systems, 121
`PeRLe, see Paris research lab, DEC’s
`physical mapping, 48
`placement and routing, 6
`poly data type, 81
`Princeton Nucleic Acid Comparator, see
`P—NAC
`
`Princeton University, 31
`PRISM, 3, 5, 183
`Processing Element, 20
`entity declaration, 61
`implementation, 26—28
`programming. 24—25
`programming view, 56-57
`Processor-in—Memory (PIM), 79
`protein sequence, see sequence
`comparison
`PRS, see pattem recoginition systems
`pyramid, 145, see Gaussian pyramid,
`Laplacian pyramid
`
`Quick and Dirty Board, see Development
`Board
`
`Quicktum Design Systems, Inc., 178
`
`rapid prototyping, 177
`RBus, 14, 20
`data register, 58
`readback. 24-25, 29
`rule in symbolic debugging, 58, 169
`real—time control, 177
`reduction operation, 80, 89—91
`reset, 25, 29
`ridge, fingerprint, 123
`robocop, 76
`RSA decryption, 2, 166
`RSA encryption, 166
`runtime library, 54, 73
`
`SBus, 12, 19
`Adapter Board, 19
`addmss space, 18, 21
`choice of, 38
`DMA performance, 75
`slave accesses, 22
`sequence comparison, 15, 100—104, 111,
`182
`
`bidirectional algorithm, 100, 103
`dbC example, 94—95
`performance, 107
`SIMD Bus, 13, 20
`data register, 58
`SIMD model, 11, 13, 17
`single-instruction multiple-data, see
`SIMD model
`size estimation, see utilization
`Sobel operators. 145
`SPARCstation 2, 12, 19, 38
`special—purpose devices, 5
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 529
`Petitioner Microsoft Corporation - EX. 1066, p. 529
`
`

`

`204
`
`Index
`
`Splash l, 6, 179
`architecture, 31—32
`Splash 2, 179
`Splash 2 Library, 51, 61
`Splash 2 simulator, 51, 66—70
`configuring, 67—68
`SRC, see Supercomputing Research
`Center
`
`Sun Microsystems, Inc., l2, 19, 38
`Supercomputing Research Center, 4
`Synopsys, Inc., 182
`Design Compiler, 53, 70
`FPGA Compiler, 53, 71, 168, 182
`systolic, 13
`
`T2 debugger, 55, 72—?3
`tags, 14
`valid data, 5?
`Tc] language, 55
`TERASYS, 79, 181, 184
`Texas Instruments
`
`1 13—1 14
`
`crossbar chip, 28, 41, 181
`text searching
`16—bit approach, 115
`8—bit implementation,
`algorithm, 111—112
`general approach, 11]
`performance, 114, 116
`Thinking Machines Corp.
`CM-2, 2, 81. 183
`CM-2X, 5
`timing analysis. 49
`tolerance box, 128
`trigger debugger, 32
`tsdb debugger, 55, 76
`
`utilization, 56
`
`valley, fingerprint. 123
`Verilog, 51
`
`VHDL, 36—37, 49—51, 182
`choice of, 36, 45
`history of, 50
`pipelining in, 189
`synchronous processes in, 187
`VHSIC initiative, 4?, 50
`Viewlogic, 32
`Virginia Polytechnic Institute
`and State University, 183
`virtual computer, 3
`VMEbus, 34, 39
`VTSplash, 142
`
`whirl, fingerprint, 123
`
`X0, 13, 17
`purpose, 43
`use in dbC, 86, 89
`use in fingerprint matching,
`132—133
`
`XACT editor, 32
`XBLOX, 168
`Xilinx, 2, 4, 7, ll
`apr tool. 33
`choice of, '38
`Netlist Format (XNF), S3
`XC3090 FPGA, 32, 182
`XC4010 FPGA, 4, 11—12,
`182
`
`XL, 15
`entity declaration, 63
`implementation, 23—24
`purpose, 43
`use in dbC, 86
`use in text search, 111
`xn fer, 54, 56, 71
`XR, 15
`implementation, 23—24
`purpose, 43
`use in text search,
`
`l 12
`
`
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 530
`'- EX. 1066, p. 530
`Petitioner Microsoft Corporatio
`
`

`

`
`
`Contributors
`
`
`A. Lynn Abbott, Bradley Department of Electrical Engineering, Virginia Polytechnic
`Institute and State University, Blacksburg, Virginia 24061. 703-231-4472
`Jeffrey M. Arnold, Center for Computing Sciences, 17100 Science Drive, Bowie,
`Maryland 20715. 301-805—7479
`_
`Peter Athanas, Bradley Department of Electrical Engineering, Virginia Polytechnic
`Institute and State University, Blacksburg, Virginia 24061. 703-231—70l0
`Duncan A. Buell, Center for Computing Sciences, 17100 Science Drive, Bowie,
`Maryland 20715. 301—805-7372
`Maya Gokhale, David Sarnoff Research Center, CN 5300, Princeton, New Jersey
`08543. 609-734-3119
`Dzung T. Hoang, Department of Computer Science, Duke University, Durham, North
`Carolina 27706. 919-660—6598
`Anil Jain, Department of Computer Science, Michigan State University, East Lan-
`sing, Michigan 48824. 517—353-5150
`Walter J. Kleinfelder, Center for Computing Sciences. 17100 Science Drive. Bowie,
`Maryland 20715. 301 —805 -7 355
`Daniel V. Pryor, Center for Computing Sciences, 17100 Science Drive, Bowie,
`Maryland 20715. 301-805-7407
`Nalini Ratha. Department of Computer Science, Michigan State University, East
`Lansing, Michigan 48824. 070 A. Jain 517-353—5150
`Diane Rover, Department of Electrical Engineering, Michigan State University, East
`Lansing, Michigan 48824. 517—353-7735
`Nabeel Shirazi, Bradley Department of Electrical Engineering, Virginia Polytechnic
`Institute and State University, Blacksburg, Virginia 24061. cfo P. Athanas 703—231-
`7010"
`Mark R. Thistle, Center for Computing Sciences, 17100 Science Drive, Bowie,
`Maryland 20715. 301-805—7413
`
`205
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 531
`Petitioner Microsoft Corporation - EX. 1066, p. 531
`
`

`

`
`
`IEEE Computer Society Press Editorial Board
`
`Advances in Computer Science and Engineering
`Editor-in-Chief
`Jon Butler. Naval Postgraduate School
`
`Associate Editor-in-Chief/Acquisitions
`Pradip K. Srimani. Colorado State University
`
`The IEEE. Computer Society Press Advances Board seeks manuscripts that describe new and sig~
`nilicant advances in computer science and engineering. Although immediate application is not neces-
`sary. ultimate application to advanced computing systems is an important quality. Publications represent
`technically substantive and clear expositions of innovative ideas.
`
`Dharma P. Agrawal, North Carolina State University
`Fluud Bolle. lBM T.J. Watson Research Center
`Vijav K. Jain, University of South Florida
`Yutaka Kanavama. Naval Postgraduate School
`Gerald M. Masson, The Johns Hopkins University
`Sudha Ram, University ofArizona
`David C. Rine, George Mason University
`A.R.K. Sastry, Rockwell lnternational Science Center
`Abhijit Sengupta, University of South Carolina
`Mukesh Singhal. Ohio State University
`Scott M. Stevens, Carnegie Mellon University
`Michael Roy Williams, The University of Calgary
`Ronald D. Williams. University of Virginia
`Lotti Zadeh. University of California, Berkeley
`
`
`
` Editorial Board
`
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`
`Additional Advances Board Titles
`
`A Probabilistic Analysis of Tesi~Response Compaction
`Slawomir Pilarski and Tiko Kameda
`
`The Cache Coherence Problem in Shared~Memory Multiprocessors: Software Solutions
`Igor Tartalja and Veljko Milutinovic
`
`The Cache Coherence Problem in Shared—Memory Maltiprocessors: Hardware Solutions
`Igor Tartalja and Veljko Milutinovic
`
`Advanced Multimicroprocessor Bus Architectures
`J anusz Zalewski
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 532
`Petitioner Microsoft Corporation - EX. 1066, p. 532
`
`

`

`
`
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`Petitioner Microsoft Corporation - Ex. 1066, p. 533
`Petitioner Microsoft Corporation - EX. 1066, p. 533
`A...
`
`

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`W...
`
`\lllllllllllllll
`
`edited by Duncan A. Buefl, Jeffrey M. Arnold, and Waite
`
`o 003 49'! 038 9_ .
`
`Details the complete Splash 2 project—the hardware and software sys—
`tems, their architecture and implementation, and the design process by
`which the architecture evolved from an earlier version machine. In addi-
`tion to the description of the machine, this book explains why Splash 2
`was engineered. It illustrates several applications in detail, allowing you
`to gain an understanding of the capabilities and the limitations of this
`kind of computing device.
`
`The Splash 2 program is significant for two reasons. First, it is part of a
`complete computer system that achieves supercomputer like perfor—
`mance on a number of different applications. The second significant
`aspect is that this large system is capable of performing real computa—
`tions on real problems. In order to understand what happens when the
`application programmer designs
`the processor architecture of
`the
`machine that executes his programs, it is necessary to see the system as
`a whole. This book looks in—depth at one of the handful of data points
`in the design space of this new kind of machine.
`
`Contents:
`
`I Custom Computing Machines: An Introduction
`0 The Architecture of Splash 2
`0 Hardware Implementation
`0
`Splash 2: The Evolution of a New Architecture
`I
`Software Architecture
`
`0
`Software Implementation
`0 A Data Parallel Programming Model
`O
`Searching Genetic Databases on Splash 2
`o
`Text Searching on Splash 2
`
`Fingerprint Matching on Splash 2
`o
`O High—Speed Image Processing with Splash 2
`o The Promise and the Problems
`.
`
`An Example Application
`
`Published by the IEEE Computer Society Press
`10662 Los Vaqueros Circle
`no. Box 3014
`LosAlamitos,CA90720-1314
`
`_
`
`139” ”'5155’7H3'X
`90000>
`
`IBEEComputerSocietyPressOrderNumberBP07413
`
`Library of Congress Number 95—4739?
`ISBN 0—8186-7413—X
`
`W 1"“
`
`3 674136
`
`9
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 534
`Petitioner Microsoft Corporation - EX. 1066, p. 534
`
`
`
`

`

`(cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3)
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`
`Petitioner Microsoft Corporation - Ex. 1066, p. 535
`
`

`

`
`
`
`
`Splash 2 : FPGAS in a custom computing machine (Book, 1996) [Wor...
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`Splash 2 : FPGAs in a custom computing
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`Author
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`Bunsen A Bus“: Jeffrey M Arnold; Walter J. _K_l§_i_n_le|_der
`
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`Brussels : IEEE Computer Society Press, 1996.
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`Editioanorrnal: I Print book : English
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`Petitioner Microsoft Corporation - Ex. 1066, p. 536
`Petitioner Microsoft Corporation - EX. 1066, p. 536
`
`

`

`
`
`Splash 2 1 FPGAS in a custom computing machine (Book, 1996) [Wor...
`
`httpsu’fwww.worldcat.org/tit]elsplash-2-fpgas-in-a-custom-computing..
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`Document Type:
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`Duncan A Eluell; Jeffrey M Arnold; Walter J Kleinfelder
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`Flnd more information about: I Duncan A Bueil El
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`OCLC Number:
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`989612266
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`Description:
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`XIV, 205 pages
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`ed. by Duncan A. Buell, Jeffrey M. Arnold and Waiter J. Kleinfelder.
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`Petitioner Microsoft Corporation - Ex. 1066, p. 537
`Petitioner Microsoft Corporation - EX. 1066, p. 537
`
`

`

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`
`Petitioner Microsoft Corporation - Ex. 1066, p. 538
`
`

`

`
`
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`Title Splash 2 : FPGAS in a custom computing machine f Duncan A. Buell. Jeffrey M. Arnold, Walter J. Kleinfelder.
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`Shelf Location Barker Library - Stacks l QA76.8.565.384 1996
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`PUbliShEd Los Alamitos. Calif. :
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`lEEE Computer Society Press. cl 996.
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`Description xiv. 205 p. : ill.
`Format Book
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`: 26 cm.
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`Bibliography Includes bibliographical references (p. 190-200) and index.
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`Electronic diqi_t_z_1_l computers ‘— Design and construction;
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`Other Author Buell, Duncan A.
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`Petitioner Microsoft Corporation - Ex. 1066, p. 539
`Petitioner Microsoft Corporation - EX. 1066, p. 5 39
`
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`Petitioner Microsoft Corporation - Ex. 1066, p. 540
`
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