Paper No. 67
`Filed: January 30, 2020
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________________
`
`MICROSOFT CORPORATION,
`
`Petitioner,
`
`v.
`
`DIRECTSTREAM, LLC,
`
`Patent Owner.
`_______________________
`
`IPR2018-01605, IPR2018-1606, IPR2018-01607
`Patent 7,620,900 B2
`
`__________________________
`
`PATENT OWNER DIRECTSTREAM, LLC’S
`DEMONSTRATIVE EXHIBITS FOR ORAL ARGUMENT
`
`
`
`Filed: January 30, 2020
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________________
`
`MICROSOFT CORPORATION,
`
`Petitioner,
`
`v.
`
`DIRECTSTREAM, LLC,
`
`Patent Owner.
`_______________________
`
`IPR2018-01605, IPR2018-1606, IPR2018-01607
`Patent 7,620,900 B2
`
`__________________________
`
`PATENT OWNER DIRECTSTREAM, LLC’S
`DEMONSTRATIVE EXHIBITS FOR ORAL ARGUMENT
`
`
`
`
`Pursuant to 37 C.F.R. §42.70(b) and the Board’s Order (Paper 57) in the
`
`above-referenced proceeding, Patent Owner DirectStream, LLC files its
`
`demonstrative exhibits for the oral hearing scheduled for February 4, 2020.
`
`
`
`
`
`Dated: January 30, 2020
`
`Respectfully submitted,
`
`
`
`
`/Alfonso Chan/
`Alfonso Chan, Reg. No. 45,964
`achan@shorechan.com
`Joseph F. DePumpo, Reg. No. 38,124
`jdepumpo@shorechan.com
`SHORE CHAN DEPUMPO LLP
`901 Main Street, Suite 330
`Dallas, Texas 75202
`Tel: (214) 593-9110
`Fax: (214) 593-9111
`
`Sean Hsu, Reg. No. 69,477
`shsu@jvllp.com
`Rajkumar Vinnakota*
`kvinnakota@jvllp.com
`G. Donald Puckett*
`dpuckett@jvllp.com
`JANIK VINNAKOTA LLP
`8111 Lyndon B. Johnson Frwy., #790
`Dallas, Texas 75251
`Tel: (214) 390-9999
`Fax: (214) 888-0219
`* Admitted Pro Hac Vice
`
`Attorneys for Patent Owner
`DirectStream, LLC
`
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`CERTIFICATE OF SERVICE
`Pursuant to 37.C.F.R. §§42.6(e)(4) and 42.25(b), the undersigned certifies that
`
`on January 30, 2020, a complete copy of the foregoing document was filed
`
`electronically through the Patent Trial and Appeal Board’s PTAB E2E System and
`
`provided, via electronic service, to the Petitioner by serving the correspondence
`
`address of record as follows:
`
`Joseph A. Micallef
`jmicallef@sidley.com
`Scott M. Border
`sborder@sidley.com
`SIDLEY AUSTIN LLP
`1501 K. Street N.W.
`Washington, DC 20005
`
`Jason P. Greenhut
`jgreenhut@sidley.com
`SIDLEY AUSTIN LLP
`1 South Dearborn
`Chicago, IL 60603
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`/Alfonso Chan/
`Alfonso Chan
`Reg. No. 45,964
`Tel: (214) 593-9110
`
`2
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`
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`Patent Owner’s Demonstratives
`February 4, 2020
`
`Microsoft Corporation, Petitioner,
`v.
`DirectStream, LLC, Patent Owner
`
`Case IPR2018-01601, -01602, -01603 (Patent No. 7,225,324 B2)
`Case IPR2018-01605, 01606, -01607 (Patent No. 7,680,800 B2)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`PODX - 1
`
`
`
`Summary of Argument
`
`Source: Response, TOC; Sur-Reply, TOC
`
`PODX - 2
`
`
`
`Summary of Argument
`
`Source: Response, TOC; Sur-Reply, TOC
`
`PODX - 3
`
`
`
`Institution Grounds
`
`Source: Institution Decision, 10-11
`
`PODX - 4
`
`
`
`Institution Grounds
`
`Source: Institution Decision, 8-9, 16-42
`
`PODX - 5
`
`
`
`1601 vs 1605 Cross-Reference
`
`•
`•
`
`1601 and 1605 Petitions pertain to related patents
`The asserted prior art is the same across both consolidated proceedings
`PO Exhibit List Description
`1601 Ex. No.
`Deposition Transcript of Harold Stone dated 5/30/19
`2066
`Stone 1987 - HPC Architecture
`2070
`Deposition Transcript of Stephen Trimberger dated 6/7/19
`2076
`U.S. Patent 6,339,819 B1
`2085
`Declaration of Jon Huppenthal dated 7/11/19
`2100
`SRC Carte TMC Programming Environment v3.0 Guide (Pre-Release)
`2107
`Declaration of Dr. Houman Homayoun dated 7/25/19
`2111
`[28] DirectHit SEC Filings, located at
`2139
`https://www.sec.gov/Archives/edgar/data/1092756/0000912057-99-010346.txt
`[44] U.S. Patent No. 8,589,666
`2155
`Declaration of Tarek El-Ghazawi dated 7/23/19
`2164
`[EL-GH08] Tarek El-Ghazawi, Esam El-Araby, Miaoqing Huang, Kris Gaj, Volodymyr Kindratenko, and
`Duncan Buell, "The Promise of High-Performance Reconfigurable Computing," IEEE Computer, vol.
`41, no. 2, pp. 69-76, February 2008
`[BUEL07] Buell, El-Ghazawi, Gaj, and Kindratenko, “High-Performance Reconfigurable Computing”
`IEEE Computer (Guest Editors Intro), March 2007 (Vol. 40, No. 3).
`[1005] Halverson, “The Functional Memory Approach to the Design of Custom Computing
`Machines,” Dissertation University of Hawaii, August 1994
`U.S. Patent No. 5,748,613
`European Patent EP 1 820 309 B1
`U.S. Patent No. 8,543,746
`U.S. Patent No. 8,352,456
`U.S. Patent Pub. No. 2010/0070730 A1
`Deposition Transcript of Dr. Harold S. Stone dated December 13, 2019
`Supplemental Declaration of Dr. Houman Homayoun Under 37 CFR §42.64(B)(2)
`
`2165
`
`2166
`
`2167
`2169
`2170
`2171
`2172
`2173
`2176
`2177
`
`1605 Ex. No.
`2065
`2069
`2075
`2084
`2101
`2108
`2112
`2140
`2156
`2166
`
`2167
`
`2168
`
`2169
`2171
`2172
`2173
`2174
`2175
`2178
`2179
`
`Source: Institution Decision, 8-9, 16-42
`
`PODX - 6
`
`
`
`Burden of Proof for Invalidity
`
`PODX - 7
`
`
`
`Legal Authority - Burden of Proof in IPRs
`
`• Petitioner bears the burden of proving by a
`preponderance of the evidence, with substantial
`evidence, that the Patent is invalid under 35 U.S.C.
`§§102 and 103
`
`• See Corning Inc. v. DSM LP Assets B.V, IPR2013-
`00048, Paper 96 at 4 (P.T.A.B. July 11, 2014) (emphasis
`in original) (“Showing a reasonable likelihood of
`prevailing [for institution] is less stringent a standard than
`prevailing by a preponderance of the evidence.”).
`
`Source: Response, 74
`
`PODX - 8
`
`
`
`Requirements for Anticipation
`
`• Under 35 U.S.C. §102, a claim is “anticipated only if
`each and every element as set forth in the claim is
`found, either expressly or inherently described, in a
`single prior art reference.” Verdegaal Bros. v. Union Oil
`Co. of Cal., 814 F.2d 628, 631, 2 USPQ2d 1051, 1053
`(Fed. Cir. 1987).
`
`Source: Response, 74
`
`PODX - 9
`
`
`
`No ambiguity
`
`• Claim elements must be described in a single reference
`with “sufficient precision and detail to establish that the
`subject matter existed in the prior art.” Verve, LLC v.
`Crane Cams, Inc., 311 F.3d 1116, 1120 (Fed. Cir. 2002);
`Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9
`USPQ2d 1913, 1920 (Fed. Cir. 1989).
`
`• Ambiguous references do not anticipate claims. Wasica
`Fin. GmbH v. Cont’l Auto. Sys., Inc., 853 F.3d 1272,
`1284 (Fed. Cir. 2017) (finding claim not invalidated
`because prior art was ambiguous on whether requisite
`disclosure would be present to a POSITA and therefore
`did not anticipate the claim).
`
`Source: Response, 75
`
`PODX - 10
`
`
`
`Requirements for Obviousness
`
`• Obviousness requires:
`– (1) “all the claimed elements were known in the prior art,”
`– (2) “one skilled in the art could have combined the elements as
`claimed by known methods with no change in their respective
`functions,” and
`– (3) “the combination yielded nothing more than predictable
`results to one of ordinary skill in the art.”
`
`• MPEP §2143(A) (emphasis added) (citing KSR, 550 U.S.
`at 416; Sakraida v. AG Pro, Inc., 425 U.S. 273, 282
`(1976); Anderson’s-Black Rock, Inc. v. Pavement
`Salvage Co., 396 U.S. 57, 62-63 (1969); Great Atl. & P.
`Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152
`(1950)).
`
`Source: Response, 110
`
`PODX - 11
`
`
`
`Requirements for Obviousness
`
`•
`
`“An invention is not obvious simply because all of the
`claimed limitations were known in the prior art at the time
`of the invention. Instead, we ask ‘whether there is a
`reason, suggestion, or motivation in the prior art that
`would lead one of ordinary skill in the art to combine the
`references, and that would also suggest a reasonable
`likelihood of success.’” Caterpillar Inc., IPR2017-02188,
`Paper 71 at 17 (Final Written Decision) (quoting Forest
`Labs, LLC v. Sigmapharm Labs., LLC, 918 F.3d 928, 934
`(Fed. Cir. 2019); Smiths Indus. Med. Sys., Inc. v. Vital
`Signs, Inc., 183 F.3d 1347, 1356 (Fed. Cir. 1999)).
`
`Source: Response, 76
`
`PODX - 12
`
`
`
`Requirements for Obviousness
`
`•
`
`In evaluating combinations of the prior art, it is not
`sufficient to say that a result may occur from a given set
`of conditions, but rather, it must occur. PersonalWeb
`Techs., LLC. v. Apple, Inc., 917 F.3d 1376, 1382 (Fed.
`Cir. 2019). If an equally plausible or more plausible
`interpretation of the prior art can be supported by
`evidence, then obviousness cannot be found through an
`application of inherency. Id.
`
`Source: Response, 77
`
`PODX - 13
`
`
`
`Requirements for Obviousness
`
`• Additionally, “it can be important to identify a reason that
`would have prompted a person of ordinary skill in the
`relevant field to combine the elements in the way the
`claimed new invention does.” KSR, 550 U.S. at 418; see
`also MPEP §2143(A).
`• And, the burden remains on Petitioner to demonstrate
`“what [skilled artisans] would have been motivated to
`do.” ZTE, 685 Fed. App’x 939-40.
`“If any of these findings cannot be made, then this
`rationale cannot be used to support a conclusion that the
`claim would have been obvious to one of ordinary skill in
`the art.” MPEP §2143(A).
`
`•
`
`Source: Response, 76-77, 110-111 ; Sur-Reply, 4-6
`
`PODX - 14
`
`
`
`Rational underpinning
`
`•
`
`“‘[R]ejections on obviousness cannot be sustained by
`mere conclusory statements; instead, there must be
`some articulated reasoning with some rational
`underpinning to support the legal conclusion of
`obviousness.’” KSR, 550 U.S. at 418.
`
`• Additionally, objective evidence relevant to
`nonobviousness (“secondary considerations”) may
`include evidence of commercial success, long-felt but
`unsolved needs, failure of others, and unexpected
`results. See Graham, 383 U.S. at 17-18.
`
`Source: Response, 76-77
`
`PODX - 15
`
`
`
`All PO evidence must be considered
`
`• All PO evidence must be considered:
`
`Source: Resp. to Pet. Motion to Exclude, 12
`
`PODX - 16
`
`
`
`Claim Construction Standard
`
`PODX - 17
`
`
`
`Claim Construction
`
`• Claim construction and determination of claim scope
`must be proper to evaluate validity
`– Phillips standard – claims given ordinary and customary
`meaning
`– Phillips standard – intrinsic evidence first
`– Phillips standard – extrinsic evidence if the intrinsic evidence is
`unclear, but it must still be consistent with intrinsic record
`– Cannot exclude preferred embodiment
`– Claim differentiation, preserve meaning and scope of different
`claims
`– Separate claim terms should be given separate meaning
`
`Source: Response, 29-33
`
`PODX - 18
`
`
`
`Claim Construction
`
`• Phillips standard – claims given ordinary and customary
`meaning
`
`• The words of a claim should be given their “ordinary and
`customary meaning,” which is “the meaning that the
`term[s] would have to a [POSITA]…at the time of the
`invention.” Phillips v. AWH Corp., 415 F.3d 1303, 1312-
`13 (Fed. Cir. 2006) (en banc).
`
`• The Board should also consider the context in which the
`term is used in an asserted claim or in related claims in
`the patent or specification. Id. at 1313
`
`Source: Response, 29-33
`
`PODX - 19
`
`
`
`Claim Construction
`
`• Broadest Reasonable Interpretation – construction must
`still be reasonable
`
`•
`
`“The broadest reasonable interpretation does not mean
`the broadest possible interpretation.” See MPEP §2111.
`“Rather, the meaning given to a claim term must be
`consistent with the ordinary and customary meaning of
`the term (unless the term has been given a special
`definition in the specification), and must be consistent
`with the use of the claim term in the specification and
`drawings.” Id.
`
`Source: Response, 32
`
`PODX - 20
`
`
`
`Patent and Claims
`
`PODX - 21
`
`
`
`Patent Summary
`
`• EX1001 – US Patent 7,225,324
`• EX1005 – US Patent 7,620,800
`
`• The ’800 Patent is a continuation of
`the ’324 Patent and both are in the
`same family
`
`Source:
`
`PODX - 22
`
`
`
`Purpose of the patent
`
`• The ’324 patent claims techniques for enhancing parallelism and
`performance in reconfigurable computing systems. EX1001,1:37-41.
`
`• At the time of the invention, “most large software applications
`achieve[d] high performance operation through the use of parallel
`processing” that required “multiple processors to work
`simultaneously on the same problem.” EX1001, 1:42-50.
`
`Source: Response, 15
`
`PODX - 23
`
`
`
`Purpose of the patent
`
`• The specification discusses the problem of passing data
`over numerous boundaries (or seams) between
`processing elements in typical multi-processor systems.
`– "In a multi-processor, microprocessor-based system, each
`processor is allocated but a relatively small portion of the total
`problem called a cell. However, to solve the total problem,
`results of one processor are often required by many adjacent
`cells because their cells interact at the boundary and upwards of
`six or more cells, all having to interact to compute results, would
`not be uncommon. Consequently, intermediate results must be
`passed around the system in order to complete the computation
`of the total problem. This, of necessity, involves numerous other
`chips and busses that run at much slower speeds than the
`microprocessor thus resulting in system performance often many
`orders of magnitude lower than the raw computation time.“
`• EX1005 at 2:26-38.
`
`Source: Response, 35
`
`PODX - 24
`
`
`
`Purpose of the patent
`
`• The problem was that “as more and more performance is
`required, so is more parallelism, resulting in ever larger
`systems” to the point that “[c]lusters exist … that have
`tens of thousands of processors and can occupy football
`fields of space.” EX1001, 1:50-56. “Systems of such a
`large physical size present many obvious downsides,
`including, among other factors, facility requirements,
`power, heat generation and reliability.” EX1001, 1:56-59.
`
`Source: Response, 15
`
`PODX - 25
`
`
`
`Purpose of the patent
`
`•
`
`In a multi-processor, microprocessor-based system, each
`processor is allocated but a relatively small portion of the total
`problem called a cell. However, to solve the total problem,
`results of one processor are often required by many adjacent
`cells because their cells interact at the boundary and upwards
`of six or more cells, all having to interact to compute results,
`would not be uncommon. Consequently, intermediate results
`must be passed around the system in order to complete the
`computation of the total problem. This, of necessity, involves
`numerous other chips and busses that run at much slower
`speeds than the microprocessor thus resulting in system
`performance often many orders of magnitude lower than the
`raw computation time.
`EX1001, 2:25-37 (emphasis added).
`
`Source: Response, 16
`
`PODX - 26
`
`
`
`Purpose of the patent
`
`• The inventors of the ’324 patent realized that this problem could be
`solved by “a processor technology … that offers orders of magnitude
`more parallelism per processor.” EX1001, 1:63-65.
`
`• And that this type of processor technology is “possible through the
`use of a reconfigurable processor” because reconfigurable
`processors can “instantiate as many functional units as may be
`required to solve the problem up to the total capacity of the
`integrated circuit chips they employ.” EX1001, 1:65-2:5.
`
`• The inventors of the ’324 patent also realized that additional, and
`less obvious, performance gains could “also be realized by
`reconfigurable processors due to the much tighter coupling of the
`parallel functional units within each chip than can be accomplished
`in a microprocessor-based computing system.” EX1001, 2:17-24.
`
`Source: Response, 15-16
`
`PODX - 27
`
`
`
`Purpose of the patent
`
`•
`
`•
`
`In a reconfigurable computing system, “since ten to one
`thousand times more computations can be performed
`within a single chip, any boundary data that is shared
`between these functional units need never leave a single
`integrated circuit chip.” EX1001, 2:38-42 (emphasis
`added).
`
`“Therefore, data moving around the system, and its
`impact on reducing overall system performance, can
`also be reduced by two or three orders of magnitude.”
`EX1001, 2:42-45.
`
`Source: Response, 16-17
`
`PODX - 28
`
`
`
`Purpose of the patent
`
`Source: EX1001, Fig. 2; Response, 44-45
`
`PODX - 29
`
`
`
`Purpose of the patent
`
`Source: EX1001, Figs. 4A, 4B; Response, 46
`
`PODX - 30
`
`
`
`Purpose of the patent
`
`Source: EX1001, Figs. 7A, 7B; Response, 45
`
`PODX - 31
`
`
`
`Purpose of the ’324 Patent – Independent claim 1
`
`Source: EX1001; Response, 53
`
`PODX - 32
`
`
`
`Purpose of the ’324 Patent – Dependent claim 15
`
`Source: EX1001; Response, 53
`
`PODX - 33
`
`
`
`Purpose of the ’800 Patent – Independent claim 1
`
`• systolic / data driven
`
`•
`
`instantiated / formed
`
`Source: EX1001; Response, 53; Sur-Reply, 43, 47-49
`
`PODX - 34
`
`
`
`Disputed Claim Terms
`
`PODX - 35
`
`
`
`Disputed Claim Terms
`
`“pass computed data seamlessly between said
`computational loops”
`
`“systolic” and “data driven”
`
`“computational loop”
`
`“stream communication”
`
`•
`
`•
`
`•
`
`•
`
`Source: Response, TOC
`
`PODX - 36
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`Source: Response, 34-35
`
`PODX - 37
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner’s construction of this term improperly
`introduces the limitation of “directly” that is not
`supportable by the intrinsic or extrinsic evidence
`
`• DirectStream’s proposed construction comes directly
`from the intrinsic record and captures the plain and
`customary understanding that “seamless” should be
`without seams or boundaries between processing
`elements. EX2111¶¶159-168, 220-223..
`
`Source: Response, 35
`
`PODX - 38
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Dr. Stone testified that the word “directly” means “the
`data goes from the first to the second without going to
`something intervening.” EX2064 at 85:14- 24;
`EX2111¶171.
`
`• But when questioned what constitutes “intervening
`structures” Dr. Stone was unable to specifically identify
`anything because “I think you’re opening a whole
`universe.” EX2064 at 86:13-18; EX2111¶172.
`
`Source: Response, 41
`
`PODX - 39
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• His answers depended on where its expert draws the
`boundaries of the processing element. EX2064 at 85:25-
`87:24; EX2111¶173.
`
`Source: Response, 41
`
`PODX - 40
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner’s construction depends on where its expert
`draws the boundaries of the processing element.
`EX2064 at 88:12-91:24; EX2111¶¶174-175.
`
`Source: Response, 41
`
`PODX - 41
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner argues in reply:
`– DirectStream also erroneously asserts Dr. Stone testified that if a
`register were between processing elements there could still be a
`direct connection between those processing elements.
`Response, 41, citing EX2064 at 86:19-88:10, 88:12-91:24. That’s
`not what he said. In the cited testimony, Dr. Stone stated he
`was talking about a register that was “within” a processing
`element, not one that was between processing elements.
`See EX2064, 86:21-87:5 (“A. I -- I'm puzzled because that -- that
`register would be within -- within the processing element in my
`mind. Q. Okay. A. If it's within the processing element as a
`register, yeah, I would put it there, then the output of that
`register, if it's connected directly to the input of the next
`processing element, would be direct.”)
`• Reply, 24-25 (emphasis added). .
`
`Source: Reply, 24-25
`
`PODX - 42
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• This is the precise problem. See Response, 41. If Dr.
`Stone deems the register to be “within,” then it must be
`direct; otherwise if he deems the register to be without,
`then it is not direct.
`
`• The same circuit would be both direct and indirect,
`depending on where the boundaries of the “processing
`element” are arbitrarily drawn with respect to intervening
`structures, which Dr. Stone concedes he could not clarify
`because it “open[s] a whole universe.”
`
`• This is not a reasonable claim construction position for
`Petitioner to take under either Phillips or BRI
`
`Source: Response, 41; Sur-Reply, 20
`
`PODX - 43
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner’s inclusion of this extraneous word into the
`construction does nothing but improperly introduce
`ambiguity and confusion. EX2111¶¶169-176.
`
`• The ambiguity arising from Petitioner’s insertion of the
`word “directly” would be avoided by simply specifying
`that the computed data is communicated over the
`reconfigurable routing resources on the chip, which all of
`the experts and the named inventor concur is what the
`patent teaches.
`– Response, 36 (Dr. Stone EX2064 at 85:14-86:12, 90:19-91:24)
`– Response, 39 (Dr. Homayoun’s report EX2111¶¶161-167, 220-
`223);
`– Reply, 21 (Mr. Huppenthal’s report, EX2100, 55).
`
`Source: Response, 41; Sur-Reply, 20-21
`
`PODX - 44
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• The specification discusses the problem of passing data
`over numerous boundaries (or seams) between
`processing elements in typical multi-processor systems.
`EX1005 at 2:26-38.
`– "In a multi-processor, microprocessor-based system, each
`processor is allocated but a relatively small portion of the total
`problem called a cell. However, to solve the total problem,
`results of one processor are often required by many adjacent
`cells because their cells interact at the boundary and upwards of
`six or more cells, all having to interact to compute results, would
`not be uncommon. Consequently, intermediate results must be
`passed around the system in order to complete the computation
`of the total problem. This, of necessity, involves numerous other
`chips and busses that run at much slower speeds than the
`microprocessor thus resulting in system performance often many
`orders of magnitude lower than the raw computation time."
`
`Source: Response, 35
`
`PODX - 45
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• The specification then discusses how the patent solves
`this problem by ensuring that “any boundary data” that is
`shared between processing units “need never leave a
`single integrated circuit chip.” EX1005 at 2:38-48.
`– On the other hand, in the use of an adaptive processor- based
`system, since ten to one thousand times more computations can
`be performed within a single chip, any boundary data that is
`shared between these functional units need never leave a single
`integrated circuit chip. Therefore, data moving around the
`system, and its impact on reducing overall system performance,
`can also be reduced by two or three orders of magnitude. This
`will allow both significant improvements in performance in certain
`applications as well as enabling certain applications to be
`performed in a practical timeframe that could not previously be
`accomplished.
`
`Source: Response, 36
`
`PODX - 46
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• The specification supports this understanding. The ’324
`patent describes one of the problems with conventional
`multi-processor computing systems is that they require
`intermediate results be passed through numerous chips
`and busses “that run at much slower speeds than the
`microprocessors thus resulting in system performance
`often many orders of magnitude lower than the raw
`computation time.” EX1001 at 2:25-37, 4:64-5:30.
`
`Source: Response, 39
`
`PODX - 47
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• By contrast, the adaptive processor-based system
`described by the ’324 patent can perform “ten to one
`thousand more computations
`… within a single chip” so that “data that is shared
`between functional need never leave a single integrated
`circuit chip.” EX1001 at 2:38-48.
`
`• The functional units are interconnected by reconfigurable
`routing resources. EX1001, Fig. 2, 5:31-51.
`
`• So, any “seamless” on chip communications use the
`reconfigurable routing resources as opposed to the
`busses and numerous chips used by conventional multi-
`processor computing systems
`
`Source: Response, 39
`
`PODX - 48
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• File History is consistent with this construction
`– “…more computations can be performed within a single chip and
`any boundary data that is shared between these functional units
`need never leave a single integrated circuit chip, eliminating the
`need for external communication protocols and simplifying
`internal communications. For example, a compiler associated
`with the reconfigurable computing system can establish stream
`connections between functional units that rely on general
`communication protocols.”
`• EX1002 at 117-118.
`
`Source: Response, 36-38
`
`PODX - 49
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• File History is consistent with this construction
`– “Khan and Gupta do not teach performing these calculations in a
`single processor. Rather multiple processors are disclosed which
`would require consideration for both internal and external
`communication protocols…. The invention as claimed states that
`communication between functional units, and not the processors,
`is communication protocol independent…. Applicants’ invention
`utilizes available resources to have an application evaluate a
`problem in a concurrent data flow sense and not in a pipeline
`sense. That is, it will “pass” a subsequent dimension of a given
`problem through a first loop of logic concurrently with the
`previous dimension of data being processed through a second
`loop. This type of concurrent operation cannot occur in the
`pipeline operation described in Khan.”
`• EX1002 at 148-150.
`
`Source: Response, 36-38
`
`PODX - 50
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• File History is consistent with this construction
`– Additionally, during prosecution, the applicant argued that the
`use of the words “protocol independent” in the claims was
`intended to “impart the ability of the functional units to
`seamlessly pass computed data between computational loops
`comprised of functional units.”
`• EX1002 at 224.
`
`Source: Response, 36-38
`
`PODX - 51
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• File History is consistent with this construction
`– The applicant explained that “communication between other
`reconfigurable processors within the system would require
`communication protocol but communication between functional
`units within an individual reconfigurable processor is free of such
`a requirement.”
`• EX1002 at 174-75; 224-25.
`
`Source: Response, 36-38
`
`PODX - 52
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Thus, the prosecution history makes clear that
`“seamlessly” is achieved by utilizing the reconfigurable
`routing resources to provide a protocol independent
`communication without the “seams” typically
`experienced at the boundary of processors.
`EX2111¶¶161-167, 220-223.
`
`Source: Response, 36
`
`PODX - 53
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner’s construction would also exclude standard
`FPGAs (including the type described in the embodiments
`of the ’324 Patent and the specific FPGA chips used in
`Petitioner’s prior art references) since standard FPGAs
`contain reconfigurable routing resources (comprising
`buffers and switches) between the configurable logic
`blocks.
`• For example, the literature on Xilinx FPGA chips shows
`buffer switch boxes and three-state buffers to connect
`two or more configurable logic blocks. EX1035 at 31;
`EX2078 at 19-29, 32-34, 37-41, 46-51, 59-65
`
`Source: Response, 40
`
`PODX - 54
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`Source: Response, 40, 102
`
`PODX - 55
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Claim differentiation with dependent claims
`
`•
`
`Inclusion of “directly” removes instantiation of anything in
`the reconfigurable routing resources, contrary to plain
`claim language and dependent claim 15
`
`Source: Response, 42, 51
`
`PODX - 56
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• EX1007 Splash2 prior art
`
`• Passing computed data
`seamlessly is not taught in
`Splash2; at best it is ambiguous
`
`Source: EX1005; Response, 96-106
`
`PODX - 57
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Splash2’s pseudocode only discloses subroutines that
`execute once for the current datum to select an
`execution path for the processor. Thus, they simply are
`not computational loops.
`
`• Additionally, Splash2 relies on the external Sun
`workstation to handle any looping, so any computational
`loop is not even instantiated on the reconfigurable
`processor. EX2111¶209; EX2167 at 14-15;
`EX2164¶¶42-43.
`
`Source: Response, 96
`
`PODX - 58
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• The workstation is separate from the array boards
`containing the FPGAs, EX1007 at 13:
`
`Source: Response, 96
`
`PODX - 59
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`•
`
`... the FPGAs must communicate with the Sun
`workstation (which is handling any looping) through the
`Sbus. EX1007 at 13; EX2111¶209; EX2167 at 14-15;
`EX2164¶¶42-43.
`
`• This boundary between the FPGAs and the workstation
`(through the interface boards) clearly constitutes a
`“seam” within the context of the ’324 Patent and its file
`history.
`
`Source: Response, 97
`
`PODX - 60
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner and its expert agree with DirectStream that the claims of
`the ’324 Patent cannot be invalidated by any references that use
`memory or other structures to provide storage between two
`processing elements—such an implementation would fail to meet
`“seamless” limitation of the independent claims.
`EX2064 at 85:14-86:12:
`
`EX2064, 91:9-24:
`
`Source: Response, 97
`
`PODX - 61
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`•
`
`In accordance with the specification and the file history
`for the ’324 Patent, this would certainly include any
`structures that require data to leave the reconfigurable
`resources on a single chip for storage and then be read
`back into the chip by the next processing element.
`EX1002 at 117-118, 147-148, 174-175, 224-225.
`
`Source: Response, 97-98
`
`PODX - 62
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Splash2 is, at best, ambiguous on whether memory is used
`to store the results from each processing element after each
`time step to preserve it for output and later use.
`EX2111¶¶210-219. The Splash2 algorithms disclosed
`indicate storage is likely necessary to preserve the values
`calculated at each timestep and to store them for some
`number of additional timesteps. EX2111¶¶210-219.
`
`• Based on the disclosed algorithms, Splash2’s pseudocode
`will overwrite the computed data at each timestep.
`EX2111¶214. Without storage to preserve the computed data
`at each timestep, intermediate computed data will be lost and
`the only preserved “computed data” would be the one
`resulting from the final time step. EX2111¶214.
`
`Source: Response, 98
`
`PODX - 63
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`•
`
`In fact, Splash2 clearly discloses providing local memory at each
`FPGA for storage purposes. EX1007 at 95 (“Many Splash 2
`applications use the off-chip memory… which are often used as
`lookup tables or as storage for results to the host.”),
`
`• EX1007 at 102 (describing the use of one or two storage registers)
`
`• EX1035 at 1; EX2111¶¶210-219.
`
`Source: Response, 98
`
`PODX - 64
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Other literature about Splash2 confirms this local memory can be used
`for storage of results. EX2156 at 205-206; EX2111¶¶215-219.
`
`Source: Response, 98-99
`
`PODX - 65
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Splash2 also discloses using a register for communicating data
`between processing elements.
`
`• EX1007 at 88
`
`• The well-known solution at the time of the invention was to use
`memory storage to smooth out those timing problems, and Splash2
`touts its local memory attached to each FPGA as a major benefit for
`programmers. EX1007 at 13, 40; EX1035 at 1.
`
`Source: Response, 98-99
`
`PODX - 66
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• At best, Splash2 is still ambiguous whether or not it uses
`the available local memory to store results.
`
`• Here, it is equally (if not more) plausible for a POSITA to
`interpret Splash2 to use the local memory due to the
`known timing problems in systolic systems prior to the
`invention of the ’324 Patent. EX2111¶¶210-219.
`
`Source:
`
`PODX - 67
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Petitioner’s expert even admits that local memory must
`be used to store temporary
`results. EX2064 at 176:13-177:25; EX2111¶¶215.
`
`Source: Response, 99
`
`PODX - 68
`
`
`
`“pass computed data seamlessly between said computational
`loops”
`
`• Even under Petitioner’s own proposed construction,
`Splash2 still does not disclose “seamless” because it
`cannot show
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