INTEGRATED CIRCUITS
`
`SCC2691
`Universal asynchronous
`receiver/transmitter (UART)
`
`Product data sheet
`Supersedes data of 1998 Sep 04
`
`2006 Aug 04
`
`Philips
`Semiconductors
`
`PHILIPS
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Product data sheet
`
`Universal asynchronous receiver/transmitter (UART)
`
`SCC2691
`
`DESCRIPTION
`The Philips Semiconductors SCC2691 Universal Asynchronous
`Receiverrrransmitter (UART) is a single-chip CMOS-LSI
`communications device that provides a full-duplex asynchronous
`receiver/transmitter. It is fabricated with Philips Semiconductors
`CMOS technology which combines the benefits of high density and
`low power consumption.
`
`The operating speed of the receiver and transmitter can be selected
`independently as one of 18 fixed baud rates, a 16X clock derived
`from a programmable counter/timer, or an external 1X or 16X clock.
`The baud rate generator and counter/timer can operate directly from
`a crystal or from external clock inputs. The ability to independently
`program the operating speed of the receiver and transmitter make
`the UART particularly attractive for dual-speed channel applications
`such as clustered terminal systems.
`
`The receiver is quadruple buffered to minimize the potential of
`receiver overrun or to reduce interrupt overhead in interrupt driven
`systems. In addition, a handshaking capability is provided to disable
`a remote UART transmitter when the receiver buffer is full.
`
`The UART provides a power-down mode in which the oscillator is
`frozen but the register contents are stored. This results in reduced
`power consumption on the order of several magnitudes.
`
`The UART is fully TTL compatible and operates from a single +5V
`power supply.
`
`FEATURES
`• Full-duplex asynchronous receiver/transmitter
`
`• Quadruple buffered receiver data register
`
`• Programmable data format:
`- 5 to 8 data bits plus parity
`- Odd, even, no parity or force parity
`- 1, 1.5 or 2 stop bits programmable in 1 /16-bit increments
`
`• 16-bit programmable Counterffimer
`
`• Baud rate for the receiver and transmitter selectable from:
`- 22 fixed rates: 50 to 115.2K baud
`- Non-standard rates to 115.2 kb
`- Non-standard user-defined rate derived from programmable
`timer/ counter
`- External 1Xor 16Xclock
`
`• Parity, framing. and overrun detection
`
`• False start bit detection
`
`• Line break detection and generation
`
`• Programmable channel mode
`- Normal (full-duplex)
`- Automatic echo
`- Local loopback
`- Remote Loopback
`
`• Multi-function programmable 16-bit counter/timer
`
`PIN CONFIGURATIONS
`
`vee
`
`WRN
`
`DO
`
`D1
`
`D2
`
`D3
`
`D4
`
`D5
`
`D6
`
`D7
`
`CEN
`
`INTRN
`
`X2
`
`RESET
`
`GND
`
`A28
`PACKAGE
`
`Pin
`
`Symbol
`
`Pin
`
`Symbol
`
`;i;
`19
`LU
`)1
`22
`
`;4
`
`:17
`:)",
`0!:":
`C,d
`:)3
`
`c,;
`
`13
`'.4
`
`RE'?E'
`
`Si"X)0!.7;'
`
`Figure 1. Pin Configurations
`
`• Single interrupt output with seven maskable interrupting
`conditions
`
`• On-chip crystal oscillator
`
`• Low power mode
`
`• TTL compatible
`
`• Single +5V power supply
`
`• Commercial (0°C to +70°C) and industrial (-40°C to +85°C)
`temperature versions available
`
`• SOL, PLCC and 300 mil wide DIP packages available
`
`2006 Aug 04
`
`2
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`ORDERING INFORMATION
`
`PACKAGES
`
`24-Pin Plastic Dual In-Line Package (DIP)
`28-Pin Plastic Leaded Chip Carrier (PLCC) Package
`24-Pin Plastic Small Outline Large (SOL) Package
`
`BLOCK DIAGRAM
`
`COMMERCIAL
`Vee= +5V ±10%,
`TA= 0°c to +70°c
`SCC2691AC1 N24
`SCC2691 AC1 A28
`SCC2691AC1 D24
`
`INDUSTRIAL
`Vee= +5V ±10%,
`TA:::: -40°C to +85°C
`SCC2691AE1 N24
`SCC2691AE1A2S
`
`VERSION
`
`S0T222-1
`S0T261-2
`S0T137-1
`
`INTERNAL DATA
`BUS
`
`~
`
`I BUS BUFFER I
`
`/
`
`' ,.::_
`
`' ' v
`
`OPERATION CONTROL
`
`ADDRESS
`DECODE
`
`I
`I
`I R/WCONTROL I
`
`INTERRUPT CONTROL c; I
`
`•
`
`CONTROL
`
`,
`
`/
`
`"'
`r<-- ~
`
`'-.
`
`V
`
`< 8 I
`
`I
`'
`
`V
`
`•
`
`3 '
`'
`
`DO-D7
`
`RON
`
`WRN
`GEN
`AO-A2
`
`RESET
`
`INTRN
`
`X1/CLK
`
`X2
`
`TIMING
`
`TIMING
`
`BAUD RATE
`GENERATOR
`
`CLOCK
`SELECTORS
`
`I
`
`COUNTER/
`TIMER
`
`CRYSTAL
`OSCILLATOR
`
`POWER DOWN
`LOGIC
`
`I
`
`I
`
`I
`
`CSR
`ACR
`CTUR
`CTLR
`
`~
`
`/ '
`
`"'
`
`-
`
`~
`
`' v
`
`~
`
`Figure 2. Block Diagram
`
`2006 Aug 04
`
`3
`
`-
`'
`V
`
`-
`
`V
`
`-
`
`-
`
`V
`
`-
`
`CHANNEL A
`
`TRANSMIT
`HOLDING REG
`
`..
`
`T,D
`
`TRANSMIT
`SHIFT REGISTER
`
`RECEIVE
`HOLDING REG (3)
`
`RECEIVE
`SHIFT REGISTER
`
`MK
`
`2
`
`-R
`SR
`
`---------------------------------> R,D
`
`INPUT PIN
`
`CHANGE OF
`STATE
`DETECTOR
`
`..
`
`OUTPUT PIN
`
`FUNCTION
`SELECT LOGIC
`
`ACR
`
`I
`
`MPI
`
`MPO
`
`SOCGJ23
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`MNEMONIC
`
`PIN DESCRIPTION
`PIN NO.
`DIP
`PLCC
`22-15
`27. 25.
`24.
`22-18
`
`DO-D7
`
`CEN
`
`14
`
`17
`
`WRN
`
`23
`
`28
`
`RON
`
`1
`
`2
`
`AO-A2
`
`8-6
`
`11-9
`
`RESET
`
`11
`
`14
`
`INTRN
`
`13
`
`16
`
`X1/CLK
`
`9
`
`12
`
`X2
`
`RxD
`
`TxD
`
`MPO
`
`10
`
`13
`
`2
`
`3
`
`4
`
`3
`
`4
`
`5
`
`MPI
`
`5
`
`6
`
`I
`
`Vee
`GND
`
`24
`12
`
`1
`15
`
`I
`I
`
`2006 Aug 04
`
`4
`
`TYPE NAME AND FUNCTION
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`0
`
`I
`
`I
`
`I
`
`0
`
`0
`
`Data Bus: Active-high 8-bit bidirectional 3-State data bus. Bit O is the LSB and bit 7 is the
`MSB. All data, command, and status transfers between the CPU and the UART take place
`over this bus. The direction of the transfer is controlled by the WRN and RON inputs when
`the CEN input is low. When the CEN input is high, the data bus is in the 3-State condition.
`Chip Enable: Active-low input. When lrn1v. data transfers between the CPU and the UART
`are enabled on 00-07 as controlled by the WRN, RON and AO-A2 inputs. When CEN is
`high, the UART is effectively isolated from the data bus and 00-07 are placed in the 3-State
`condition.
`Write Strobe: Active-low input. A low on this pin while CEN is low causes the contents of
`the data bus to be transferred to the register selected by AO-A2. The transfer occurs on the
`trailing (rising) edge of the signal.
`Read Strobe: Active-low input. A low on this pin while CEN is low causes the contents of
`the register selected by AO-A2 to be placed on the data bus. The read cycle begins on the
`leading (falling) edge of RON.
`Address Inputs: Active-high address inputs to select the UART registers for read/write
`operations.
`Reset: Master reset. A high on this pin clears the status register (SR), the interrupt mask
`register (IMR). and the interrupt status register (ISR), sets the mode register pointer to MRI,
`and places the receiver and transmitter in the inactive state causing the TxD output to go to
`the marking (high) state. Clears Test modes.
`Interrupt Request: This active-low output is asserted upon occurrence of one or more of
`seven maskable interrupting conditions. The CPU can read the interrupt status register to
`determine the interrupting condition(s). This open-drain output requires a pull-up resistor.
`Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate
`frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see
`Figure 7, Clock Timing.
`Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin
`not connected although it is permissible to ground it.
`Receiver Serial Data Input: The least significant bit is received first. If external receiver
`clock is specified, this input is sampled on the rising edge of the clock.
`Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
`held in the marking {high) condition vvhen the transmitter is idle or disabled and when the
`UART is operating in local loopback mode. If external transmitter is specified, the data is
`shifted on the falling edge of the transmitter clock.
`Multi-Purpose Output: One of the follo\tving functions can be selected for this output pin by
`programming the auxiliary control register:
`RTSN - Request to send active-low output. This output is asserted and negated via the
`command register. By appropriate programming of the mode registers. RTSN can be pro-
`grammed to be automatically reset after the character in the transmitter is completely shifted
`or when the receiver FIFO and shift register are full.
`CITO - The counter/l:imer output.
`TxC1 X - The 1 X clock for the transmitter.
`TxC16X - The 16X clock for the transmitter.
`RxC1 X - The 1 X clock for the receiver.
`RxC16X - The 16X clock for the receiver.
`TxRDY -The transmitter holding register empty signal. Active-law output. (Open drain)
`RxRDY/FFULL - The receiver FIFO not empty/full signal. Active-low output. (Open drain)
`MultiaPurpose Input: This pin can serve as an input for one of the following functions:
`GPI - General purpose input. The current state of the pin can be determined by reading the
`ISR.
`CTSN - Clear-to-send active-low input.
`CTCLK - Counter/l:imer external clock input.
`RTCLK - Receiver and/or transmitter external clock input. This may be a 1 X or 1 GX clock as
`programmed by CSR[3 OJ or CSR[7:4].
`Pin has an internal Vee pull-up device supplying 1 to 4 J.A of current.
`Power Supply: +5V supply input.
`Ground
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`PARAMETER
`Operating ambient temperature range2
`
`ABSOLUTE MAXIMUM RATINGS1
`SYMBOL
`TA
`TsrG
`Vee
`Vs
`Po
`
`Storage temperature range
`Voltage from Vee to GND3
`Voltage from any pin to ground3
`
`Power Dissipation
`
`RATING
`Note 4
`-65 to +150
`-0.5 to+ 7.0
`
`-0.5 to Vee±.10%
`300
`
`UNIT
`C
`oc
`V
`V
`mW
`
`NOTES:
`1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
`functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
`implied.
`2. For operating at elevated temperature, the device must be derated based on +150'C maximum junction temperature.
`3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
`charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
`4. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and Vee supply
`range.
`DC ELECTRICAL CHARACTERISTICS1, 2, 3
`
`SYMBOL
`
`PARAMETER
`
`TEST CONDITIONS
`
`LIMITS
`Typ
`
`Min
`
`leeo
`NOTES:
`1. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and Vee supply
`range.
`2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between OV and 3.0V with a transition time of
`20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
`output voltages of 0.8V and 2V as appropriate.
`3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
`4. Test condition for outputs: CL= 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL= 50pF, RL = 2.7kn to Vee-
`5. For power down current levels in the 1µA region see the UART application note.
`
`2006 Aug 04
`
`5
`
`VIL
`V1H
`
`Voe
`VoH4
`
`'"
`,,,
`
`loo
`
`lx1L
`lx1H
`
`lx2L
`
`lx2H
`
`leeA
`
`Input low voltage
`Input high voltage
`
`All except X1/CLK
`X1/CLK
`
`Output low voltage
`Output high voltage
`(except open drain outputs)
`
`Input leakage current
`Data bus 3-State leakage current
`
`Open-drain output leakage current
`
`Xi/CLK low input current
`X1 /CLK high input current
`
`X2 low output current
`
`X2 high output current
`
`Power supply current, active
`
`Power down current5
`
`loL = 2.4mA
`
`loH = -400µA
`
`V1N =Oto Vee
`Vo= 0.4 to Vee
`
`Vo= 0.4 to Vee
`V1N = 0, X2 floated
`
`V1N = Vee. X2 floated
`
`Vour = 0. XI/CLK = Vee
`Vour = Vee, X1/CLK = ov
`0°C to +70°C
`-4o·=c to +85°C
`
`2
`0.8Vce
`
`2.4
`-10
`-10
`-10
`-100
`0
`-100
`
`-30
`30
`
`0.8
`1.0
`
`Max
`
`0.8
`
`Vee
`0.4
`
`10
`10
`10
`0
`100
`
`UNIT
`
`V
`
`V
`V
`
`V
`
`V
`
`µA
`µA
`µA
`µA
`µA
`µA
`
`100
`2.0
`2.5
`500
`
`µA
`mA
`mA
`µA
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
`
`SYMBOL
`
`PARAMETER
`
`Reset timing (Figure 3)
`
`Reset pulse width
`tRES
`Bus timing (Figure 4) 0
`AO-A2 setup time to RON, WRN low
`!As
`AO-A2 hold time from RON. WRN low
`!AH
`CEN setup time to RON, WRN low
`!cs
`CEN hold time from RON, WRN high
`!cH
`WRN, RON pulse width
`!Rw
`Data valid after RON low
`loo
`Data bus floating after RON high
`!oF
`Data setup time before WRN high
`los
`Data hold time after WRN high
`!oH
`Time between reads and/or writes6, 7
`tR\ND
`MPI and MPO timing (Figure 5)5
`
`MPI input setup time before RON low
`!ps
`Ml input hold time after RON low
`!pH
`MPO output valid after WRN high
`!po
`Interrupt timing (Figure 6)
`
`!1R
`
`INTRN negated
`Read RHR (RxROY/FFULL interrupt)
`Write THR (TxRDY, TxEMT interrupt)
`Reset command (break change interrupt)
`Reset command (MPI change interrupt)
`Stop CIT command (counter interrupt)
`Write IMR (clear of interrupt mask bit)
`Clock timing (Figure 7)
`
`tcLK
`fcLK9
`tcrc
`fcrc8
`!RX
`fRX 8
`
`Xi/CLK high or low time
`X1/CLK frequency
`Counter/timer clock high or lrn1v time
`Counter/timer clock frequency
`RxC high or low time
`RxC frequency (16X)
`RxC frequency (1X)
`TxC high or low time
`TxC frequency {16X)
`TxC frequency (IX)
`Transmitter timing (Figure 8)
`
`lrx
`
`frxs
`
`TxO output delay from TxC external clock input on IP pin
`trxo
`Output delay from TxC low at OP pin to TxD data output
`tres
`Receiver timing (Figure 9)
`
`Min
`
`LIMITS
`Typ
`
`Max
`
`UNIT
`
`I
`
`100
`
`I
`
`I
`
`I
`
`10
`100
`0
`0
`150
`
`50
`30
`150
`
`30
`30
`
`100
`0
`100
`0
`220
`0
`0
`220
`0
`0
`
`0
`
`125
`110
`
`370
`
`370
`370
`370
`370
`370
`270
`
`4.0
`
`4.0
`
`2.0
`1.0
`
`2.0
`1.0
`
`350
`150
`
`3.6864
`
`ns
`
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`
`ns
`ns
`ns
`
`ns
`ns
`ns
`ns
`ns
`ns
`
`ns
`MHz
`ns
`MHz
`ns
`MHz
`MHz
`ns
`MHz
`MHz
`
`ns
`ns
`
`RxO data setup time before RxC high at external clock input on IP pin
`RxO data hold time after RxC high at external clock input on IP pin
`
`100
`100
`
`ns
`ns
`
`tRxs
`IRXH
`NOTES:
`1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and Vee supply range.
`2. All voltage measurements are referenced to ground (GNO). For testing, all input signals swing between OV and 3.0V with a transition time of
`20ns max. For X1/CLK. this swing is behveen 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
`output voltages of 0.8V and 2V as appropriate.
`3. Typical values are at +25'-'C, typical supply voltages, and typical processing parameters.
`4. Test condition for outputs: CL= 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL= 50pF, RL = 2.?k.Q. to Vee.
`5. Timing is illustrated and referenced to the WRN and RON inputs. The device may also be operated with CEN as the ·strobing' input. In this
`case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RON (also CEN and WRN) are ORed inter(cid:173)
`nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
`If CEN is used as the 'strobing' input, this parameter defines the minimum high time between one CEN and the next. The RON signal must
`be negated for tRwD guarantee that any status register changes are valid.
`7. Consecutive write operations to the command register require at least three rising edges of the Xi clock between writes.
`8. These parameters are guaranteed by design, but are not 100%) tested in production.
`9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
`
`6.
`
`2006 Aug 04
`
`6
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`BLOCK DIAGRAM
`ft.s shown in the block diagram, the UART consists of: data bus buffer,
`interrupt control, operation control, timing, receiver and transmitter.
`
`Data Bus Buffer
`The data bus buffer provides the interface between the external and
`internal data busses. It is controlled by the operation control block to
`allow read and write operations to take place between the controlling
`CPU and UART
`
`Interrupt Control
`A single interrupt output (INTRN) is provided which may be asserted
`upon occurrence of any of the following internal events:
`- Transmit holding register ready
`- Transmit shift register empty
`- Receive holding register ready or FIFO full
`- Change in break received status
`- Counter reached terminal count
`- Change in MPI input
`- Assertion of MPI input
`
`Associated with the interrupt system are the interrupt mask register
`(IMR) and the interrupt status register (ISR). The IMR can be
`programmed to select only certain of the above conditions to cause
`INTRN to be asserted. The ISR can be read by the CPU to
`determine all currently active interrupting conditions. However. the
`bits of the ISR are not masked by the IMR.
`
`Operation Control
`The operation control logic receives operation commands from the
`CPU and generates appropriate signals to internal sections to
`control device operation. It contains address decoding and read and
`write circuits to permit communications with the microprocessor via
`the data bus buffer. The functions performed by the CPU read and
`write operations are shown in Table 1.
`
`SCC2692, SCC6868'1 and SCC26988" Philips Semiconductors ICs
`for Data Communications, IC-19. 1994.
`
`Mode registers 1 and 2 are accessed via an auxiliary pointer. The
`pointer is set to MR1 by RESET or by issuing a reset pointer
`command via the command register. Any read or write of the mode
`register while the pointer is at MR1 switches the pointer to MR2. the
`pointer then remains at MR2 so that subsequent accesses are to
`MR2. unless the pointer is reset to MR1 as described above.
`
`Timing Circuits
`The timing block consists of a crystal oscillator, a baud rate
`generator, a programmable 16-bit counter/timer, and two clock
`selectors.
`
`The crystal oscillator operates directly from a 3.6864MHz crystal
`connected across the XI/ CLK and X2 inputs with a minimum of
`external components. lfan external clock of the appropriate
`frequency is available, it may be connected to X1/CLK. If an external
`clock is used instead of a crystal, X1/CLK is driven using a
`configuration similar to the one in Figure 7. In this case. the input
`high-voltage must be capable of attaining the voltage specified in the
`DC Electrical Characteristics. The clock serves as the basic timing
`reference for the baud rate generator (BRG), the counter/timer, and
`other internal circuits. A clock frequency, within the limits specified in
`the electrical specifications, must be supplied if the internal BRG is
`not used.
`
`The baud rate generator operates from the oscillator or external
`clock input and is capable of generating 18 commonly used data
`communications baud rates ranging from 50 to 38.4K baud. Thirteen
`of these are available simultaneously for use by the receiver and
`transmitter. Eight are fixed, and one of two sets of five can be
`selected by programming ACR[7]. The clock outputs from the BRG
`are at 16X the actual baud rate. The counter/timer can be used as a
`timer to produce a 16X clock for any other baud rate by counting
`down the crystal clock or an external clock. The clock selectors
`allow the independent selection by the receiver and transmitter of
`any of these baud rates or an external timing signal.
`
`Counter/Timer (CIT)
`The CIT operation is programmed by ACR[6:4]. One of eight timing
`sources can be used as the input to the CIT. The output of the CIT is
`available to the clock selectors and can be programmed by
`ACR[2:0} to be output on the MPO pin.
`
`In the timer mode, the CIT generates a square wave whose period is
`twice the number of clock periods loaded into the CIT upper and
`lower registers. The counter ready bit in the ISR is set once each
`cycle of the square wave. If the value in CTUR or CTLR is changed.
`the current half-period will not be affected, but subsequent
`half-periods will be affected. In this mode the CIT runs continuously
`and does not recognize the stop counter command (the command
`only resets the counter ready bit in the ISR). Receipt of a start CIT
`command causes the counter to terminate the current timing cycle
`and to begin a new cycle using the values in CTUR and CTLR.
`
`In the counter mode, the C/T counts down the number of pulses
`loaded into CTUR and CTLR. Counting begins upon receipt of a
`start CIT command. Upon reaching terminal count, the counter
`ready bit in the ISR is set. The counter continues counting past the
`terminal count until stopped by the CPU. If MPO is programmed to
`be the output of the CIT, the output remains high until terminal count
`is reached. at which time it goes low. The output returns to the high
`state and the counter ready bit is cleared when the counter is
`stopped by a stop counter command. the CPU may change the
`
`WRITE
`(WRN = 0)
`MR1, MR2
`CSR
`CR
`THR
`ACR
`IMR
`CTUR
`CTLR
`
`Table 1. Register Addressing
`READ
`(RDN = 0)
`MR1, MR2
`SR
`BRG Test
`RHR
`1X/16X Test
`ISR
`CTU
`CTL
`
`AO
`0
`1
`0
`1
`0
`1
`0
`1
`
`A1
`0
`0
`1
`1
`0
`0
`1
`1
`
`A2
`0
`0
`0
`0
`1
`1
`1
`1
`NOTE;
`*Reserved registers should never be read during operation since
`they are reserved for internal diagnostics.
`ACR = Auxiliary control register
`CR= Command register
`CSR = Clock select register
`CTL = Counter/timer lower output register
`CTLR = Counter/timer lower preset register
`CTU = Counter/timer upper output register
`CTUR = Counter/timer upper preset register
`MR = Mode register A
`SR = Status register
`THR = Tx holding register
`* See Table 6 for BRG Test frequencies in this data sheet, and
`"Extended baud rates for SCN268·1, SCN68681, SCC2691,
`
`2006 Aug 04
`
`7
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`values of CTUR and CTLR at any time, but the new count becomes
`effective only on the next start counter command following a stop
`counter command. If new values have not been loaded, the previous
`count values are preserved and used for the next count cycle.
`
`In the counter mode, the current value of the upper and lrn,ver eight
`bits of the counter may be read by the CPU. It is recommended that
`the counter be stopped when reading to prevent potential problems
`which may occur if a carry from the lrn,ver eight bits to the upper
`eight bits occurs between the times that both halves of the counter
`are read. However. a subsequent start counter command causes
`the counter to begin a new count cycle using the values in CTUR
`and CTLR. See further description in CTUR/CTLR section.
`Receiver and Transmitter
`The UART is a full-duplex asynchronous receiver/transmitter. The
`operating frequency for the receiver and transmitter can be selected
`independently from the baud rate generator, the counter/timer, or
`from an external input. Registers associated with the
`communications channel are: the mode registers (MR1 and MR2),
`the clock select register (CSR), the command register (CR), the
`status register {SR), the transmit holding register (THR). and the
`receive holding register {RHR).
`
`Transmitter
`The transmitter accepts parallel data from the CPU and converts it
`to a serial bit stream on the TxD output pin. It automatically sends a
`start bit followed by the programmed number of data bits, an
`optional parity bit. and the programmed number of stop bits. The
`least significant bit is sent first. Following the transmission of the
`stop bits, if a new character is not available in the THR, the TxD
`output remains high and the TxEMT bit in the SR will be set to 1.
`Transmission resumes and the TxEMT bit is cleared when the CPU
`loads a new character in the THR. In the 16Xclock mode, this also
`resynchronizes the internal iX transmitter clock so that transmission
`of the new character begins with minimum delay.
`
`The transmitter can be forced to send a break (continuous low
`condition) by issuing a start break command via the CR. The break
`is terminated by a stop break command.
`
`If the transmitter is disabled, it continues operating until the
`character currently being transmitted and the character in the THR,
`if any, are completely sent out. Characters cannot be loaded in the
`THR while the transmitter is disabled.
`
`Receiver
`The receiver accepts serial data on the RxD pin. converts the serial
`input to parallel format, checks for start bit, stop bit, parity bit {if any).
`or break condition, and presents the assembled character to the
`CPU. The receiver looks for a high-to-low {mark-to-space) transition
`of the start bit on the RxD input pin. lfa transition is detected, the
`state of the RxD pin is sampled again each 16X clock for 7-1/2
`clocks (16X clock mode) or at the next rising edge of the bit time
`clock (1X clock mode). If RxD is sampled high, the start bit is invalid
`and the search for a valid start bit begins again. If RxD is still low, a
`valid start bit is assumed and the receiver continues to sample the
`input at one bit time intervals at the theoretical center of the bit, until
`the proper number of data bits and the parity bit (if any) have been
`assembled, and one sop bit has been detected. The data is then
`transferred to the RHR and the RxRDY bit in the SR is set to a 1. If
`the character length is less than eight bits, the most significant
`unused bits in the RHR are set to zero.
`
`After the stop bit is detected, the receiver will immediately look for
`the next start bit. However, if a non-zero character was received
`without a stop bit (i.e. framing error) and RxD remains low for
`
`2006 Aug 04
`
`8
`
`one-half of the bit period after the stop bit was sampled, then the
`receiver operates as if a new start bit transition had been detected at
`that point(one-half bit time after the stop bit was sampled).
`
`The parity error. framing error and overrun error (if any) are strobed
`into the SR at the received character boundary before the RxRDY
`status bit is set.
`
`If a break condition is detected {RxD is low for the entire character
`including the stop bit), only one character consisting of all zeros will
`be loaded in the FIFO and the received SR break bit is set to 1. The
`RxD input must return to high for two (2) clock edges of the XI
`crystal clock for the receiver to recognize the end of the break
`condition and begin the search for a start bit. This vvm usually
`require a high time of one X1 clock period or 3 X1 edges since
`the clock of the controller is not synchronous to the X1 clock.
`
`RECEIVER FIFO
`The RHR consists of a first-in-first-out (FIFO) queue with a capacity
`of three characters. Data is loaded from the receive shift register
`into the top-most empty position of the FIFO. The RxRDY bit in the
`status register (SR) is set whenever one or more characters are
`available to be read, and a FFULL status bit is set if all three queue
`positions are filled with data. Either of these bits can be selected to
`cause an interrupt. A read of the RHR outputs the data at the top of
`the FIFO. After the read cycle, the data FIFO and its associated
`status bits are 'popped' thus emptying a FIFO position for new data.
`
`Receiver Status Bits
`In addition to the data word. three status bits (parity error. framing
`error, and received break) are appended to each data character in
`the FIFO. Status can be provided in tvvo ways. as programmed by
`the error mode control bit in mode register 1. In the character mode,
`status is provided on a character-by-character basis: the status
`applies only to the character at the top of the FIFO. In the block
`mode, the status provided in the SR for these three bits is the
`logical-OR of the status for all characters coming to the top of the
`FIFO since the last reset error command was issued. In either
`mode, reading the SR does not affect the FIFO. The FIFO is
`'popped' only when the RHR is read. Therefore, the SR should be
`read prior to reading the corresponding data character.
`
`The receiver can control the deactivation of RTS. If programmed to
`operate in this mode, the RTSN output will be negated when a valid
`start bit was received and the FIFO is full. When a FIFO position
`becomes available, the RTSN output will be re-asserted
`automatically. This feature can be used to prevent an overrun, in
`the receiver, by connecting the RTSN output to the CTSN input of
`the transmitting device.
`
`Receiver Reset and Disable
`Receiver disable stops the receiver immediately- data being
`assembled if the receiver shift register is lost. Data and status in the
`FIFO is preserved and may be read. A re-enable of the receiver
`after a disable will cause the receiver to begin assembling
`characters at the next start bit detected. A receiver reset will discard
`the present shift register data, reset the receiver ready bit (RxRDY),
`clear the status of the byte at the top of the FIFO and re-align the
`FIFO read/write pointers. This has the appearance of "clearing or
`flushing·· the receiver FIFO. In fact, the FIFO is NEVER cleared!
`The data in the FIFO remains valid until overwritten by another
`received character. Because of this, erroneous reading or extra
`reads of the receiver FIFO will miss-align the FIFO pointers and
`result in the reading of previously read data. A receiver reset will
`re-align the pointers.
`
`CISCO 1043
`Cisco v. ChriMar
`
`

`

`Philips Semiconductors
`
`Universal asynchronous receiver/transmitter (UART)
`
`Product data sheet
`
`SCC2691
`
`In addition to the normal transmitter and receiver operation
`described above, the UART incorporates a special mode which
`provides automatic wake-up of the receiver through address frame
`recognition for multi-processor communications. This mode is
`selected by programming bits MR1[4:3] to '11 ".
`
`In this mode of operation. a 'master' station transmits an address
`character followed by data characters for the addressed ·slave'
`station. The slave stations, whose receivers are normally disabled.
`examine the received data stream and 'wake-up' the CPU [by
`setting RxRDY) only upon receipt of an address character. The CPU
`compares the received address to its station address and enables
`the receiver if it wishes to receive the subsequent data characters.
`Upon receipt of another address character, the CPU may disable the
`receiver to initiate the process again.
`
`A transmitted character consists of a start bit. the programmed
`number of data bits, an address/data (JVD) bit. and the programmed
`number of stop bits. The polarity of the transmitted AID bit is
`selected by the CPU by programming bit MR1[2]. MR1[2] = O
`transmits a zero in the JVD bit position which identifies the
`corresponding data bits as data, while MR1 [2] = 1 transmits a one in
`the AID bit position which identifies the corresponding data bits as
`an address. The CPU should program the mode register prior to
`loading the corresponding data bits in the THR.
`
`While in this mode, the receiver continuously looks at the received
`data stream, whether it is enabled or disabled. If disabled, it sets the
`RxRDY status bit and loads the character in the RHR FIFO if the
`received AID bit is a one, but discards the received character if the
`received AID bit is a zero. If enabled, all received characters are
`then transferred to the CPU via the RHR. In either case, the data
`bits are loaded in the data FIFO while the AID bit is loaded in the
`status FIFO position normally used for parity error (SR[5]). Framing
`error. overrun error, and break detect operate normally whether or
`not the receiver is enabled.
`MULTI-PURPOSE INPUT PIN
`The MPI pin can be programmed as an input to one of several
`UART circuits. The function of the pin is selected by programming
`the appropriate control register (MR2[4]), ACR[64], CSR [74, 3:01).
`Only one of the functions may be selected at any given time. If CTS
`or GPI is selected, a change of state detector provided \rVith the pin
`is activated. A high-to-low or low-to-high transition of the inputs
`lasting longer than 25-50µs sets the MPI change-of-state bit in the
`interrupt status register. The bit is cleared via a command. The
`change-of-state can be programmed to generate an interrupt to the
`CPU by setting the corresponding bit in th