Petitioner Bluehouse Global Ltd.
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1004
`
`EX. 1004
`
`

`

`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2011/0109351A1
`YAMAZAKI et al.
`(43) Pub. Date:
`May 12, 2011
`
`US 2011 0109351A1
`
`(54) SEMICONDUCTOR DEVICE AND
`MANUFACTURING METHOD THEREOF
`
`(75) Inventors:
`
`Shunpei YAMAZAKI. Setagaya
`(JP); Jun KOYAMA, Sagamihara
`s: Hiroyuki MIYAKE, Atsugi
`
`(73) Assignee:
`
`SEMCONDUCTOR ENERGY
`LABORATORY CO.,LTD.,
`Atsugi (JP)
`
`(21) Appl. No.:
`
`12/938,533
`
`(22) Filed:
`
`Nov. 3, 2010
`
`(30)
`
`Foreign Application Priority Data
`
`Nov. 6, 2009 (JP) ................................. 2009-255.535
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`HO3K 3/00
`(2006.01)
`HOIL 29/786
`(52) ("no 2. 's 10 257/E29.296
`257/E21476
`
`ABSTRACT
`(57)
`An oxide semiconductor layer which is intrinsic or Substan
`tially intrinsic and includes a crystalline region in a Surface
`portion of the oxide semiconductor layer is used for the tran
`sistors. An intrinsic or Substantially intrinsic semiconductor
`from which an impurity which is to be an electron donor
`(donor) is removed from an oxide semiconductor and which
`has a larger energy gap than a silicon semiconductor is used.
`Electrical characteristics of the transistors can be controlled
`by controlling the potential of a pair of conductive films
`which are provided on opposite sides from each other with
`respect to the oxide semiconductor layer, each with an insu
`lating film arranged therebetween, so that the position of a
`channel formed in the oxide semiconductor layer is deter
`mined.
`
`
`
`
`
`
`
`
`
`A
`M 2 2 2
`
`
`N N 22
`AS NK
`
`
`
`440A
`
`440B
`
`BLUEHOUSE EXHIBIT 1004
`Page 2 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 1 of 27
`
`US 2011/O109351A1
`
`NYYYYYY
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`SN N
`SNSNS N
`
`WYYYYYYYYYYYYYYYYY
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`
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`
`
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`SNNN N
`
`SNS NSN M W
`NSN N QNSN
`N
`
`
`
`
`
`440A
`
`440B
`
`BLUEHOUSE EXHIBIT 1004
`Page 3 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 2 of 27
`
`US 2011/O109351A1
`
`FIG. 2
`
`
`
`
`
`
`
`2. 2 2
`
`404C 405C
`
`a
`
`-
`
`-
`
`-
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`
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`
`H H H H H H H H H H H H H H - - - - - - - - - -
`
`.
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`eese
`.
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`.
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`.
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`.
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`.
`
`.
`
`400 440A
`
`421
`
`450
`
`BLUEHOUSE EXHIBIT 1004
`Page 4 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 3 of 27
`
`US 2011/O109351A1
`
`FIG. 3A
`
`440A
`
`
`
`
`
`440B
`422b. 455d
`455C
`455a 422a 455b 428
`A.
`410a: (4%
`i
`i E7
`7(SVZS
`NNN &zz, NQ As
`A
`M
`2
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`N Salaa aa Saa a SaaS N N NNS
`ayaya.N Aaaay an a.
`NNN
`NN
`exerxesexes
`
`2
`
`400 421 a 404a 405a 402 41 Ob 408 421b 404b. 405b
`
`FIG. 3B
`
`
`
`WDH
`
`FIG. 3C
`
`
`
`
`
`
`
`
`
`
`
`OUTPUT
`
`440A
`
`2%: É 2.
`N N SN3 2
`N
`3. 3 Ns 2
`steeae 3
`as a S. 2
`S
`
`
`
`
`
`
`
`
`
`
`
`INPUT
`
`
`
`422b
`
`421 a 410c
`
`WDL
`
`BLUEHOUSE EXHIBIT 1004
`Page 5 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 4 of 27
`
`US 2011/O109351A1
`
`FIG. 4A
`11 12 13 14
`
`8% 6RSHHHHHH
`to took to to
`
`
`
`OUT (1) OUT (2) OUT (3) OUT (4) OUT (5)
`
`OUT (N-1) OUT (N)
`
`FIG. 4B
`
`22
`21 ( 23
`
`24
`
`26
`
`27 d 25
`
`
`
`BLUEHOUSE EXHIBIT 1004
`Page 6 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 5 of 27
`
`US 2011/O109351A1
`
`OUT (3)
`WCC
`CK
`
`
`
`
`
`OUT (1)
`(SR)
`
`OUT (1)
`
`Ouro)
`OUT(3)
`
`|| ||
`Jil
`
`
`
`--
`
`BLUEHOUSE EXHIBIT 1004
`Page 7 of 61
`
`

`

`Patent Application Publication
`
`May 12, 2011 Sheet 6 of 27
`
`US 2011/O109351A1
`
`
`
`BLUEHOUSE EXHIBIT 1004
`Page 8 of 61
`
`

`

`Patent Application Publication
`
`May 12, 2011 Sheet 7 of 27
`
`US 2011/O109351A1
`
`
`
`BLUEHOUSE EXHIBIT 1004
`Page 9 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 8 of 27
`
`US 2011/O109351A1
`
`FIG. 8A
`
`OUT (1) VDD
`OUT (2)
`OUT (3)
`
`OUT (1) VDD
`OUT (2)
`OUT (3)
`
`?
`
`?
`
`BLUEHOUSE EXHIBIT 1004
`Page 10 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 9 of 27
`
`US 2011/O109351A1
`
`
`
`BLUEHOUSE EXHIBIT 1004
`Page 11 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 10 of 27
`
`US 2011/O109351A1
`
`FIG. 1 OA
`
`
`
`5603 1 5603 2 5603 k
`
`FIG. 1 OB
`
`-
`one gate selection period
`Sout 1 -
`I
`- -
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`Sout. 2 — – —
`Wdata 1
`...
`i.
`i.
`Wdata_2
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`I
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`SOut N —- . . . . . . .
`
`Data (SK)
`
`Data (SKK)
`Data (Sk+k)
`
`T3 TN-1
`
`BLUEHOUSE EXHIBIT 1004
`Page 12 of 61
`
`

`

`Patent Application Publication
`
`May 12, 2011 Sheet 11 of 27
`
`US 2011/O109351A1
`
`
`
`| |ZOV OZOV 0807 Z80?
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`
`BLUEHOUSE EXHIBIT 1004
`Page 13 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 12 of 27
`
`US 2011/O109351A1
`
`FIG. 12
`2606
`20,
`
`Z 27 27 27 27 27 2.
`
`2601 2605 2604 2603
`A
`
`2602
`A
`
`
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`
`27 27 27 27W 27 27 27 27 27 27 27 27 2 2 2
`
`
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`
`NYYYNNY YYYYNNYNY YYYNNY YNY YNN NYNNY YNNY YNNY
`
`2 1
`
`aaaaa. a
`
`BLUEHOUSE EXHIBIT 1004
`Page 14 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 13 of 27
`
`US 2011/O109351A1
`
`FIG. 13
`
`587 590b990a
`
`594 595 589
`
`588
`
`CZ& SA
`8.
`
`
`
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`r
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`SN)
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`RN
`
`581
`
`583
`
`BLUEHOUSE EXHIBIT 1004
`Page 15 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 14 of 27
`
`US 2011/O109351A1
`
`FIG. 14
`
`
`
`6406
`
`6401
`
`BLUEHOUSE EXHIBIT 1004
`Page 16 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 15 of 27
`
`US 2011/O109351A1
`
`7012
`
`7019
`
`7016 7015
`
`Prasars
`
`7035
`
`YZZYZZYZZYZZYYY 24& 2 Z42
`
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`al
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`9024
`FIG. 15B
`: ; / 7023
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`
`BLUEHOUSE EXHIBIT 1004
`Page 17 of 61
`
`

`

`Patent Application Publication
`
`May 12, 2011 Sheet 16 of 27
`
`
`
`
`
`US 2011/O109351A1
`
`
`
`©-------------- -----------------------------------------------------------------O
`
`|H
`
`BLUEHOUSE EXHIBIT 1004
`Page 18 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 17 of 27
`
`US 2011/O109351A1
`
`FIG. 17A
`
`
`
`FIG. 17B
`
`
`
`Y
`
`%
`
`2Z)
`1 OADxOAOx
`K.
`2.
`Ul
`%
`23
`%
`al
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`%
`3-2631
`3. S7 Sr.
`X
`35 DZA. H ROOAXOAX
`2
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`TE. : OOO-AAA-XXXX
`42.2%ZZZZZZZZZZZZZZZZZZZZZZZ2 W.
`
`OOADOO
`
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`
`CO's iOOi A
`
`BLUEHOUSE EXHIBIT 1004
`Page 19 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 18 of 27
`
`US 2011/O109351A1
`
`FIG. 18
`
`2707
`
`2703
`
`
`
`2705
`
`2701
`
`BLUEHOUSE EXHIBIT 1004
`Page 20 of 61
`
`

`

`Patent Application Publication
`
`May 12, 2011 Sheet 19 of 27
`
`US 2011/O109351A1
`
`FIG. 19A
`
`
`
`9601
`
`96.03
`
`
`
`ZZZZ7 Z2
`22 2
`Geist: 22%
`
`12
`
`Z2
`
`as
`
`a
`
`Z2
`Z212
`
`96.05
`
`FIG. 19B
`
`
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`
`
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`
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`
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`
`% 2 % s 3
`
`%% 2 Z Z2
`
`
`
`
`
`S
`s
`s
`
`BLUEHOUSE EXHIBIT 1004
`Page 21 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 20 of 27
`
`US 2011/O109351A1
`
`FIG. 20A
`
`FIG. 20B
`
`
`
`98.91
`
`BLUEHOUSE EXHIBIT 1004
`Page 22 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 21 of 27
`
`US 2011/O109351A1
`
`FIG 21A
`
`1003
`
`1001
`
`1006
`
`1004
`
`FIG 21B
`
`
`
`BLUEHOUSE EXHIBIT 1004
`Page 23 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 22 of 27
`
`US 2011/O109351A1
`
`FIG. 22A1
`
`FIG. 22A2
`
`2N
`
`2
`
`s
`2 % 2 % 2
`%
`
`2
`
`% %
`% %
`
`.
`% 2
`2 22
`% % 2
`
`2
`
`3
`2 2
`
`428 415 412
`
`22% 222
`22 2
`2
`
`
`
`NSNs eSa
`
`seeeeeeeeeeeeeeeeeeeeeeeeeeeee
`222s22s22sesseeses
`
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`
`C1
`
`402 411
`
`400
`
`FIG. 22B1
`
`FIG. 22B2
`
`
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`N V
`
`
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`% %
`
`e
`2
`2 2
`
`418
`
`%
`
`2 3
`
`400
`
`2
`
`BLUEHOUSE EXHIBIT 1004
`Page 24 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 23 of 27
`
`US 2011/O109351A1
`
`FIG. 23
`
`
`
`
`
`NNS
`
`BLUEHOUSE EXHIBIT 1004
`Page 25 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 24 of 27
`
`US 2011/O109351A1
`
`FIG. 24A
`
`
`
`FIG. 24B
`
`D
`
`BLUEHOUSE EXHIBIT 1004
`Page 26 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 25 of 27
`
`US 2011/O109351A1
`
`FIG. 25
`
`OS
`
`G
`
`Effi,
`
`(=GND)
`
`7TTI)
`
`BLUEHOUSE EXHIBIT 1004
`Page 27 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 26 of 27
`
`US 2011/O109351A1
`
`FIG. 26A
`
`EIII--------|--
`
`GE2
`
`(=GND)
`
`FIG. 26B
`
`
`
`G
`
`GE2
`
`f o
`
`minority carrier
`S Zer O
`
`BLUEHOUSE EXHIBIT 1004
`Page 28 of 61
`
`

`

`Patent Application Publication May 12, 2011 Sheet 27 of 27
`
`US 2011/O109351A1
`
`FIG. 27
`
`
`
`vacuum level
`
`EE T IT
`
`- E
`-----------e.
`
`EV
`
`BLUEHOUSE EXHIBIT 1004
`Page 29 of 61
`
`

`

`US 2011/O 109351 A1
`
`May 12, 2011
`
`SEMCONDUCTORDEVICE AND
`MANUFACTURING METHOD THEREOF
`
`TECHNICAL FIELD
`0001. The present invention relates to a semiconductor
`device including a transistor.
`0002. Note that the semiconductor device in this specifi
`cation refers to any device that can function by utilizing
`semiconductor characteristics, and semiconductor elements
`and circuits, electro-optic devices including semiconductor
`elements and circuits, and electronic devices including semi
`conductor elements and circuits are all semiconductor
`devices.
`
`BACKGROUND ART
`0003. In recent years, a technique by which transistors are
`formed using semiconductor thin films formed over a Sub
`strate having an insulating Surface has been attracting atten
`tion. A transistor is used for a semiconductor device typified
`by a liquid crystal television. As a semiconductor thin film
`that can be applied to the transistors, a silicon-based semi
`conductor material is known, and an oxide semiconductor
`attracts attention as another material.
`0004. A transistor is manufactured mainly using a semi
`conductor material Such as amorphous silicon or polycrystal
`line silicon. A transistor formed using amorphous silicon has
`low field-effect mobility, but such a transistor can be formed
`over a glass Substrate with a larger area. On the other hand, a
`transistor formed using crystalline silicon has high field
`effect mobility, but a crystallization step Such as laser anneal
`ing is necessary and Such a transistoris not always Suitable for
`a larger glass Substrate.
`0005. As a material of the oxide semiconductor, zinc oxide
`and a material containing Zinc oxide as its component are
`known. Further, thin film transistors formed using an amor
`phous oxide (oxide semiconductor) having an electron carrier
`concentration of less than 10"/cm are disclosed (Patent
`Documents 1 to 3).
`0006 Moreover, there is a trend in an active matrix semi
`conductor device typified by a liquid crystal display device
`towards a larger Screen, e.g., a 60-inch diagonal screen, and
`further, the development of an active matrix semiconductor
`device is aimed even at a screen size of a diagonal of 120
`inches or more. In addition, a trend in resolution of a screenis
`toward higher definition, e.g., high-definition (HD) image
`quality (1366x768) or full high-definition (FHD) image qual
`ity (1920x1080), and prompt development of a so-called 4K
`Digital Cinema display device, which has a resolution of
`3840x2048 or 4096x2160, is also pushed.
`0007 As a display device has a higher definition, the num
`ber of pixels needed for it is significantly increased. As a
`result, writing time for one pixel is shortened, and thus a
`transistor is required to have high speed operation character
`istics, large on current, and the like. In the meantime, a prob
`lem of energy depletion in recent years has caused demand for
`a display device whose power consumption is Suppressed.
`Therefore, a transistor is also required to have low off-state
`current and Suppressed unnecessary leakage current.
`
`REFERENCE
`Patent Document
`Patent Document 1 Japanese Published Patent
`0008
`Application No. 2006-165527
`
`Patent Document 2 Japanese Published Patent
`0009
`Application No. 2006-165528
`(0010
`Patent Document 3 Japanese Published Patent
`Application No. 2006-165529
`
`DISCLOSURE OF INVENTION
`0011 A transistor using an oxide semiconductor has
`higher field-effect mobility than a transistor using amorphous
`silicon. However, a transistor using an oxide semiconductor
`has lower field-effect mobility than a transistor using poly
`crystalline silicon, so that field-effect mobility of a transistor
`using an oxide semiconductor is required to be further
`improved.
`0012. In addition, a difference from the stoichiometric
`composition in an oxide semiconductor arises in a formation
`process. For example, electrical conductivity of an oxide
`semiconductor is changed due to excess and deficiency of
`oxygen. Further, hydrogen that enters the oxide semiconduc
`tor thin film during the formation of the thin film forms an
`oxygen (O)-hydrogen (H) bond and serves as an electron
`donor, which is a factor of changing electric conductivity.
`Further, the O-H bond is a bond having polarity; and thus,
`the O-H bond might cause variation in characteristics of an
`active device Such as a transistor formed using an oxide
`semiconductor.
`0013 Even when the electron carrier concentration is
`lower than 10"/cm, the oxide semiconductoris substantially
`n-type, and the on/off ratio of the transistors disclosed in the
`above patent documents is only 10. Suchallow on/offratio of
`the transistor is due to large off-state current.
`0014. The present invention is made in view of the fore
`going technical background. Therefore, an object of the
`present invention is to provide a semiconductor device in
`which transistors with different characteristics, specifically, a
`transistor with excellent dynamic characteristics (on charac
`teristics or frequency characteristics (referred to as feharac
`teristics)) and a transistor having a reduced off-state current,
`are provided over one substrate. Further, another object is to
`provide a simple method for manufacturing the semiconduc
`tor device.
`0015. In order to achieve the above-described object, in
`the invention, an oxide semiconductor layer which is intrinsic
`or Substantially intrinsic and includes a crystalline region in a
`Surface portion is focused. A semiconductor from which an
`impurity which is to be an electron donor (donor) from an
`oxide semiconductor is removed and which has a larger
`energy gap than a silicon semiconductor can be used as a
`semiconductor which is intrinsic or Substantially intrinsic.
`The electric characteristics of transistors is controlled by
`controlling the potential of a pair of conductive films which
`are provided on opposite sides form each other with respect to
`the oxide semiconductor layer, each with an insulating film
`arranged therebetween, so that the position of a channel
`formed in the oxide semiconductor layer is determined.
`0016 One embodiment of the present invention is a semi
`conductor device in which a transistor with excellent dynamic
`characteristics and a transistor with stable electric character
`istics (e.g., an extremely reduced off-state current) are used
`over one substrate. Specifically, an embodiment of the present
`invention is a semiconductor from which an impurity which is
`to be an electron donor (donor) from an oxide semiconductor
`is removed and which has a larger energy gap than a silicon
`semiconductor can be used. Using the oxide semiconductor,
`an oxide semiconductor layer which is intrinsic or Substan
`
`BLUEHOUSE EXHIBIT 1004
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`

`

`US 2011/O 109351 A1
`
`May 12, 2011
`
`tially intrinsic and includes a crystalline region in a Surface
`portion of the oxide semiconductor layer is formed. In addi
`tion, a plurality of transistors having a structure in which
`conductive films which are provided on opposite sides from
`each other with respect to the oxide semiconductor layer, each
`with an insulating film arranged therebetween is provided
`over one substrate.
`0017. That is, an embodiment of the present invention is a
`semiconductor device including a first electrode layer, a first
`insulating film over the first electrode layer, an oxide semi
`conductor layer including a crystalline region in a Surface
`portion of the oxide semiconductor layer, over the first insu
`lating film, a second electrode layer and a third electrode layer
`over the first electrode layer and in contact with the oxide
`semiconductor layer, the second electrode layer having an
`end portion overlapping with the first electrode layer, and the
`third electrode layer having an end portion overlapping with
`the first electrode layer, a second insulating film including an
`oxide insulating film in contact with the second electrode
`layer, the third electrode layer, and the oxide semiconductor
`layer, and a fourth electrode layer overlapping with the first
`electrode layer and the oxide semiconductor layer, over the
`second insulating film. In addition, the semiconductor device
`includes a plurality of transistors in which an energy gap of an
`oxide semiconductor used in the oxide semiconductor layer is
`greater than or equal to 2 eV.
`0018. An embodiment of the present invention is an
`inverter circuit which includes the above-described semicon
`ductor device including a depression transistor and an
`enhancement transistor.
`0019. An embodiment of the present invention is includes
`a display device which includes the above-described semi
`conductor device including a pixel portion and a driver circuit
`portion which drives the pixel portion.
`0020. An embodiment of the present invention is a driving
`method using the first electrode layer as a main gate electrode
`in at least one transistor and the fourth electrode layer as a
`main gate electrode in the other transistors in the above
`described semiconductor device.
`0021. An embodiment of the present invention is a driving
`method using the fourth electrode layer as a main gate elec
`trode in the depletion transistor and the fourth electrode layer
`as a main gate electrode in the enhancement transistor in the
`above-described inverter circuit.
`0022. An embodiment of the present invention is a driving
`method using the first electrode layer as a main gate electrode
`in at least one transistor included in the pixel portion and the
`fourth electrode layer as a main gate electrode in at least one
`transistor included in the driver circuit portion in the above
`described display device.
`0023. An embodiment of the present invention is a manu
`facturing method of a semiconductor device including the
`steps of forming a first electrode layer, forming a first insu
`lating film over the first electrode layer, forming an oxide
`semiconductor layer over the first insulating film, performing
`dehydration or dehydrogenation on the oxide semiconductor
`layer so that a crystalline region is formed in a surface portion
`of the oxide semiconductor layer, forming a second electrode
`layer and a third electrode layer over the first electrode layer
`and in contact with the oxide semiconductor layer, the second
`electrode layer having an end portion overlapping with the
`first electrode layer, and the third electrode layer having an
`end portion overlapping with the first electrode layer, forming
`a second insulating film including an oxide insulating film in
`
`contact with the second electrode layer, the third electrode
`layer, and the oxide semiconductor layer, and forming a
`fourth electrode layer overlapping with the first electrode
`layer and the oxide semiconductor layer, over the second
`insulating film. In addition, the above-described semiconduc
`tor device includes a plurality of transistors over one substrate
`in which an energy gap of an oxide semiconductor used in the
`oxide semiconductor layer is greater than or equal to 2 eV.
`0024. In this specification, an EL layer refers to a layer
`provided between a pair of electrodes in a light-emitting
`element. Thus, a light-emitting layer containing an organic
`compound that is a light-emitting Substance which is inter
`posed between electrodes is an embodiment of the EL layer.
`0025 Note that in this specification, a light-emitting
`device refers to an image display device, a light-emitting
`device, or a light source (including a lighting device). In
`addition, the light-emitting device includes any of the follow
`ing modules in its category: a module in which a connector
`such as a flexible printed circuit (FPC), a tape automated
`bonding (TAB) tape, or a tape carrier package (TCP) is
`attached to a light-emitting device; a module having a TAB
`tape or a TCP provided with a printed wiring board at the end
`thereof, and a module having an integrated circuit (IC)
`directly mounted over a Substrate over which a light-emitting
`element is formed by a chip on glass (COG) method.
`0026. According to one embodiment of the present inven
`tion, a crystalline region included in an oxide semiconductor
`layer is used as a channel formation region, whereby opera
`tion speed of the circuit included in a semiconductor device
`can be increased. In addition, a circuit is formed using a
`transistor in which a purified oxide semiconductor is used,
`whereby operation of the circuit included in a semiconductor
`device can be stabilized. Further, off-state current reduced to
`1x10' A or lower, whereby a storage capacitor included in
`a semiconductor device can be reduced in size or in number.
`Further, a semiconductor device including transistors with
`different characteristics over one substrate can be provided.
`Furthermore, the semiconductor device can be manufactured
`by a simple method.
`
`BRIEF DESCRIPTION OF DRAWINGS
`0027. In the accompanying drawings;
`0028 FIGS. 1A to 1E each illustrate a manufacturing
`method of a semiconductor device according to an embodi
`ment;
`0029 FIG. 2 illustrates a semiconductor device according
`to an embodiment;
`0030 FIGS. 3A to 3C each illustrate an inverter circuit
`according to an embodiment;
`0031 FIGS. 4A to 4C each illustrate a shift register
`according to an embodiment;
`0032 FIGS.5A and 5B each illustrate a pulse output cir
`cuit according to an embodiment;
`0033 FIGS. 6A to 6D each illustrate a pulse output circuit
`according to an embodiment;
`0034 FIGS. 7A to 7D each illustrate a pulse output circuit
`according to an embodiment;
`0035 FIGS. 8A and 8B each illustrate a timing chart
`according to an embodiment;
`0036 FIGS. 9A and 9B are block diagrams of display
`devices according to an embodiment;
`0037 FIGS. 10A and 10B each illustrate a driver circuit of
`a display device according to an embodiment;
`
`BLUEHOUSE EXHIBIT 1004
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`

`US 2011/O 109351 A1
`
`May 12, 2011
`
`0038 FIGS. 11A1 and 11A2 are cross-sectional views and
`FIG. 11B is a plan view each illustrating an embodiment of
`the present invention;
`0039 FIG. 12 is a cross-sectional view illustrating an
`embodiment of the present invention;
`0040 FIG. 13 is a cross-sectional view illustrating an
`embodiment of the present invention;
`0041
`FIG. 14 shows an equivalent circuit of a pixel in a
`semiconductor device;
`0042 FIGS. 15A to 15C are cross-sectional views each
`illustrating an embodiment of the present invention;
`0.043
`FIGS. 16A and 16B area cross-sectional view and a
`plan view, respectively, illustrating an embodiment of the
`present invention;
`0044 FIGS. 17A and 17B each illustrate an example of a
`usage mode of electronic paper;
`0045 FIG. 18 is an external view illustrating an example
`of an electronic book reader;
`0046 FIGS. 19A and 19B are external views illustrating
`examples of a television device and a digital photo frame,
`respectively;
`0047 FIGS. 20A and 20B are external views illustrating
`examples of game machines;
`0048 FIGS. 21A and 21B are external views illustrating
`examples of cellular phones;
`0049 FIGS. 22A1, 22A2, 22B1 and 22B2 are each illus
`trates an end portion of a display device according to an
`embodiment;
`0050 FIG. 23 is a longitudinal cross-sectional view of an
`inverted Staggered transistor in which an oxide semiconduc
`tor is used;
`0051
`FIG. 24A shows energy band diagrams (schematic
`diagrams) along the section A-A illustrated in FIG. 23 in the
`case in which the potential of the source and the potential of
`the drain are the same (VO), and FIG. 24B shows energy
`band diagrams (Schematic diagrams) along A-A illustrated in
`FIG. 23 in the case in which positive potential is applied to the
`drain (V, 0) with respect to the source:
`0052 FIG.25 shows an energy band diagram (a schematic
`diagram) along the section B-B' illustrated in FIG. 23 in the
`case in which the gate Voltage is 0 V.
`0053 FIG. 26A shows an energy band diagram (a sche
`matic diagram) along B-B' illustrated in FIG. 23 in the case in
`which a positive potential (V-0) is applied to a gate (GE1),
`and FIG. 26B shows an energy band diagram (a schematic
`diagram) along B-B' illustrated in FIG.23 in the case in which
`a negative potential (VO) is applied to the gate (GE1); and
`0054 FIG. 27 shows a relation between the vacuum level
`and the work function of a metal (pM), and between the
`vacuum level and the electron affinity of an oxide semicon
`ductor (X).
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`0055. Hereinafter, embodiments of the present invention
`will be described in detail with reference to the accompanying
`drawings. Note that the present invention is not limited to the
`description below and it is easily understood by those skilled
`in the art that the mode and details can be changed variously.
`Therefore, the present invention is not construed as being
`limited to description of the embodiments. Note that in the
`drawings of this specification, the identical portions or por
`
`tions having a similar function are denoted by the identical
`reference numerals, and description thereon may be omitted.
`
`Embodiment 1
`
`0056. In this embodiment, one embodiment of a substrate
`provided with a circuit of a display device and a manufactur
`ing method of the substrate provided with a circuit as one
`embodiment of a semiconductor device and a manufacturing
`method of the semiconductor device will be described with
`reference to FIGS 1A to 1E.
`0057 FIG. 1E illustrates an example of a cross-sectional
`structure of a plurality of transistors formed over a substrate
`provided with a circuit of a display device. Transistors 440A
`and 440B illustrated in FIG. 1E each have a kind of four
`terminal structure in which a pair of electrode layers which
`are provided on opposite sides from each other with respect to
`a channel formation region of an oxide semiconductor layer,
`each with an insulating film arranged therebetween. Note that
`a so-called dual-gate transistor in which a pair of electrode
`layers which are provided on opposite sides from each other
`with respect to a channel formation region of an oxide semi
`conductor layer, each with an insulating film arranged ther
`ebetween is one embodiment of the four-terminal structure of
`this embodiment. Further, the case where the transistor 440B
`is applied to a pixel of a display device and the transistor 440A
`is applied to part of a driver circuit arranged in the periphery
`of a pixel portion will be described.
`0058. The transistor 440A includes a first electrode layer
`421a, a first insulating layer 402, an oxide semiconductor
`layer 404a including a crystalline region 405a, a second elec
`trode layer 455a, and a third electrode layer 455b over a
`Substrate 400 having an insulating Surface. In addition, the
`transistor 440A includes a second insulating layer 428 which
`is in contact with the crystalline region 405a and covers the
`transistor 440A, and a fourth electrode layer 422a which is
`provided over a channel formation region with the second
`insulating layer 428 interposed therebetween. The first elec
`trode layer 421a and the oxide semiconductor layer 404a
`including the crystalline region 405a overlap with each other
`with the first insulating layer 402 interposed therebetween.
`Further, the second electrode layer 455a and the third elec
`trode layer 455b are formed over the oxide semiconductor
`layer 404a so that part of the second electrode layer 455a part
`of the third electrode layer 455b overlap with the oxide semi
`conductor layer 404a.
`0059. The transistor 440B includes a first electrode layer
`421b, the first insulating layer 402, an oxide semiconductor
`layer 404b including a crystalline region 405b, a second elec
`trode layer 455c, and a third electrode layer 455d over the
`Substrate 400 having an insulating Surface. In addition, the
`transistor 440B includes the second insulating layer 428
`which is in contact with the crystalline region 405b and cov
`ers the transistor 440B and a fourth electrode layer 422b
`which is provided over the channel formation region with the
`second insulating layer 428 interposed therebetween. The
`first electrode layer 421b and the oxide semiconductor layer
`404b including the crystalline region 405b overlap with each
`other with the first insulating layer 402 interposed therebe
`tween. Further, the second electrode layer 455c and the third
`electrode layer 455d are formed over the oxide semiconduc
`tor layer 404b so that part of the second electrode layer 455c
`part of the third electrode layer 455d overlap with the oxide
`semiconductor layer 404b.
`
`BLUEHOUSE EXHIBIT 1004
`Page 32 of 61
`
`

`

`US 2011/O 109351 A1
`
`May 12, 2011
`
`0060. The transistors 440A and 440B each have a dual
`gate structure. In a transistor having a dual-gate structure, one
`or both of electrode layers which are provided on opposite
`sides from each other with respect to an oxide semiconductor
`layer, each with an insulating film arranged therebetween can
`be used as a gate electrode layer. Note that the second elec
`trode layer and the third electrode layer function as a source
`electrode layer and a drain electrode layer.
`0061. In this embodiment, the fourth electrode layer 422a
`of the transistor 440A is used as a main gate electrode of the
`transistor. Accordingly, a channel is formed in a region which
`is positioned between a region in contact with the second
`electrode layer 455a of the oxide semiconductor layer 404a
`and a region in contact with the third electrode layer 455b of
`the oxide semiconductor layer 404a, which is in contact with
`the second insulating layer 428, and which overlaps with the
`fourth electrode layer 422a.
`0062. The first electrode layer and the fourth electrode
`layer are provided on opposite sides from each other with
`respect to the oxide semiconductor layer, each with the insu
`lating film arranged therebetween. Note that in this embodi
`ment, in the case where the potential of the first electrode
`layer is higher that that of the fourth electrode layer, the first
`electrode layer is referred to as a main gate electrode, and in
`the case where the potential of the fourth electrode layer is
`higher that that of the first electrode layer, the fourth electrode
`layer is referred to as a main gate electrode. The potential of
`either the first electrode layer or the fourth electrode layer
`may be GND, 0 V, or in a floating state.
`0063. The first electrode layer 421b of the transistor 440B
`is used as a main gate electrode of the transistor. Accordingly,
`a channel is formed in a region which is positioned between a
`region in contact with the second electrode layer 455c of the
`oxide semiconductor layer 404b and a region in contact with
`the third electrode layer 455d of the oxide semiconductor
`layer 404b, which is in contact with the first insulating layer
`402, and which overlaps with the first electrode layer 421b.
`0064. Note that the transistor 440B can have a light-trans
`mitting property when the first electrode layer 421b, the sec
`ond electrode layer 455c, the third electrode layer 455b, and
`the fourth electrode layer 422b are formed using a light
`transmitting conductive film. In the case where a light-trans
`mitting transistor is applied to a pixel of a display device, the
`aperture ratio of the pixel can be improved.
`0065. As a material of the light-transmitting conductive
`film, a conductive material that transmits visible light, for
`example, an In Sn-O-based oxide conductive material, an
`In—Sn-Zn-O-based oxide conductive material, an
`In—Al-Zn-O-based oxide conductive material, a