pd
`
`Planet Depos0
`We Make It Happen™
`
`pt of Martin
`Transcri
`Rinard, Ph.D.
`
`Date: June 3, 2022
`
`
`
`(PTAB) (INTEL) Case: Intel Corporation -v-Qualcomm Incorporated
`
`Planet Depos
`Phone: 888.433.3767
`IPR2018-01334
`Email: transcripts@planetdepos.com
`Intel v. Qualcomm
`INTEL 1028
`
`www. planetdepos.com
`
`
`
`WORLDWIDE COURT REPORTING & LITIGATION TECHNOLOGY
`
`
`
`
`
`Planet Depos0
`We Make It Happen™
`
`pt of Martin
`Transcri
`Rinard, Ph.D.
`
`Date: June 3, 2022
`
`
`
`(PTAB) (INTEL) Case: Intel Corporation -v-Qualcomm Incorporated
`
`Planet Depos
`Phone: 888.433.3767
`IPR2018-01334
`Email: transcripts@planetdepos.com
`Intel v. Qualcomm
`INTEL 1028
`
`www. planetdepos.com
`
`
`
`WORLDWIDE COURT REPORTING & LITIGATION TECHNOLOGY
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`
`Petitioner,
`
`Vv.
`
`QUALCOMM INCORPORATED,
`
`Patent Owner.
`
`IPR2018-01334
`
`U.S. Patent No. 8,838,949
`
`Reported by: Renee J. Ogden, CSR-3455, RPR
`
`Deposition of MARTIN RINARD, Ph.D.
`
`Conducted Virtually
`
`Friday, June 3, 2022
`
`7:03 a.m.
`
`Job No.: 451226
`
`Pages:
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`1 - 88
`
`
`
`2
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`APPEARANCES :
`
`ON BEHALF OF THE PETITIONER:
`
`WILMER CUTLER PICKERING HALE AND DORR, LLP
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Jrnightingale@jonesday.com
`
`BY:
`
`JOSEPH F. HAAG
`
`1875 Pennsylvania Avenue, NW
`
`Washington, DC 20006
`
`(202) 663-6000
`
`Joseph. haag@wilmerhale.com
`
`ON BEHALF OF THE PATENT OWNER:
`
`JONES DAY
`
`BY:
`
`JOSHUA R. NIGHTINGALE
`
`500 Grant Street
`
`Suite 4500
`
`Pittsburgh, Pennsylvania 15219
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`(412) 394-7950
`
`
`
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`3
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`TABLE OF CONTENTS
`
`WITNESS
`
`MARTIN RINARD, Ph.D.
`
`EXAMINATION
`
`BY MR. HAAG
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`(Exhibits not offered.)
`
`INDEX TO EXHIBITS
`
`EXHIBIT
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`Friday, June
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`7:03 a.m.
`
`4
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`and that I will be reporting this deposition and
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`PLANET DEPOS TECH:
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`Thank you to
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`everyone for attending this proceeding remotely
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`which we anticipate will run smoothly.
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`Please
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`remember to speak slowly and do your best not to
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`talk over one another, and please be aware that we
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`are recording this proceeding for backup purposes.
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`Any off-the-record discussions should be had away
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`the reporter identify who is speaking.
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`If you're
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`please identify yourself each time before speaking.
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`And I apologize in advance for any
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`technical-related interruptions.
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`Thank you.
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`COURT REPORTER:
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`The attorneys
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`participating in this deposition acknowledge that
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`I'm not physically present in the deposition room
`
`
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`5
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`administering the oath remotely.
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`The parties and their counsel consent to
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`this arrangement and waive any objections to this
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`manner of reporting.
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`Counsel, please indicate your agreement
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`on the record.
`
`MR. HAAG: This is Joseph Haag. We
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`And what is your current address?
`
`
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`MR. NIGHTINGALE: This is Josh
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`Nightingale of Jones Day. We agree.
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`MARTIN RINARD, Ph.D.,
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`was thereupon called as a witness herein, and after
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`having first been duly sworn or affirmed to testify
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`to the truth,
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`the whole truth and nothing but the
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`truth, was examined and testified as follows:
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`EXAMINATION
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`BY MR. HAAG:
`
`Good morning.
`
`Good morning.
`
`Can you please state your full name for the record?
`
`Martin Conway Rinard.
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`0o0FPOOFPCOYFOOPF
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`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`I do.
`
`48 Robbins Road, Arlington, Massachusetts 02416.
`
`And where are you currently located?
`
`6
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`At that address.
`
`So is that your home address?
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`Yes, it is.
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`Do you understand that you're under oath today?
`
`Yes,
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`I do.
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`And do you understand that you must answer
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`truthfully and fully just as if you were in the
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`court?
`
`Yes,
`
`I do.
`
`Is there any reason you cannot provide your best
`
`and honest testimony here today?
`
`Not that I'm aware of.
`
`Approximately how many times have you been deposed
`
`before?
`
`It's hard for me to give you an exact answer.
`
`I
`
`would say in the ballpark of 10, maybe 12; maybe a
`
`little bit more than that, maybe a little less.
`
`So you understand that I'll be asking you a series
`
`of questions here today?
`
`Yes,
`
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`7
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`And you'll be providing answers as best you can?
`
`That's my understanding.
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`And I would appreciate it if you don't interrupt
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`when I'm trying to ask a question.
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`Can we agree
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`that?
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`I'll do my best.
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`And I'll also do my best to try not to interrupt
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`your answers, okay?
`
`Okay.
`
`Have you been deposed by -- over a video link
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Let me see.
`
`
`
`before?
`
`Yes,
`
`I have.
`
`Okay.
`
`Do you have any documents in front of you?
`
`Physical documents?
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`I have Gupta;
`
`this is the '949 Patent.
`
`I've got
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`Svensson U.S. Patent 7,356,680.
`
`I've also got
`
`Bauer, which is -- yeah,
`
`I think we know what I'm
`
`talking about.
`
`Okay.
`
`Do you have any notes on those documents?
`
`No,
`
`I don't.
`
`They should be clean copies.
`
`And is the '949 Patent exhibit marked 1001?
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`8
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`It says Intel 1001, and it appears to be
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`a copy of the -- well, we'll see it if loads.
`
`Yeah.
`
`It appears it be a copy of the '949 Patent.
`
`I haven't examined every page, but it looks
`
`familiar.
`
`Okay. And then physical copy of Svensson that you
`
`have,
`
`is that marked Exhibit 10- -- 1010?
`
`No.
`
`It's just -- it's not marked at all.
`
`Okay.
`
`A.
`
`Q.
`
`A.
`
`It doesn't have an exhibit marker on it.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Do you have any other electronic documents open?
`
`
`
`Q.
`
`A.
`
`Q.
`
`A.
`
`Q.
`
`And then is Bauer,
`
`is that marked 1009?
`
`No markings on it whatsoever.
`
`Okay.
`
`No exhibit markings.
`
`You don't have any handwritten notes on any of
`
`those physical documents?
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`No,
`
`I don't.
`
`And just before the deposition started,
`
`I believe
`
`you downloaded copies of Exhibit 1001, 2015, and
`
`2014;
`
`is that right?
`
`That's correct.
`
`PLANET DEPOS
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`9
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`No,
`
`I do not.
`
`So I'd like to turn first to --
`
`Just for clarification?
`
`sure.
`
`So I'm looking at -- okay.
`
`You know,
`
`I'm just
`
`looking for the exhibit numbers on the documents
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`and I see them,
`
`so I think we're good.
`
`It should be lower right of the first page.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Yeah, again, without examining it, it
`
`
`
`Yeah,
`
`I see them.
`
`Do you see that, sir?
`
`I do.
`
`Okay.
`
`So I'd like to first turn to Exhibit 2015.
`
`Okay. Which one's that again? Oh, that's my
`
`declar- -- that's the remanded declaration of
`
`Dr. Martin Rinard, correct?
`
`Yes.
`
`Do you have that in front of you?
`
`Give me a second.
`
`Yes,
`
`I have it in front of me.
`
`And do you recognize this document?
`
`Let me take a look.
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`PLANET DEPOS
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`10
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`appears to the remanded declaration of -- filed in
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`this case.
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`And do you see your signature on the last page?
`
`Yes,
`
`I do.
`
`That is your Signature, right?
`
`It appears to be, yes.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Pardon me?
`
`
`
`And approximately how much time did you spend on
`
`this declaration?
`
`Difficult for me to give you an exact answer.
`
`I
`
`would say, again, ballpark some tens of hours.
`
`I
`
`would say certainly less than 100; probably less
`
`than 50.
`
`It would be difficult for me to be more
`
`exact than that.
`
`And I think you've spent a decent amount of time on
`
`the '949 Patent over the past few years, right?
`
`I don't know whether I would characterize it as
`
`"decent" or not, but, yes, I've been involved with
`
`this patent in several litigations.
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`And you have been deposed on it at least a couple
`
`times; if not a few times, right?
`
`I'd say that's accurate, yes.
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`11
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`I've been deposed several times on matters
`
`involving the '949 Patent.
`
`So I'd like to turn first to paragraph -- if I can
`
`find it -- paragraph 45 of your declaration of
`
`Exhibit 2015.
`
`It should be on page 22.
`
`Yes.
`
`Do you have that in front of you, sir?
`
`Paragraph 45 you said?
`
`Yes.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Do you see that?
`
`
`
`Yes,
`
`I have paragraph 45 in front of me.
`
`And in paragraph 45, you address claims 1 and 2,
`
`right?
`
`I believe that's correct, yes.
`
`This is claims 1 and 2 of the '949 Patent, right?
`
`That's my understanding.
`
`And you say that claims 1 and 2 have a different
`
`scope under your proposed construction, right?
`
`Well,
`
`I believe it said "different scopes under my
`
`proposed construction."
`
`And there's a sentence that begins with "Claim 2
`
`further limits."
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`PLANET DEPOS
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`Yes, next to last sentence in the paragraph.
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`Is
`
`that what you're referring to?
`
`12
`
`Yes.
`
`please?
`
`Can you read that out
`
`loud for us,
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`I note that there's more sentences in
`
`Do you want me to read the whole paragraph?
`
`Just
`
`that one sentence.
`
`Just that one sentence.
`
`Yeah.
`
`So just for context,
`
`I think -- I'm happy to
`
`read that one sentence, but I want -- but I'll just
`
`remark that that one sentence occurs in the context
`
`of paragraph 45, and it's a single sentence in the
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`middle of paragraph 45.
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`The context would include
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`the sentences before it and the sentences after it.
`
`So having that,
`
`the sentence that you've asked me
`
`to read reads:
`
`"Claim 2 further limits the scatter
`
`loader controller element by adding limitations on
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`how it 'directly'
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`loads into system memory -
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`specifically, expressly excluding 'copying data
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`between system memory locations on the secondary
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`processor.'"
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`
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`13
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`that paragraph and in the declaration in general
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`that provide additional context to the sentence
`
`that I just read.
`
`So in that sentence am I right that you're saying
`
`that claim 2 further limits claim 1
`
`in that claim 2
`
`excludes copying between system memory locations on
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`the secondary processor?
`
`MR. NIGHTINGALE: Objection to form.
`
`Let me take a quick like here. You're asking me
`
`about -- I'm understanding your question to be
`
`asking me specifically about the text of claim 2.
`
`I have claim 2 here, and it says -- it includes the
`
`limitation of "without copying data between system
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`memory locations on the secondary processor."
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`From claim 1 it further limits
`
`
`
`BY MR. HAAG:
`
`Q.
`
`So in that sentence, you're saying that claim 2
`
`further limits claim 1, right?
`
`I believe claim 2 does further limit claim l, yes.
`
`It's a --
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`And you're --
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`It's a defendant claim.
`
`I'm sorry.
`
`It's a
`
`defendant claim.
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`14
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`claim 1.
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`And you're saying that claim 2 excludes copying
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`data between system memory locations on the
`
`secondary processor, right?
`
`I think that's accurate because claim 2 says
`
`"without copying data between system memory
`
`locations on the secondary processor."
`
`
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`If you look at the
`
`And you're saying that claim 2 further limits the
`
`scatter loader controller of claim 1, right?
`
`That's one of the things I'm saying here because it
`
`says -- I mean, claim 2 starts "The multi-processor
`
`system of claim 1
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`in which the system" -- "the
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`scatter loader control is configured," and then it
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`goes on.
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`So one of the things it's doing is it's
`
`limiting the configuration of the scatter loader
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`controller from claim 1.
`
`And so in claim 1, it allows copying data between
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`system memory locations on the secondary processor,
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`but claim 2 does not;
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`is that right?
`
`I would not agree with that characterization
`
`because claim 1 -- there's certain important things
`
`that claim 1 does limit.
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`15
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`variety of limitations in claim 1, claim 1
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`includes
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`a limitation "to scatter load each received data
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`segment based at least in part on the loaded image
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`header, directly from the hardware buffer to the
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`system memory." And that limits -- that -- in
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`fact,
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`that excludes copying between system memory
`
`locations for the received data segments.
`
`So how do you think claim 2 further limits claim 1?
`
`As I say in my expert report, and here I am reading
`
`the very last sentence of paragraph 45,
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`I say:
`
`"I
`
`note that claim 1 recites the term 'data segment, '
`
`and claim 2 recites the term 'data.'"
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`So what is it about claim 2 that you think further
`
`
`
`I'll also note additionally that claim 2
`
`says -- includes the limitation where "the software
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`loader controller is configure" -- "configured to
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`load the executable software image directly from
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`the hardware buffer to the system memory of the
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`secondary processor"; whereas, claim 1 says "to
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`scatter load each received data segment based at
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`least in part on the loaded image header, directly
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`from the hardware buffer to the system memory."
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`16
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`limits claim 1?
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`The use of the term "data segment" in claim 1 and
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`"data" in claim 2 as well as, again,
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`the use of the
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`term "data segment" in claim 1 and the use of the
`
`term "software image" in claim 2.
`
`Those are two
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`segment has been litigated extensively in this
`
`differences between --
`
`Do you agree with --
`
`I'm sorry.
`
`Those are two differences between
`
`claim 1 and claim 2.
`
`Do you agree with me that "data" is a broader term
`
`than "data segment"?
`
`I would say that often depends on context, and you
`
`would have to consider the context carefully.
`
`In
`
`this situation,
`
`I think that there are things that
`
`you could potentially consider to be data that are
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`not necessarily data segments in the context of
`
`this patent and these two claims.
`
`Do you agree with me that a data segment is data,
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`right?
`
`I would say the data segment contains data, but
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`there's -- I will also point out that the term data
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`
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`17
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`case. There's a lot of nuance here and conditions
`
`here that we're going to have to go through if
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`we're going to get deep into it.
`
`I'm going to have
`
`to ask you to show me various documents and trial
`
`testimony to get deep into it.
`
`So you have got a sentence here that reads:
`
`"Claim 2 further limits the data loader controller
`
`element by adding limitations on how it directly
`
`loads into system memory, specifically expressly
`
`excluding copying data between system memory
`
`locations on the secondary processor."
`
`You see that sentence, right?
`
`Just to keep the record clean,
`
`I believe you read
`
`that sentence inaccurately.
`
`I think you said "data
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`loader controller" instead of "scatter loader
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`scatter loader controller is configured to," and
`
`
`
`controller."
`
`Okay.
`
`Now, you say there "Claim 2 further limits."
`
`What do you mean by "further limits"?
`
`All I'm saying is that I'm referring here to the
`
`first sentence of the claim 2 where it says "The
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`multiprocessor system of claim 1
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`in which the
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`18
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`then the claim goes on.
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`So that's what I'm
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`referring to.
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`I'm referring to the first part of
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`the sentence of claim 2.
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`What do you mean by "further limits"?
`
`It just says, “further limits the scatter
`
`controller."
`
`The configuration of the scatter
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`controller, set scatter loader controller.
`
`If you
`
`look at claim 1 --
`
`I'm sorry.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`"further limits" means in your sentence. What does
`
`
`
`-- you will see that claim 1
`
`includes a scatter
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`loader controller configured and then there are
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`several claim elements, and further to -- and in
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`claim 2 further limits the configuration of the
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`scatter loader controller as laid out in the
`
`following text in claim 2.
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`So by "further limits," you mean adds an additional
`
`feature to it?
`
`MR. NIGHTINGALE: Objection to form.
`
`A.
`
`I wouldn't put it that way at all.
`
`BY MR. HAAG:
`
`Q. Sir,
`
`I'm just trying to understand what you think
`
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`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`19
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`that mean?
`
`MR. NIGHTINGALE: Objection to the form.
`
`I would say that it imposes -- I'm sorry.
`
`I
`
`didn't -- can I hear the question again to be sure
`
`we're on the same page?
`
`BY MR. HAAG:
`
`Q. What does "further limits" mean in your paragraph
`
`secondary processor," right?
`
`
`
`45?
`
`MR. NIGHTINGALE:
`
`Same objection.
`
`I understand you to be asking me about the next to
`
`last sentence in claim 45.
`
`I think I'm saying that
`
`it adds an additional requirement to the
`
`configuration of the scatter loader controller as
`
`laid out in claim 2.
`
`I'm finding it difficult to
`
`give you a more precise answer than simply reading
`
`back the language of claim 2 because I think that
`
`the language of claim 2 is clear on how it further
`
`limits the configuration.
`
`BY MR. HAAG:
`
`Q. And you say "specifically expressly excluding
`
`copying data between system memory locations on the
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`A.
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`I believe -- I believe that sentence directly
`
`copies the language from claim 2.
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`20
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`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`part on the loaded image shutter directly from the
`
`So are you saying that claim 1 allows copying data
`
`between system memory locations on the secondary
`
`processor and claim 2 does not?
`
`Let me be precise here. What I'm saying is,
`
`claim 1 expressly says in the claim element to
`
`"scatter load each received data segment based at
`
`least in part on the loaded image header directly
`
`from the hardware buffer to the system memory."
`
`That claim element rules out any copying
`
`of data segments between system memory locations on
`
`the -- in between system memory locations and I
`
`suppose I should say on the secondary processor in
`
`claim 1.
`
`So then,
`
`in your view, how does claim 2 further
`
`limit claim 1?
`
`Claim 2 uses the term "data" instead of "data
`
`segment," and it uses the term "executable software
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`image" directly from the hardware buffer instead of
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`using each received data segment based at least in
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`21
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`hardware buffer to the system memory.
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`Those are
`
`two of the differences between claim 1 and claim 2.
`
`If you could turn to paragraph 21 of your
`
`declaration.
`
`Sure.
`
`I'm there.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`If you turn to your declaration to paragraph 9 --
`
`Right about
`
`in the middle of that paragraph, you
`
`refer to final locations in system memory.
`
`Do you
`
`see that?
`
`Please give me a chance to read the paragraph.
`
`Here you are referring to, again,
`
`the
`
`next to last sentence in that paragraph where the
`
`sentence refers to Figure 3?
`
`Yes.
`
`It refers to final locations in system
`
`memory.
`
`Do you see that?
`
`I do see that. That's, again, referring to final
`
`locations in system memory 305 referencing
`
`Figure 3.
`
`What do you mean by "final locations"?
`
`It means in this case the locations where they
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`are -- that means they're final locations. That
`
`means they're not copied to any other location.
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`Okay.
`
`I'm there.
`
`On this page you referred to a couple -- I think
`
`they're books by Hennessy and Patterson.
`
`Yeah.
`
`You are referring here to Hennessy and
`
`Patterson, "Computer Architecture-A Quantitative
`
`Approach," the fourth and fifth editions.
`
`And are those books?
`
`Yes,
`
`they are.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`I'm not going to try
`
`
`
`And I think you have portions of at least one of
`
`those in Exhibit 2014, right?
`
`Let me check that. Let me see what we have here.
`
`It's a long book.
`
`I'm not going to try on what is
`
`and isn't present in Exhibit 2014.
`
`I think we can
`
`go on here if you have got some specific part of
`
`the book you are interested in.
`
`I just have a couple questions.
`
`I mean,
`
`this is
`
`your exhibit that you attached to your declaration,
`
`right, Exhibit 14?
`
`I referenced the book,
`
`I attached it to -- I
`
`presume it's been filed with my declaration.
`
`Whether what I'm seeing on the screen before me or
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`not is the full book or not,
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`to take a position on that issue without doing a
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`lot of examination, and I don't think we need to do
`
`that right here.
`
`The full book is longer than 77 pages,
`
`though,
`
`right?
`
`Yes.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`declaration.
`
`
`
`I think this exhibit is 77 pages, right?
`
`Let me see. That's what the PDF reader says.
`
`Okay.
`
`So we can agree that Exhibit 2014 is at
`
`least some excerpts from a Hennessy and Patterson
`
`book, right?
`
`I think that's a logical conclusion based on what
`
`you told me. Yeah,
`
`I think it goes directly from
`
`the table of contents to chapter 5.
`
`Presumably in
`
`the book there's chapters 1 through 4 as listed in
`
`the table of contents.
`
`So you selected the portions you thought were the
`
`most relevant to include this Exhibit 2014;
`
`is that
`
`fair?
`
`I selected the portions of these books I thought
`
`were most relevant and cited them in my
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`And it looks like Exhibit 2014 is the fourth
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`edition of the Hennessy and Patterson book;
`
`is that
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`24
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`right?
`
`That's what it says.
`
`And why did you cite the Hennessy and Patterson
`
`books?
`
`Just for background.
`
`They are known books in
`
`computer architecture.
`
`I'm familiar with them.
`
`I'm familiar with the series from various other
`
`editions, and I thought it was useful background.
`
`Are you saying that the Hennessy and Patterson
`
`books are well-known books in architecture?
`
`Yes,
`
`they are very well known.
`
`MR. NIGHTINGALE: Objection,
`
`foundation.
`
`Let me clarify.
`
`I would say they're very well
`
`known to people in computer architecture that I
`
`know and, of course, myself and people in computing
`
`work generally tend to be very aware of this book.
`
`It's a standard textbook used throughout, you know,
`
`many computer architecture courses.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`So you refer to Figure 5.2 on page 289 of
`
`
`
`BY MR. HAAG:
`
`Q.
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`Exhibit 2014.
`
`Do you see that?
`
`Are you asking do you see where I refer to it or do
`
`I see Figure 5.2?
`
`Well, do you see where you refer to it?
`
`Yeah.
`
`It's about the middle of the paragraph 9,
`
`I
`
`believe.
`
`Okay.
`
`Now, can you find that Figure 5.2 on
`
`page 289 of Exhibit 2014?
`
`Sure.
`
`I see Figure 5.2.
`
`The first sentence with the caption of Figure 5.2
`
`says "Starting with 1980, performance as a
`
`baseline,
`
`the gap in performance between memory and
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`comparing the performance gap between a processor
`
`
`
`processors is plotted over time."
`
`Do you see that?
`
`I do see that sentence.
`
`And then it goes on and in the next sentence it
`
`refers to DRAM.
`
`Mm-hmm.
`
`Right.
`
`So am I right that Figure 5.2 is comparing
`
`processor to DRAM memory?
`
`I'm not sure I understand your question.
`
`It's
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`and DRAM.
`
`So Figure 5.2 is comparing the performance gap
`
`between a processor and DRAM?
`
`It's presenting a performance gap between
`
`processors and DRAM.
`
`Am I right that DRAM is a typical type of external
`
`memory?
`
`I would say that DRAM is often used as a form of
`
`memory in many computer systems.
`
`In fact,
`
`the
`
`majority of computer systems that you would see in
`
`a laptop or a desktop, and it has been for several
`
`
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`separate process technology from a processor chip?
`
`decades.
`
`And typically that DRAM is external to the
`
`processor chip, right?
`
`Can you clarify what you mean by "external"?
`
`A separate chip.
`
`It is often a separate chip or -- a separate chip
`
`Or in some cases chips.
`
`From the processor, right?
`
`That's my understanding, yes.
`
`And am I right that DRAM is typically made using a
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`Can you be more specific by what you mean by
`
`"orocess technology"?
`
`Yeah,
`
`I'm talking about the manufacturing
`
`technology in a fab?
`
`You mean fabrication technology?
`
`MR. NIGHTINGALE: Objection to scope,
`
`relevance.
`
`BY MR. HAAG:
`
`Correct.
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`to a processor chip.
`
`
`
`Often that can be the case, yes.
`
`So DRAM is typically made from a different
`
`fabrication technology than the processor chip;
`
`is
`
`that fair?
`
`relevance.
`
`MR. NIGHTINGALE: Objection, scope,
`
`It would help me answer the question if you could
`
`give me some idea of what you're trying to figure
`
`out here.
`
`BY MR. HAAG:
`
`Q.
`
`I'm just trying to figure out if the fabrication
`
`technology is typically different for DRAM compared
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`It can be, yes. And what you refer to here as --
`
`and, you know,
`
`I don't know how deep you want to
`
`get into this, but in a fab, you have a sequence of
`
`steps that you use to manufacture various computer
`
`chips, and those have different technologies, and,
`
`you know, you can make processors in a whole wide
`
`range of technologies.
`
`You can make DRAMs and
`
`other kinds of RAMs as well
`
`in a whole range of
`
`technologies. And often you'll mix different kinds
`
`of technologies together into a computer system for
`
`a variety of reasons,
`
`including costs and other
`
`kinds of -- costs, density, other kinds of
`
`constraints.
`
`So in general, you would expect to
`
`see a computer system, say, over the last several
`
`decades,
`
`incorporating multiple chips and, you
`
`know,
`
`these chips may have been manufactured on fab
`
`lines that use kinds of technologies, sure.
`
`I'd like you to turn to the previous page of
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Yes.
`
`
`
`Exhibit 2014.
`
`Okay.
`
`And there's a Figure 5.1 shown there, right?
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`29
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`And it shows the levels of a typical memory
`
`architecture, right?
`
`The first sentence of Figure 5.1 says "The levels
`
`in a typical memory hierarchy in embedded, desktop,
`
`and server computers."
`
`And on the -- on Figure 5.2,
`
`this comparison
`
`between performance of processor and memory,
`
`there's a memory listed.
`
`Is that memory shown in
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`memory. And I would say Figure 5.1 is more general
`
`
`
`Figure 5.1?
`
`That specific memory.
`
`The memory referred to in Figure 5.2.
`
`Well, if you like at 5.2, it is -- the X axis
`
`covers a range of times from 1980 to 2010, so, of
`
`course,
`
`there's not any one specific memory. And
`
`in Figure 5.2, it's plotting the performance of a
`
`range of memories over time.
`
`Yeah. And what type of memory is that shown
`
`Figure 5.2?
`
`Is it also shown in Figure 5.1?
`
`MR. NIGHTINGALE: Objection,
`
`form.
`
`In general,
`
`I would expect 5.2 to be talking -- the
`
`line that says "Memory" to be referring to DRAM
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`than that potentially, but in practice,
`
`the figure
`
`labeled "Memory" -- the box labeled "Memory" in 5.1
`
`could be and often is implemented in DRAM, but it
`
`doesn't have to be implemented in DRAM.
`
`BY MR. HAAG:
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`Now it shows a CPU, and it's got registers in it,
`
`So the box labeled "Memory" in Figure 5.1 often
`
`would be implemented in DRAM.
`
`Is that fair to say?
`
`It could be.
`
`I mean, many computer systems -- but,
`
`again, you've got to realize 5.1 is an abstraction
`
`of the actual architecture that occurs in many
`
`computer systems.
`
`If you look at the corresponding
`
`figure from the next edition of the machine, you'll
`
`see a slightly different architecture. This is a
`
`conceptual architecture that's intended for -- to
`
`give you an idea of what's going on. There have
`
`been systems that have been built with this
`
`specific -- with an architecture that is captured
`
`accurately, 5- -- Figure 5.1, but there are other
`
`architectures as well. This is intended to be a
`
`conceptual overview of the kinds of levels that you
`
`see in a memory hierarchy.
`
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`right?
`
`You're referring here to the circle in Figure 5.1
`
`labeled "CPU" and inside has a box called
`
`"Registers." That's correct.
`
`And it's got a size and speed listed below that
`
`circle.
`
`I do.
`
`Do you see that?
`
`And what does that speed indicate?
`
`Okay.
`
`So let's see if we can --
`
`MR. NIGHTINGALE: Objection,
`
`relevance
`
`and scope.
`
`So what I'll -- so if you look at the very first
`
`paragraph under 5.1 Introduction,
`
`the very last
`
`line says "Figure 5.1 shows a multilevel memory
`
`hierarchy,
`
`including typical sizes and speeds of
`
`access." And I'll note that these numbers have
`
`changed over time,
`
`so this is something that would
`
`be typical as of the time that this book was
`
`written, and things may have changed later on.
`
`
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`So the speed there refers to speed of
`
`BY MR. HAAG:
`
`Q. Yeah.
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`access?
`
`Again, speeds of access, and I think that's what is
`
`explicitly stated in the last sentence of the first
`
`paragraph of Section 5.1 Introduction.
`
`Figure 5.1 of Exhibit 2014 shows that the speed of
`
`access of the CPU and its registers is about 250
`
`picoseconds, right?
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`of a certain date, and that is -- that time's going
`
`
`
`I don't think that's an accurate characterization
`
`of how I would interpret this.
`
`I would say the
`
`accurate characterization is this is a typically
`
`speed of access for the registers. And [I'll just,
`
`you know,
`
`remark here that registers are -- I mean,
`
`I don't know how deeply you want to get into this,
`
`but registrars are distinct from the memory
`
`hierarchy in the way that they're accessed by the
`
`instructions of architecture.
`
`I can go as far as
`
`you want to into that.
`
`So Figure 5.1 shows that the typical speed of
`
`access for registers is about 250 picoseconds?
`
`MR. NIGHTINGALE: Objection, scope.
`
`Again, let's bear in mind that this is written as
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`to be -- 1S going to be typical as of that date
`
`according to the authors of the paper, but on any
`
`machine and in particular as machines change over
`
`time,
`
`that speed's going to change. And,
`
`in fact,
`
`I don't know that 250 picoseconds specifically is
`
`going to be the exact access time for any machine.
`
`It's going to be a typical range. That's how this
`
`is --
`
`BY MR. HAAG:
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`I'll just say the information in the
`
`
`
`Q. Okay.
`
`I understand.
`
`It's typical range of typical
`
`speed, right?
`
`It's intended to give -- you know, again, a range
`
`or a ballpark of where you might be at for these
`
`systems at this point in time.
`
`I mean,
`
`is it what it's intended to do is compare a
`
`speed of access of CPU registers versus cache
`
`versus memory versus I/O devices?
`
`Is that what
`
`Figure 5.1 is trying to do?
`
`MR. NIGHTINGALE: Objection,
`
`form,
`
`scope,
`
`relevance.
`
`I would hesitate to characterize a figure as having
`
`an intention.
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`figure provides, again, ballpark indications of
`
`what the speeds of access of the various components
`
`labeled in the figure would be,
`
`so that would be,
`
`for example, registers, cache, memory, and I/O
`
`devices as the components of the figure labeled in
`
`the figure.
`
`And, again, I'll just -- I'll just
`
`remark that these things change over time, and this
`
`is intended to be a typical and it isn't -- I would
`
`not expect it to be the case that if you looked at
`
`any specific system, you would find exactly these
`
`Transcript of Martin Rinard, Ph.D.
`Conducted on June 3, 2022
`
`intended to -- to capture the
`
`
`
`numbers in that system.
`
`BY MR. HAAG:
`
`So for the cache Figure 5.1 lists the typical speed
`
`of access of 1 nanosecond, right?
`
`If you look at the Speed column at the bottom of
`
`Figure 5.1, it says "1 ns," and that's nanoseconds.
`
`And if you look at the size, it's 64 kilobytes.
`
`And, again,
`
`I just want to emphasize that these
`
`numbers change over time, and they're intended to
`
`be -- give you a typical idea of what's going on.
`
`They're not
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`characteristics of any specific system.
`
`And so in Figure 5.1,
`
`the cache speed of access is
`
`on the order but slightly larger or slightly higher
`
`than the register access time;
`
`is that right?
`
`Why don't I --
`
`MR. NIGHTINGALE: Objection to scope,
`
`relevance.
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