(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`(19) World Intellectual Property Organization
`International Bureau
`
`|||||||||I|||||l||||||||||||||||lllllIllll|||||||||||||||l||||||||||||||||||||||||||||||||J||||
`
`12 August 2010 (12.08.2010)
`
`(43} International Publication Date
`
`(10) International Publication Number
`
`WO 2010/091105 A2
`
`(51)
`
`(21)
`
`International Patent Classification:
`H03K17/22{2006.0l}
`,
`,
`,
`.
`‘
`‘
`Internatlonal Application Nlll‘llbl‘l':
`I’LTM530‘0’03305'
`
`(22)
`
`International Filing Date:
`
`3 February 3010 (03313010)
`
`(25) Filing Language:
`
`(26) Publication Language:
`(30) merit), Data.
`13305559
`
`4 Febntary 2009(04012009)
`
`English
`‘
`Enghsh
`
`us
`
`(71) Applicant {for all designated States except US): QUAL-
`COMM INCORPORATED IUSIUS'I: Atln: Internation-
`a1 lp Administration, 5175 Morehouse Drive, San Diego,
`CA 92121 (US),
`
`(72)
`(75)
`
`Inventors: and
`InventorstApplieants (for US onh'): KWON. Chang, Ki
`[KIUUS]; 5775 Morehouse Drive, San Diego, CA 92121
`(US). MOHAN, Vivek [USJUS]; 5275 Morehouse Drive,
`San Diego, C A 92l3l (US),
`(74) Agent: TALPALATSKY. Sam: 5775 Morehouse Drive.
`San Diego, CA 92l2l (US).
`
`CA. CH. CL. CN. CO. CR. CU. CZ. DE, DK, DM, DO,
`DZ, EC, Eli, EC), ES, FI, GB, GD, GE, (ill, GM, GT,
`IIN. I-IR, I-IU. ID, IL, IN, IS. JP. KE, KG. KM, KN. KP,
`KR, K2, LA, LC, LK, LR, LS, LT, LU, LY. MA, MI).
`ME, MG, MK, MN. MW, MX, MY, MZ, NA. NG, N1,
`NO, NZ, OM, PE, PG, PH, PL, PT, no, RS, RU, sc, so,
`SE, SG. SK. SL, SM. ST, SV, SY, TII, TJ. TM, TN. TR.
`TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
`
`(84) Designated States (unless otherwise indicated, flJr everv
`kind of‘regt‘onol protection available): ARIPO (BW, (il I,
`QM, Kn, Ls, MW, MZ, NA, so, st, 32, TZ, UG, ZM,
`4W" Ems“ (AM: Ma BY‘ K0, K3, MD, R“, T"
`TM}, Eluopean (AT, BE, no, CH, CY, CZ, DIE, DK, RE,
`ES, FI. FR. GB, GR, UR, IlU, [I], IS, IT, LT, LU, LV,
`MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM,
`TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, ('iQ, GW,
`ML. MR, NE, SN, TD, TO).
`
`Declarations under Rule 4.] 't':
`
`— as to applicant‘s entitlement to npplrfln‘ and be granted
`rt potent (Ride 4. 1' 7o?»
`
`— as to the applicant's entitlement to claim the priort'tt' of
`tl'e enrl'u‘rt
`t'cat') Rt [e 4.}?
`I
`1‘ W I
`" M '
`(”I")
`Published:
`
`{81) Designated States (mites-5 other-Hiya indicated, fin- everv — without international seat-cl: rem” and to be republished
`kind ofmrtt'onttl protection available): AE, AG, AL, AM,
`“PU” receipt ‘1‘” “(PM ”-100"1' (Rule 433(3))
`A0, AT, AU, AZ, BA, BB, BO, 811, BR, BW, BY, BZ,
`
`(54) Title: MULTIPLE SUPPLY-VOLTAGE POW HR-Ul‘tr DOWN DETECTORS
`
`
`
`
`
`I.-'0
`Network
`
`(57) Abstract: A multiple supply voltage device includes an inputt‘outpul (L‘O) network operative at a first supply voltage, a core
`network coupled to the U0 network and operative at a second supply voltage. and a power-on-eontrol (POC) network coupled to
`the 00 network and the core network. The FCC network is configured to transmit a POC signal to the U0 network and includes
`an adjustable current power uptdown detector configured to detect a power state of the core network, The POC network also in-
`cludes processing circuitry coupled to the adjustable current power nptdown detector and configured to process the power state
`into the FCC signal, and one or more tbedback circuits. For reducing the leakage current while also improving the power-
`upt‘down detection speed, the leodback circuitts] are coupled to die adjustable ctn‘rcnt power tip/down detector and configured to
`provide feedback signals to adjust a current capacity of the adjustable current power upr’down detector,
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.1
`Exhibit 2001, p.1
`
`
`
`wo2010/091105A2|l||||||||||||||||||||||||ll|||||||||||||||||l|||||||||||||||||||||||||||||||||||||l|||||||||||
`
`

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`MULTIPLE SUPPLY-VOLTAGE POWER-UPIDOWN DETECTORS
`
`TECHNICAL FIELD
`
`[0001] The present disclosure is related, in general, to integrated circuit
`
`devices and, more particularly, to power upfdown detectors for multiple supply voltages
`
`devices.
`
`BACKGROUND
`
`[0002] As technology has advanced there has been an increased ability to
`
`include more and more devices and components within integrated circuits.
`
`Semiconductor fabrication techniques have allowed these embedded devices to become
`
`smaller and have lower voltage requirements, while still operating at high—speeds.
`
`However, because these new integrated devices often interface with older technology
`
`devices or legacy products, inpquutput (UO) circuits within the integrated circuit have
`
`remained at higher operating voltages to interface with the higher voltage requirements
`
`of these older systems. Therefore, many newer integrated circuit devices include dual
`
`power supplies: one lower-voltage power supply for the internally operating or core
`
`applications, and a second higher-voltage power supply for the U0 circuits and devices.
`
`|0003] Core devices and applications communicate with operations
`
`outside of the integrated component through the U0 devices.
`
`In order to facilitate
`
`communication between the core and U0 devices, level shifters are employed. Because
`
`the U0 devices are connected to the core devices through level shifters, problems may
`
`OCCur when the core devices are powered-down. Powering down or power collapsing is
`
`a common technique used to save power when no device operations are pending or in
`
`progress. For example, ifthe core network is power collapsed, it is possible that the
`
`level shifters, whether through stray currents or the like, could send a signal to the UO
`
`devices for transmission. The U0 devices assume that the core devices have initiated
`
`this communication, and will, therefore, transmit the erroneous signal into the external
`
`environment.
`
`[0004]
`
`It has been found uscfiil to have the U0 devices in a known state
`
`when the core networks are powered down.
`
`In order to guarantee these known states,
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.2
`Exhibit 2001, p.2
`
`

`

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`
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`
`solutions have included the addition of hardware or software for managing additional
`
`external signals to control the U0 circuitry. By using these external signals, the U0
`
`circuitry can be controlled (e.g., placed in a known state) whenever the core power is
`
`collapsed. However, whether implementing this external signal management system
`
`using hardware or software, a considerable amount of delay is added to the operation of
`
`the integrated device. Although hardware is slightly faster than software controls, ,
`
`hardware solutions may have problems caused by significant additional power leakage
`
`on the [£0 device side.
`
`[0005] One hardware solution currently in use provides power-upfdown
`
`detectors to generate a power-onfoff-eontrol (POC) signal internally. The POC signal
`
`instructs the [10 devices when the core devices are shut down. FIGURE 1
`
`is a circuit
`
`diagram illustrating standard POC system 10 for multiple supply voltage devices. POC
`
`system 10 is made up of three functional blocks: power-upfdown detector 100. signal
`
`amplifier 10], and output stage 102. Power-upfdown detector 100 has PMOS transistor
`
`M1 and NMOS transistors M2 — M3. The gate terminals for each ofMl-M3 are
`
`connected to core power supply 103, ch. When core power supply 103 is power
`
`collapsed, M2 and M3 are switched off while M1 is switched on, pulling up the input
`
`node to amplifier 105 to V130, i.e., U0 power supply 104. A “high” signal is input into
`
`amplifier 105 which inverts the output to a “low” signal.
`
`In output stage 102, the low
`
`signal from amplifier 105 is processed in Output buffer 106 and again inverted to a high
`
`signal for FCC 107. The high signal for POC 10'? is transmitted to the 110 circuitry
`
`indicating that core power supply 103 has been shut down.
`
`[0006] When core power supply 103, ch, is on, M] becomes very weak
`
`and M2 and M3 both switch strongly on, pulling the input node to amplifier 105 to V35,
`
`i.e., core power supply 103. V53 is considered the logical low signal. Therefore,
`
`amplifier 105 inverts it to a high signal which is then processed in output buffer 106 and
`
`inverted again to a low signal. This signal detection process operates acceptably when
`
`either U0 power supply 104 is on and core power supply 103 is power collapsed or
`
`when core power supply 103 is powered-up before U0 power supply 104 is powered-
`
`up. However, when ”0 power supply 104 is powered-up before core power supply 103
`
`powers-up, substantial current leakage may occur in the power upr'down detector 100 or
`
`in the FCC 10.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.3
`Exhibit 2001, p.3
`
`

`

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`
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`
`|0007]
`
`In the situation where L’O power supply 104 is on and core power
`
`supply 103 is off, MI is switched on with M2 and M3 switched off. When core power
`
`supply I03 is then powered up, M2 and M3 switch on, and M1 becomes very weak.
`
`However, before M] can switch completely off, there is a period in which all three
`
`transistors within power upfdown detector 100 are on. Thus, a virtual short is created to
`
`ground causing a significant amount of current to flow from UO power supply 104 to
`
`ground. This “glitch” current consumes unnecessary power.
`
`[0008]
`
`In order to reduce this stray power consumption, one solution may
`
`be adopted to decrease the sizes of transistors M 1 -M3. By reducing the size ofM 1 -M3,
`
`the actual amount of current that can pass through the transistors is physically limited.
`
`However, because the transistors are now smaller, their switching speeds are also
`
`reduced. The reduced switching speed translates into less sensitivity in detecting
`
`power-upldown of core supply voltage 103 or longer processing time for power-
`
`upi’down events.
`
`[0009]
`
`FIGURE 2 is an illustration of diagram 20 presenting the signal
`
`interactions in POC circuit 10 of FIGURE 1. Diagram 20 includes power supply
`
`diagram 21 and POC diagram 22. As L’O power supply 104 is powered up, there is a
`
`steady increase until it reaches V1.0. POC 107 follows U0 power supply 104 as it
`
`powers up to reach the high level. Similarly, when UO power supply 104 maintains
`
`steady at Vm at time 200, POC 107 remains steady at the high signal. When core
`
`power supply 103 begins to power on at time 201 power upfdown detector 100
`
`(FIGURE 1) takes a little time to actually detect this new power level. Once detected, at
`
`time 202, POC 107 is switched to the low value. POC 107 should, thereafter, remain at
`
`the low level until core power supply 103 is power collapsed, between times 203 and
`
`205. Again, because power upfdown detector 100 (FIGURE 1) takes a little time to
`
`actually detect the new power level, POC 10'? remains in the low state until time 204,
`
`when the powering down is actually detected by power upldown detector 100. This
`
`low state time, between time 202 and 204 is referred to as the normal operation region.
`
`Once core power supply 103 is completely off or power collapsed at time 205, the input
`
`to amplifier 105 (FIGURE 1) is again pulled up to the high signal. POC 10? will then
`
`follow L’O power supply 104 as it also powers down between times 206 and 20?.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.4
`Exhibit 2001, p.4
`
`

`

`W0 20101091105
`
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`
`|0010] The leakage current between HO power supply 104 and ground can
`
`be lessened because of the smalier transistor size. Thus, during the time between times
`
`201 and 205 any leakage that occurs is reduced. However, this reduced leakage comes
`
`at the price of faster detection. If POC circuit 10 may include the lower-threshold or
`
`bigger transistors, switching/detecting times would be faster. For example, as core
`
`power supply 103 begins to power up at time 201, the lower-threshold or bigger
`
`transistors of power upr’down detector 100 would detect the power-up at time 208,
`
`instead of time 202. MoreOver when core power supply 103 begins powering down at
`
`time 203, the power upldown detector 100 would detect the power-down at time 209,
`
`instead of time 204. This increase may be represented by the difference between the
`
`time periods of time 202 to 204 vs. time 208 to 209. Therefore, the conventional
`
`solutions still have problems with leakage and switching times.
`
`SUMMARY
`
`[001 1|
`
`Various representative embodiments of the disclosure relate to
`
`integrated devices having multiple supply voltages. Further representative
`
`embodiments of the present disclosure relate to methods for reducing power
`
`consumption in a power onfoff control (POC) network of a multiple supply voltage
`
`device. Additional representative embodiments of the present disclosure relate to
`
`systems for reducing power consumption in a POC network of a multiple supply voltage
`
`device.
`
`[0012] A multiple supply voltage device includes a core network operative
`
`at a first supply voltage and a control network coupled to the core network. The control
`
`network is configured to transmit a control signal. The control network includes an
`
`upfdown ( upi’down) detector configured to detect a power state of the core network.
`
`The control network further includes processing circuitry coupled to the upfdown
`
`detector and is configured to generate the control signal based on the power state. The
`
`control network further includes one or more feedback cirCuits coupled to the upldown
`
`detector. The one or more feedback circuits are configured to provide feedback signals
`
`to adjust a current capacity of said upfdown detector.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.5
`Exhibit 2001, p.5
`
`

`

`W0 2010,1091 105
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`
`[0013| A method for reducing power consumption in a power onloff
`
`control (POC) network ofa multiple supply voltage device includes detecting a power-
`
`on ofa second supply voltage while a first supply voltage is already on, decreasing a
`
`current capacity of a power onfoff detector of the POC network in response to the
`
`power-on detection, detecting a power-down of the second supply voltage while the first
`
`supply voltage is on, and increasing the current capacity of the power onfoff detector in
`
`response to the power-down detection.
`
`[0014] A system for reducing power consumption in a power enfoff control
`
`(POC) network of a multiple supply voltage device includes a means for detecting a
`
`power-on ofa second supply voltage while a first supply voltage is already on. The
`
`system further includes means for decreasing a current capacity of a power onz’off
`
`detector of the POC network responsive to the power-on detection. The system further
`
`includes means for detecting a power-down of the second supply voltage while the first
`
`supply voltage is on, and means for increasing the current capacity of the power onfoff
`
`detector responsive to the power-down detection.
`
`[0015] The foregoing has outlined rather broadly the features and
`
`technical advantages of the present embodiments in order that the detailed description of
`
`the disclosure that follows may be better understood. Additional features and
`
`advantages of the embodiments will be described hereinafter which form the subject of
`
`the claims ofthe disclosure.
`
`It should be appreciated by those skilled in the art that the
`
`conception and specific embodiments disclosed may be readily utilized as a basis for
`
`modifying or designing other structures for carrying out the same purposes ofthe
`
`present disclosure.
`
`It should also be realized by those skilled in the art that such
`
`equivalent constructions do not depart from the spirit and scope of the disclosure as set
`
`forth in the appended claims. The novel features which are believed to be characteristic
`
`of the disclosure, both as to its organization and method of operation, together with
`
`further objects and advantages will be better understood from the following description
`
`when considered in connection with the accompanying figures. It is to be expressly
`
`understood, however, that each of the figures is provided for the purpose of illustration
`
`and description only and is not intended as a definition of the limits of the present
`
`disclosure.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.6
`Exhibit 2001, p.6
`
`

`

`W0 20101091 105
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`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0016]
`
`For a more complete understanding of the present disclosure,
`
`reference is now made to the following descriptions taken in conjunction with the
`
`accompanying drawings.
`
`[0017]
`
`FIGURE 1 is a circuit diagram illustrating a conventional POC
`
`system for multiple supply voltage devices.
`
`[0018]
`
`FIGURE 2 is an illustration ofa diagram presenting the signal
`
`interactions in the POC circuit of FIGURE 1.
`
`[0019]
`
`FIGURE 3A is a block diagram illustrating an integrated circuit
`
`(IC) device having a power on control (POC) network configured according to the
`
`teachings of the present disclosure.
`
`[0020]
`
`FIGURE 33 is a block diagram illustrating a POC network
`
`configured according to the teachings of the present disclosure.
`
`[0021]
`
`FIGURE 4 is a circuit diagram illustrating another POC network
`
`configured according to the teachings of the present disclosure.
`
`[0022]
`
`FIGURE 5 is a circuit diagram illustrating a further POC network
`
`configured according to the teachings ofthe present disclosure.
`
`[0023]
`
`FIGURE 6 is a circuit diagram illustrating still another POC
`
`network configured according to the teachings of the present disclosure.
`
`[0024]
`
`FIGURE 7 is a flowchart illustrating process blocks for
`
`implementing one embodiment according to the teachings ofthe present disclosure.
`
`FIGURE 8 is a diagram illustrating an exemplary wireless communication
`
`system.
`
`DETAILED DESCRIPTION
`
`[0025] Turning now to FIGURE 3A, a block diagram is presented
`
`illustrating an integrated circuit (IC) device 30 having a power on control (POC)
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.7
`Exhibit 2001, p.7
`
`

`

`W0 20101091105
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`
`network 305 configured according to one embodiment of the present disclosure. The 'IC
`
`device 30 is an integrated circuit that includes embedded components powered by
`
`multiple power supplies, such as the V1.0 300 and the ch 30]. TheVIi-o 300 and the
`
`WOW 301 supply several different voltage level power supplies to different components
`
`and networks within the 1C device 30. Two such embedded networks are the lit)
`
`network 302 and the core network 303. The lz’O network 302 operates at a voltage level
`
`provided by the Vm) 300. The Core network 303 operates at a voltage level provided by
`
`the me 301, which is uSually a lower voltage than that provided by the Vpo 300.
`
`Because the HO network 302 and the core network 303 operate at different voltages,
`
`they are coupled together through level shifters 304 for communication. The level
`
`shifters 304 essentially shift the voltage levels of any communications that occur
`
`between the U0 network 302 and the core network 303.
`
`|0026]
`
`POC network 305 senses the status of the core network 303 and
`
`transmits a POC signal to the [KO network 302 and level shifters 304. The POC signal
`
`either turns them on or off. This prevents stray signals received by the U0 network 302
`
`from being mistakenly transmitted to devices or components external to the IC device
`
`30.
`
`[0027]
`
`FIGURE 3B is a block diagram illustrating a POC network 305
`
`configured according to one embodiment of the present disclosure. The POC network
`
`305 includes a power upfdown detector 306, processing circuitry 307, and feedback
`
`network 310. The processing circuitry 307 is made up ofa signal processor 308 and an
`
`output buffer 309. When the VH0 300 is on and the Venn, 301 is off, the power upfdown
`
`detector 306 provides a detection signal to the signal processor 308, which processes the
`
`detection signal and transmits the processed signal to the output buffer 309. The output
`
`buffer 309 then conditions the processed signal into a POC signal 3] I, which is then
`
`transmitted to an HO network 302. Along the way, a feedback network 310 receives
`
`feedback from the signal processor 308 and feeds that signal back to the power
`
`upldown detector 306. The power upldown detector 306 uses the feedback signal to
`
`adjust its current capacity. While the Wm 30] is in an off or low state, the feedback
`
`signal allows the power upr’down detector 306 to select a maximum current capacity.
`
`This maximum current capacity state makes the power up!down detector 306 more
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.8
`Exhibit 2001, p.8
`
`

`

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`sensitive to detecting when the ch 301 either powers-up or powers-down, or both,
`
`depending on the circuit configuration of the power upfdown detector 306.
`
`[0028] When the more 301 powers-up while the Vim 300 is on, the power
`
`upi’down detector 306 detects the power-up and changes the value of the detection signal
`
`transmitted to the signal processor 308. The process detection signal is then conditioned
`
`by the output buffer 309 into the changed POC signal 3] l and transmitted to the HO
`
`network 302. With the changing signals being processed through the signal processing
`
`circuitry 307, the feedback network 310 receives the new feedback signal that, when
`
`input into power the uptdown detector 306, causes the current capacity within the power
`
`upfdown detector 306 to decrease. This decrease in current capacity will limit and
`
`reduce the amount of leakage current that may be dissipated through the power
`
`upi’down detector 306 because of its connections to the Vm 300 and the Wm 30].
`
`[0029]
`
`FIGURE 4 is a circuit diagram illustrating a POC network 40
`
`configured according to one embodiment of the present disclosure. The POC network
`
`40 has similar processing regions as the POC network 305 (FIGURE 3A and SB), i.e., a
`
`power upfdown detector 306, a signal processor 308, an output buffer 309, and a
`
`feedback network 310. The POC network 40 also generates a POC signal 3] l and is
`
`coupled to a Vm 300 and a Vcom 30!. As shown in the embodiment illustrated in
`
`FIGURE 4, the power upfdown detector 306 comprises multipie transistors M4-M7
`
`coupled in series together. Each gate of the transistors M4-M'? is coupled to the ch
`
`30] , while the source terminal of the transistor M4 is coupled to the VH0 300. The
`
`transistors M4 and M5 are p-type transistors and the transistors M6 and M? are n-type
`
`transistors. Therefore, when the me 301 is off, i.e., in a low state, the transistors M4
`
`and M5 are switched on, while the transistors M6 and M? are switched off.
`
`[0030]
`
`In contrast, when the ch 301 is on, i.e., in a high state, transistors
`
`M4 and M5 become very weak while transistors M6 and M7 are strongly switched on.
`
`M6 and M7 turning on pulls the voltage ofthe input to inverting amplifier to V53, which
`
`is a logical low signal compared with Vm. V35 is designed as the logical low signal and
`
`may comprise ground, 0 V, or some other selected voltage level that represents the
`
`logical low symbol. Thus, when the Wm 30] is off, the transistors M4 and M5 pull up
`
`the voltage level at the input to an inverting amplifier 400 to the Vm 300. Therefore,
`
`the input to the inverting amplifier 400 is high when the ch 301 is off and low when
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.9
`Exhibit 2001, p.9
`
`

`

`W0 20101091105
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`
`the Wm 30] is on. The inverting amplifier 400 then amplifies and inverts the detection
`
`signal before transmitting it to the inverting buffer 401 for conditioning and inverting
`
`for the POC signal 31 l.
`
`[003l] The feedback network 310 comprises a transistor M8 connected in
`
`parallel to the transistor M4. The transistor M8 is also configured as a p-type transistor,
`
`such that when the feedback signai from the inverting amplifier 400 is high, the
`
`transistor M8 is switched off, and when the feed back signal is low, the transistor M8 is
`
`switched on. Thus, when the ch 301 is off, producing a high detection signal, the
`
`inverting amplifier 400 inverts that signal to a logic low which causes the transistor M8
`
`to switch on. As the ch 301 is powered-on, the detection signal changes to a logic
`
`low, which changes the feedback signal from the inverting amplifier 400 to a logic high,
`
`which, in turn, turns the transistor M8 off. While the transistor M8 is off, the power
`
`upldown detector 306 has a decreased current capacity, i.e.. smaller current will flow
`
`through the transistor M8 because of the amplified low signal. The voltage level caused
`
`by the ch 301 on the gate terminals of M4 and M5 could in some glitch or stray signal
`
`situations, cause leakage through M4 and M5. Because the feedback signal for the
`
`transistor M8 is received from the inverting amplifier 400, when the ch 301 powers-
`
`down, the feedback signal will switch quickly from a logic high to a logic low, which
`
`will then switch the transistor M8 on. Thus, in the circuit configuration depicted in
`
`FIGURE 4, the power upfdown detector 40 will detect the Vcure 301 powering down
`
`more quickly than the existing POC networks.
`
`[0032]
`
`FIGURE 5 is a circuit diagram illustrating a POC network 50
`
`configured according to one embodiment of the present disclosure. The POC network
`
`50 comprises multiple transistors M4-M? in the power upfdown detector 306 coupled
`
`together in a fashion similar to the POC network 40 (FIGURE 4) with each gate coupled
`
`to a ch 301, and the source terminal of the transistor M4 coupled to a Vlgo 300. A
`
`signal processor 308 comprises an inverting amplifier 400, and an output buffer 309
`
`includes an inverting buffer 401. The POC network 50 generates a POC signal 31 I,
`
`which will be transmitted to the U0 network to which the POC network 50 is coupled.
`
`In the POC network 50, a feedback network 310 is configured with the transistors M9
`
`and M10 coupled in parallel with the transistor M7. The transistors M6. MT, M10, are
`
`the same type, n-type or can be low—threshold n-type transistors to speed up the power-
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.10
`Exhibit 2001, p.10
`
`

`

`W0 20101091105
`
`PCTIU52010f023081
`
`10
`
`on detection. The transistor M9 receives its feedback signal from the output of the
`
`inverting buffer 401, while the gate of the transistor M 10 is connected to the ch 301.
`
`[0033]
`
`In operation, when the Vm) 300 is on and the ch 301 is off, the
`
`inverting amplifier 400 receives a logic high signal by virtue of the VUO 300, which,
`
`when amplified and inverted by the inverting amplifier 400 and then conditioned and
`
`inverted by the inverting buffer 401, provides a logic high feedback signal. This high
`
`signal would normally switch M9 in the feedback network 310 on. However, because
`
`M6, M7, and M10 are all off, there is no channel formation within the transistor M9 to
`
`switch it on. When the ch 301 powers on, M4 and M5 become very weak, while M6,
`
`MT, and M10 switch on, which immediately causes M9 to switch on because its gate is
`
`already connected to a logic high input. M6 and M? switching on pulls the input to the
`
`inverting amplifier 400 down to a logical low signal, i.e., V35. The low detection signal
`
`input to the inverting amplifier 400 is amplified and inverted and then conditioned and
`
`inverted again at the inverting buffer 401. Once the inverting buffer 401 outputs a low
`
`signal, the feedback of that low to the transistor M9 will switch M9 off, which, because
`
`switching M9 off stops the channel formation in the transistor M 10, causes the transistor
`
`M10 to also switch off. Thus, the configuration of the POC network 50, as illustrated in
`
`FIGURE 5, operates to detect the ch 301 powering on faster than the existing POC
`
`networks, while still reducing the amount ofleakage current while the Wm 30] is on.
`
`The feedback signal used by the transistor M9 allows the power upfdown detector 306
`
`to adjust its current capacity, which reduces the leakage current at the same time as the
`
`detection speed is improved.
`
`[0034]
`
`FIGURE 6 is a circuit diagram illustrating a POC network 60
`
`configured according to one embodiment of the present disclosure. The POC network
`
`60 includes a feedback network 310 configured according to the circuit arrangements of
`
`both the POC network 40 (FIGURE 4) and the POC network 50 (FIGURE 5). As such,
`
`multiple transistors M4-M7 make up the power upfdown detector 306. The feedback
`
`network 310 includes transistor M8. coupled in parallel to the transistor M4, and the
`
`transistors M9 and M10, coupled in parallel with the transistor MT. The detection
`
`signal from the power upi’down detector 306 provides input to an inverting amplifier
`
`400 ofa signal processor 308, which amplifies and inverts the detection signal for input
`
`to an inverting buffer 401 of an output buffer 309. The conditioned and inverted POC
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.11
`Exhibit 2001, p.11
`
`

`

`W0 20100391 105
`
`PCTIU52010f023081
`
`ll
`
`signal 31 I is then transmitted to the appropriate U0 and level shifter network of the
`
`system. The feedback transistor M8 obtains its feedback signal from the output of the
`
`inverting amplifier 400, while the feedback transistor M9 obtains its feedback signal
`
`from the output of the inverting buffer 401. Using these feedback signals, as described
`
`with respect to the POC network 40 (FIGURE 4) and the POC network 50 (FIGURE 5),
`
`the POC network 60 is able to increase the speed that the Vcom 301 is quickly detected
`
`both in thc power-on and power-off stages. At the same time, because the feedback
`
`network 310 provides the capability of the POC network 60 to adjust the current
`
`capacity of the power upfdown detector 306, the unwanted leakage current can also be
`
`reduced during the me 30] normal operation periods.
`
`[0035]
`
`It should be noted that each of the embodiments described with
`
`respect to the POC network 40 (FIGURE 4), the POC network 50 (FIGURE 5), and the
`
`POC network 60 (FIGURE 6) has its own advantages. For example, the POC network
`
`50 (FIGURE 5) is able to have a considerably improved performance characteristic with
`
`the addition of very small thin—oxide circuitry to the overall silicon. Thus, each of the
`
`illustrated embodiments, as well as the various additional andfor alternative
`
`embodiments ofthe present disclosure represent improvements over the existing
`
`systems and methods.
`
`[0036]
`
`FIGURE 7 is a flowchart illustrating process blocks for
`
`implementing one embodiment of the present disclosure.
`
`In block 700, a power-on of a
`
`second supply voltage is detected while a first supply voltage is already on. At block
`
`70] a current capacity of a power onfoff detector of the POC network is decreased
`
`responsive to the power-0n detection. At block T02 a power—down of the second supply
`
`voltage is detected while the first supply voltage is on. At block 3’03 the current
`
`capacity of the power onfoff detector is increased responsive to the power-down
`
`detection.
`
`[0037]
`
`Figure 8 is a diagram illustrating an exemplary wireless communication
`
`system.
`
`In some embodiments, a system 800 includes multiple remote units 820—824
`
`and multiple base stations 850-852.
`
`It can be recognized that typical wireless
`
`communication systems may have many more remote units and base stations. The
`
`remote units 820-824 include multiple semiconductor devices 830-834 having power
`
`detection, as discussed above. Figure 8 shows a forward link signals 880 from the base
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. V. Qualcomm Incorporated
`IPR2018-01316
`IPR2018-01316
`Exhibit 2001, p.12
`Exhibit 2001, p.12
`
`

`

`W0 2010,1091 105
`
`PCTI‘USZOI 0f023081
`
`12
`
`stations 850-852 and the remote units 820-824 and a reverse link signals 890 from the
`
`remote units 820-824 to the base stations 850-852.
`
`[0038]
`
`In other embodiments, Figure 8 the remote unit 820 is shown as a
`
`mobile telephone, the remote unit 822 is shown as a portable computer, and the remote
`
`unit 824 is shown as a fixed location remote unit in a wireless local loop system. For
`
`example, the remote units may be mobile phones, hand-held personal communication
`
`systems (PCS) units, portable