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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Apple Inc.
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-01315
`Patent 8,063,674
`______________________
`
`PRELIMINARY PATENT OWNER RESPONSE TO PETITION FOR
`INTER PARTES REVIEW PURSUANT TO 37 C.F.R. § 42.107
`
`
`
`
`
`

`

`TABLE OF CONTENTS
`INTRODUCTION ......................................................................................... 1 
`I. 
`II.  THE ‘674 PATENT AND ITS PROSECUTION HISTORY .................... 2 
`A.  Overview of the ‘674 Patent ............................................................... 2 
`B. 
`Prosecution History of the ’674 Patent .............................................. 6 
`III.  OVERVIEW OF THE CITED REFERENCES ......................................... 9 
`A.  Overview of Steinacker ....................................................................... 9 
`B.  Overview of Doyle ............................................................................. 11 
`C.  Overview of Park ............................................................................... 13 
`D.  Overview of Majcherczak ................................................................. 15 
`IV.  GROUND 1 OF THE PETITION SHOULD BE DENIED BECAUSE
`
`THE PETITIONER HAS FAILED TO DEMONSTRATE A
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`MOTIVATION TO COMBINE STEINACKER, DOYLE AND PARK ...
`
` ....................................................................................................................... 16 
`The Proposed Combination of Steinacker, Doyle and Park is
`A. 
`
`Based On Impermissible Hindsight Reconstruction ...................... 16 
`B. 
`Park Teaches Away from the Petitioner’s Hypothetical
`
`Combination ....................................................................................... 24 
`C. 
`The POSA Would Not Be Motivated to Combine Steinacker,
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`Doyle and Park Because of the Disadvantages That Would Result
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`from the Combination ....................................................................... 25 
`THE BOARD SHOULD EXERCISE ITS DISCRETION UNDER
`V. 
`35 U.S.C. § 325(d) TO DENY GROUNDS 2a AND 2b BECAUSE THE
`
`ALLEGED AAPA AND MAJCHERCZAK WERE PREVIOUSLY
`
`CONSIDERED DURING PROSECUTION ............................................. 27 
`
`VI.  THE BOARD SHOULD DENY GROUNDS 2a AND 2b BECAUSE
`
`INTER PARTES REVIEW CANNOT PROPERLY BE BASED ON
`
`AAPA ............................................................................................................ 34 
`VII.  CONCLUSION ............................................................................................ 36 
`
`
`

`

`I.
`
`
`INTRODUCTION
`Apple Inc. (“Apple” or “Petitioner”) seeks review of claims 1, 2, and 5-7 of
`
`U.S. Patent No. 8,063,674 (the “’674 Patent”) based on obviousness grounds.1 In
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`determining whether to institute inter partes review, the Board must resolve whether
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`a person of ordinary skill in the art (POSA) would have found it obvious to combine
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`prior-art elements in the manner proposed by Apple. For this inquiry, the Federal
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`Circuit has cautioned that “[t]he inventor’s own path itself never leads to a
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`conclusion of obviousness; that is hindsight.” Otsuka Pharm. Co. v. Sandoz, Inc.,
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`678 F.3d 1280, 1296 (Fed. Cir. 2012). Thus, it is improper to rely on the patent itself
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`as a roadmap for combining prior-art elements “like separate pieces of a simple
`
`jigsaw puzzle.” InTouch Techs., Inc. v. VGO Commc’ns, Inc., 751 F.3d 1327, 1349
`
`(Fed. Cir. 2014).
`
`
`
`Yet that is exactly what Apple does in its Petition. In Ground 1, Apple asserts
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`that the challenged claims are obvious over the combination of Steinacker, Doyle,
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`and Park. But the POSA would never consider implementing the voltage level
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`detector of Steinacker’s analog/digital mixed signal circuit with the interface circuit
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`of Doyle, as Apple proposes. Doyle’s circuit is designed to provide an interface
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`between a TTL circuit and a CMOS circuit. The design and purpose of Doyle’s
`
`
`1 Apple seeks review of claims 8, 9, 12, 13 and 16-22 of the ’674 Patent over
`the same combination of references in IPR2018-01316.
`
`
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`1
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`

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`TTL/CMOS interface circuit is entirely unrelated to the analog/digital mixed signal
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`circuit of Steinacker, and the POSA would not combine the circuits absent a desire
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`to recreate the circuits disclosed in the ’674 Patent. Likewise, the POSA would not
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`combine Park with the hypothetical Steinacker/Doyle circuit to reduce leakage
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`current (Petition at 22) because neither Steinacker nor Doyle recognizes any
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`problem relating to leakage power consumption. Only impermissible hindsight
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`would lead one to make this combination.
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`
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`Apple’s Grounds 2a and 2b based on the alleged AAPA and Majcherczak are
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`also deficient. These grounds are nothing more than a rehash of art that the Office
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`already considered during prosecution, and the Board should deny them on this basis
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`alone.
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`
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`Because Apple’s petition fails to establish a reasonable likelihood of
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`prevailing on any claim, the Board should decline to institute trial on the ’674 Patent.
`
`II. THE ‘674 PATENT AND ITS PROSECUTION HISTORY
`A. Overview of the ’674 Patent
`U.S. Patent No. 8,068,674 (“the ’674 Patent”), titled “Multiple Supply-
`
`
`
`Voltage Power-Up/Down Detectors,” generally relates to power-up/down detectors.
`
`The ’674 Patent issued on November 22, 2011, from an application filed on February
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`4, 2009.
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`2
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`Modern integrated circuits include multiple networks operating with different
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`supply voltages (e.g., V1 and V2). For example, a lower voltage V1 may be used
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`for a core logic network, while a higher voltage V2 may be used for an input/output
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`(“I/O”) network. Multiple independent supply voltages provide flexibility in
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`operating different networks independently, such as being able to turn off parts of
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`the circuit that are not needed (e.g., sleep mode), which results in significant power
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`savings. Also, because new integrated circuit devices often interface with older
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`technology, “input/output (I/O) circuits within the integrated circuit have remained
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`at higher operating voltages to interface with the higher voltage requirements of
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`these older systems.” Ex. 1001 (’674 Patent) at 1:22-25.
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`
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`The Background section of the ’674 Patent recognizes that many previous
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`power up/down detectors suffered from problems. For example, the ’674 Patent
`
`explains:
`
`Core devices and applications communicate with operations outside
`of the integrated component through the I/O devices. In order to
`facilitate communication between the core and I/O devices, level
`shifters are employed. Because the I/O devices are connected to the
`core devices through level shifters, problems may occur when the core
`devices are powered-down. Powering down or power collapsing is a
`common technique used to save power when no device operations are
`pending or in progress. For example, if the core network is power
`collapsed, it is possible that the lever shifters, whether through stray
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`
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`3
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`

`

`current or the like, could send a signal to the I/O devices for
`transmission. The I/O devices assume that the core devices have
`initiated this communication, and will, therefore, transmit the erroneous
`signal into the external environment.
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`Id. at 1:26-40. As another example, the Background section of the ’674 Patent
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`describes the problem of “glitch” current caused by slow detection speeds in a
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`previous power up/detector design shown in Fig. 1:
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`In the situation where I/O power supply 104 is on and core power
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`supply 103 is off, M1 is switched on with M2 and M3 switched off.
`When core power supply 103 is then powered up, M2 and M3 switch
`on, and M1 becomes very weak. However, before M1 can switch
`completely off, there is a period in which all three transistors within
`power up/down detector 100 are on. Thus, a virtual short is created to
`ground causing a significant amount of current to flow from I/O power
`supply 104 to ground. This “glitch” current consumes unnecessary
`power.
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`Id. at 2:21-30.
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`
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`The ’674 Patent teaches using feedback to increase the speed of the power-
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`up/down detection while simultaneously reducing power consumption. An example
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`implementation of that feedback is shown below in Figure 4:
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`4
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`Id. at Fig. 4. During a power-up transition (i.e., when Vcore goes from low to high),
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`M8 transitions from being on to off. When M8 is off, the current capacity of the
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`power up/down detector is decreased. See id. at 6:12-18. During a power-down
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`transition (i.e., when Vcore goes from high to low), M8 transitions from off to on.
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`When M8 is on, the “power up/down detector 40 will detect the Vcore 301 powering
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`down more quickly than the existing POC networks.” Id. at 6:23-28. Thus, the
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`feedback technique disclosed in the ’674 Patent provides fast and energy efficient
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`power up/down detection.
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`
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`Claim 1 of the ‘674 Patent is exemplary:
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`1. A multiple supply voltage device comprising:
`a core network operative at a first supply voltage; and
`a control network coupled to said core network wherein said control
`network is configured to transmit a control signal, said control
`network comprising: an up/down (up/down) detector configured to
`5
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`

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`detect a power state of said core network; processing circuitry coupled
`to said up/down detector and configured to generate said control
`signal based on said power state;
`one or more feedback circuits coupled to said up/down detector, said
`one or more feedback circuits configured to provide feedback signals
`to adjust a current capacity of said up/down detector;
`at least one first transistor coupled to a second supply voltage, the at
`least one more first transistor being configured to switch on when said
`first supply voltage is powered down and to switch off when said first
`supply voltage is powered on;
`at least one second transistor coupled in series with the at least one first
`transistor and coupled to said first supply voltage, the at least one
`second transistor being configured to switch on when said first supply
`voltage is powered on and to switch off when said first supply voltage
`is powered down;
`at least one third transistor coupled in series between the at least one
`first transistor and the at least one second transistor.
`
`B.
`Prosecution History of the ’674 Patent
`U.S. Patent Application No. 12/365,559, which later issued as the ’674 Patent,
`
`
`
`was filed on February 4, 2009. See Ex. 1002 at 226-72. On February 3, 2010,
`
`Qualcomm filed a Patent Cooperation Treaty (PCT) application claiming priority to
`
`the previously filed U.S. application. Ex. 2001 at 1. The description, figures, and
`
`claims of the PCT application were the same as the as-filed U.S. application.
`
`Compare Ex. 1002 at 226-54 with Ex. 2001 at 2-29.
`
`
`
`On August 5, 2010, the International Searching Authority issued an
`
`International Search Report (ISR) and Written Opinion for the PCT application. Ex.
`
`1002 at 170-87. Among other references, the ISR cited the Majcherczak reference
`
`
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`6
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`

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`(Ex. 1008) and stated that it is a “document of particular relevance; the claimed
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`invention cannot be considered novel or cannot be considered to involve an inventive
`
`step when the document is taken alone.” Ex. 1002 at 171. The Written Opinion
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`(referring to Majcherczak as “Document D2”) went further and provided a detailed
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`description of how Majcherczak allegedly meets the claim limitations:
`
`
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`Id. at 184-86. The Written Opinion concluded that “[t]he features of claims 1, 10,
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`20 and 26 are . . . anticipated by [Majcherczak].” Id. at 185.
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`
`
`On September 8, 2010, prior to the start of substantive examination of the U.S.
`
`application, Qualcomm filed the ISR and Written Opinion with the USPTO, listing
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`both on an IDS along with the documents cited in the ISR. Id. at 166-68.
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`
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`During prosecution of the U.S. application, the examiner issued two office
`
`actions. Id. at 102-14, 142-54. Following the issuance of the first office action, the
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`7
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`examiner entered a “List of References cited by applicant and considered by
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`examiner” into the record. Id. at 125-26. In the document, the examiner provided
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`his initials by the Majcherczak reference, indicating that he considered it:
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`Id. at 125. In the same document, the examiner lined through the ISR and Written
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`Opinion of the International Searching Authority, indicating that the citations to
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`these documents in the IDS were “not in conformance and not considered”:
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`
`
`
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`Id. at 126.
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`
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`Prosecution progressed, and the examiner eventually issued a first of two
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`Notices of Allowance. Id. at 64-73. Recognizing that the examiner had not yet
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`considered the ISR and Written Opinion, Qualcomm filed a Request for Continued
`
`Examination (RCE) to withdraw the allowed application from issue. Id. at 41-48.
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`With the RCE, Qualcomm re-filed the ISR and Written Opinion and also filed a new
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`8
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`

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`IDS listing both. Id. The examiner subsequently issued the second Notice of
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`Allowance (id. at 16-25) along with a “List of References cited by applicant and
`
`considered by examiner” indicating his consideration of the ISR and Written
`
`Opinions:
`
`Id. at 30.
`
`
`
`III. OVERVIEW OF THE CITED REFERENCES
`A. Overview of Steinacker
`U.S. Patent No. 7,279,943 (“Steinacker”), titled “Circuit Arrangement
`
`
`
`Receiving Different Supply Voltages,” generally relates to a “mixed signal” circuit
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`that includes at least one analog circuit and at least one digital circuit that operate at
`
`two different supply voltages. Steinacker issued on October 9, 2007, from an
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`application filed on October 12, 2005.
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`
`
`Steinacker explains that “[t]he invention is based on the problem of providing
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`a circuit arrangement having at least two circuit blocks operating at different supply
`
`voltages which is able to ensure reliable operation of the circuit arrangement
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`regardless of turn-on profiles for the different supply voltages in the circuit blocks.”
`
`Ex. 1005 (Steinacker) at 2:14-19. An example of Steinacker’s circuit arrangement
`
`is set forth in Figure 1 below.
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`
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`9
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`

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`
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`Figure 1 of Steinacker (above) shows a first supply voltage domain 1.1 that
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`supplies a first circuit block 2 with a first supply voltage, and second supply voltage
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`domain 1.2 that supplies a second circuit block 3 (and possible a third circuit block
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`10) with a second supply voltage. Id. at 4:5-12. The basic concept behind
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`Steinacker’s design is that “the second circuit block is deactivated when the first
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`supply voltage is still too low in order to ensure safe operation of the first circuit
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`block.” Id. at 2:35-38. This is accomplished using a voltage level detector 5 that
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`detects the lower first supply voltage and sends a control signal to a voltage level
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`shifting unit 4, causing the voltage level shifting unit 4 to send a deactivation signal
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`to the second circuit block 3. Id. at 4:56-5:3. “The second circuit block 3 is shut
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`
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`10
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`

`

`down if the first supply voltage is too low to ensure the operation of the respectively
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`supplied logic gates.” Id. at 5:1-3.
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`
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`Steinacker provides little detail regarding the makeup of the voltage level
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`detector 5 shown in Figure 1, stating only that “[i]n the illustration, the voltage level
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`detector 5 is in the form of a Schmitt trigger with an inverting output,” and that “it
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`is likewise conceivable for the voltage level detector 5 to be in the form of an inverter
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`circuit, a comparator circuit or comparable circuits.” Id. at 4:49-53.
`
`B. Overview of Doyle
`U.S. Patent No. 4,717,836 (“Doyle”), titled “CMOS Input Level Shifting
`
`
`
`Circuit with Temperature-Compensating N-Channel Field Effect Transistor
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`Structure,” generally relates to an interface between a TTL circuit and a CMOS
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`circuit. Doyle issued on January 5, 1988, from an application filed on
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`February 4, 1986.
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`
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`Dolye describes certain objects of “the invention” including “to provide a
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`CMOS inverter circuit having a trip point that is relatively stable with respect to
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`temperature and/or to certain CMOS manufacturing process parameters,” and “to
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`provide a stable TTL compatible input circuit in a CMOS integrated circuit.”
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`Ex. 1006 (Doyle) at 2:37-43. An example of Doyle’s TTL compatible input circuit
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`is shown in Figure 2 below.
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`
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`11
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`

`

`
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`Id. at Fig. 2.
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`
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`Doyle teaches a CMOS input level shifting circuit with a temperature-
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`compensating NFET structure. This is accomplished, as shown in Figure 2, by
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`adding a resistor “R” in series between the source terminal of the bottom NMOS
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`transistor 16 and ground. Id. at 5:67-6:4; 2:48-56 (“the invention provides a self-
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`compensating MOS circuit wherein a series resistance that comprise an extension of
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`the region in which the source and drain regions of a MOS field effect transistor
`
`(MOSFET) are diffused provides effective compensation of the drain current of the
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`field effect transistor with respect to the temperature of the circuit and also with
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`respect to variations in MOS manufacturing parameters”). “The described circuit
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`provides a TTL-compatible CMOS input circuit that provides effective, inexpensive
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`high speed interfacing to worst case applied TTL levels despite wide ranges in the
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`
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`12
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`

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`P-channel MOS threshold voltages, N-channel MOS threshold voltages and despite
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`wide variations in temperature.” Id. at 3:22-27.
`
`C. Overview of Park
`The Park reference is a 2006 IEEE article by Jun Cheol Park and Vincent J.
`
`
`
`Mooney III, titled “Sleepy Stack Leakage Reduction.” Park generally relates to a
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`CMOS circuit structure for reducing leakage power consumption, which the authors
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`refer to as a “sleepy stack” structure.
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`
`
`Park claims that their “sleepy stack” CMOS circuit structure provides a
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`“remedy for static power consumption” existing in prior designs. See Ex. 1007 (Park)
`
`at 1. Specifically, Park’s “sleepy stack” structure combines and improves upon “two
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`major prior approaches, the sleep transistor technique and the forced stack technique.”
`
`Id. Fig. 1 of Park (reproduced below) illustrates the previous “forced stack” and
`
`“sleep transistor” techniques that its new “sleepy stack” structure allegedly improves
`
`upon.
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`Id.
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`13
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`

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`
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`With reference to the “forced stack technique” shown above in Fig. 1, Park
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`explains that its new “sleepy stack” design “can achieve more power savings than
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`the forced stack technique,” and more particularly can achieve an improvement of
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`“up to two orders of magnitude leakage power reduction compared to the forced
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`stack.” Id. at 1-2. An example of Park’s “sleepy stack” implemented in an inverter
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`is illustrated in Fig. 2, reproduced below.
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`
`
`Id. at 3.
`
`
`
`
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`As shown in Fig. 2 (above), Park’s “sleepy stack technique has a structure
`
`merging the forced stack technique and the sleep transistor technique,” where “sleep
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`transistors are added in parallel to one of the transistors in each set of two stacked
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`transistors.” Id. Park explains, “The sleepy stack technique has a combined
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`structure of the forced stack technique and the sleep transistor technique. However,
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`unlike the sleep transistor technique, the sleepy stack technique retains exact logic
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`14
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`

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`state when in sleep mode; furthermore, unlike the forced stack technique, the sleepy
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`stack technique can utilize high-Vth transistors without 5x (or greater) delay penalties.
`
`Therefore, far better than any prior approach known to the authors of this paper, the
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`sleepy stack technique can achieve ultra-low leakage power consumption while
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`saving state.” Id. at 2.
`
`D. Overview of Majcherczak
`U.S. Patent Application No. 2002/0163364 (“Majcherczak”), titled “Power
`
`
`
`Supply Detection Device,” relates generally to a device that detects the drop in the
`
`supply voltage of the core of an integrated circuit. Apple’s Petition relies on the
`
`power supply detection device of Majcherczak Fig. 2:
`
`
`
`Ex. 1008 (Majcherczak) at Fig. 2.
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`15
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`

`
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`The power supply detection device of Fig. 2 is configured to be used with an
`
`integrated circuit having two power supply voltages. In the above figure, the core
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`supply voltage Vdd “is for a core of the integrated circuit,” and the interface supply
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`voltage Vdd3 “is a voltage greater than the power supply voltage for the core, and is
`
`applied to external interfaces of the integrated circuit and to input/output interface
`
`circuits within the integrated circuit.” Id. at ¶ 0001. The embodiment of Fig. 2
`
`includes a power supply stage E2, an input stage E1 that receives the core supply
`
`voltage Vdd, and an output stage E3. Id. at ¶¶ 0025-26, 0037. The output stage E3
`
`includes an inverter IV powered by the interface supply voltage Vdd3. Id. at ¶ 0037.
`
`The output stage E3 further includes “a pull-down transistor M6 for pulling the
`
`output node Nin of the inverter of the input stage to the interface power supply
`
`voltage Vdd3. This pull-down transistor M6 is typically a P-type MOS transistor . . . .”
`
`Id.
`
`IV. GROUND 1 OF THE PETITION SHOULD BE DENIED BECAUSE
`THE PETITIONER HAS FAILED TO DEMONSTRATE A
`MOTIVATION TO COMBINE STEINACKER, DOYLE AND PARK
`A. The Proposed Combination of Steinacker, Doyle and Park
`is Based On Impermissible Hindsight Reconstruction
`Ground 1 of the petition is a textbook example of impermissible hindsight
`
`reconstruction. Instead of starting with a relevant primary reference and explaining
`
`why the person of ordinary skill in the art would have been motivated to modify that
`
`reference to derive the claimed invention, the Petitioner pieces together a
`
`
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`16
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`

`

`hypothetical “prior art” circuit from
`
`three entirely unrelated references.
`
`Unsurprisingly, the Petitioner fails to provide an adequate explanation, absent
`
`impermissible hindsight reconstruction, why the POSA would have been motivated
`
`to combine these references.
`
`Independent claim 1 of the ’674 Patent, at issue in Ground 1 of the petition,
`
`claims a very specific invention, reciting a specific circuit used for a specific purpose
`
`in an up/down detector of a multiple supply voltage device. Because of the
`
`specificity of the claims, Apple is not able to identify a single prior art reference that
`
`teaches anything remotely similar. In fact, none of the references applied in
`
`Ground 1 discloses an up/down detector, let alone the specific circuit application set
`
`forth in the claims.
`
`Because none of the references are relevant to the specific invention recited
`
`in independent claim 1, Ground 1 of the petition must rely on impermissible
`
`hindsight reconstruction in its attempt to show motivation to combine the references
`
`into something resembling the claimed invention. As the Board recently recognized
`
`in Samsung Electronics Co., Ltd. v. Red Rock Analytics, LLC, IPR2018-00557
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`(Paper 18, August 20, 2018), it is impermissible to rely on the patent itself “as a
`
`roadmap for putting what amounts to pieces of a jigsaw puzzle together.” Like the
`
`petitioner in Samsung, Apple relies on the teachings of the ’674 Patent to piece
`
`together the unrelated Steinacker, Doyle and Park references in a jigsaw puzzle-like
`
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`17
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`fashion. This is evident by Apple’s own diagram (reproduced below), which
`
`provides instructions for putting together the pieces of its hypothetical prior art
`
`puzzle from wholly unrelated references.
`
`
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`Petition at 20.
`
`Apple’s contrived diagram (above) combines circuit components from Doyle
`
`and Park, allegedly based on the teachings of Steinacker. Notably, Apple’s
`
`hypothetical circuit does not include a single component from Steinacker, Apple’s
`
`
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`18
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`

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`primary reference, which is not surprising because Steinacker includes almost no
`
`details that are relevant to the specific claim elements of the ’674 Patent.
`
`Steinacker describes a “mixed signal” circuit that includes at least one analog
`
`circuit block and at least one digital circuit block that operate at two different supply
`
`voltages. Ex. 1005 (Steinacker) at 1:18-23. Fig. 1 of Steinacker (reproduced below)
`
`shows an example circuit arrangement with a first (e.g., analog) circuit block 2 in a
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`first supply voltage domain 1.1, and second and third (e.g., digital) circuit blocks 3,
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`10 in a second supply voltage domain 1.2. The circuit arrangement includes a
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`“voltage level detector 5” that is used to detect when the first supply voltage is too
`
`low to ensure the proper operation of the logic gates.
`
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`19
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`Steinacker’s “voltage level detector 5” is not an up/down detector, as recited
`
`in the claims of the ’674 Patent. But, in any case, Steinacker provides almost no
`
`details about the implementation of its “voltage level detector,” stating only that “the
`
`voltage level detector 5 is in the form of a Schmitt trigger with an inverting output,”
`
`and that “it is likewise conceivable for the voltage level detector 5 to be in the form
`
`of an inverter circuit, a comparator circuit or comparable circuits.” Id. at 4:49-53.
`
`Apple uses Steinacker as the foundational reference for its hypothetical combination
`
`based only on this passing disclosure to a “voltage level detector,” which is, at best,
`
`marginally relevant to the teachings of the ’674 Patent. In fact, Steinacker’s lack of
`
`relevance to the claims of the ’674 Patent is demonstrated by the fact that Apple’s
`
`own hypothetical circuit diagram, which it attempts to read on the claims of the ’674
`
`Patent, does not include a single circuit component from Steinacker.
`
`Moreover, the Steinacker reference is directed to a different problem than
`
`the ’674 Patent. Steinacker relates to the generation of a power-on reset signal for
`
`initializing digital circuits in a mixed signal circuit (i.e., an IC with both analog and
`
`digital components), in order to prevent problems where the analog circuitry is
`
`activated/deactivated by the digital circuitry. Steinacker states that “to ensure
`
`reliable operation of the circuit arrangement, a reset signal for the first circuit block
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`[i.e., the digital circuit] therefore cannot appear until after a certain waiting period.”
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`Id. at 2:4-6. Steinacker further explains that “[a] basic concept behind the invention
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`is that the second circuit block is deactivated when the first supply voltage is still
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`too low in order to ensure safe operation of the first circuit block. Incorrect output
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`signals from the first circuit block are thus not processed by the second circuit block.
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`Only when the first supply voltage is above the threshold value is it possible for the
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`second circuit block to be actuated by the first circuit block.” Id. at 2:35-43. At best,
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`Steinacker recognizes the need for a voltage level detector – Steinacker provides no
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`teachings that are relevant to the ’674 Patent, which improves the performance of a
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`power-on-control (POC) circuit.
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`For example, in the ’674 Patent, a feedback circuit is used to improve
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`switching times in a POC circuit. See Section II.A above. By contrast, there is
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`absolutely no indication that Steinacker would care about increased switching times
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`in his level detector. This is evident by the fact that Steinacker provides almost no
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`description of its level detector, which confirms that its performance is not important
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`to Steinacker’s system. With respect to the level detector 5, Steinacker indicates that
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`any type of level detector will do, and thus the POSA would be motivated to simply
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`use a traditional circuit, such as the Schmitt trigger device depicted in Fig. 1. The
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`POSA would have had no reason to modify Steinacker’s level detector to include a
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`specialized feedback design, absent impermissible hindsight reconstruction based on
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`the completely different problems recognized by the ’674 Patent.
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`Further, the Doyle and Park references, which Apple relies on to build its
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`hypothetical circuit, are completely unrelated to the claims of the ’674 Patent. As
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`detailed above in Section III.B., the Doyle reference describes a CMOS-TTL
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`interface from 1986. There is no conceivable reason why the POSA would have
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`looked to a 1986 CMOS-TTL interface as a replacement for Steinacker’s inverter.
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`It is evident that Apple relies on Doyle because its TTL interface looks similar in
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`some ways to the multiple supply POC network described in the ’674 Patent. But
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`Apple has demonstrated no reason to look to Dolye’s CMOS-TTL interface for use
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`in a multiple supply voltage up/down detector, absent a desire to recreate the specific
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`design described and claimed in the ’674 Patent. This is classic hindsight
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`reconstruction, and cannot properly support a finding of obviousness. Otsuka Pharm.
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`Co. v. Sandoz, Inc., 678 F.3d 1280, 1296 (Fed. Cir. 2012) (“[t]he inventor’s own
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`path itself never leads to a conclusion of obviousness; that is hindsight”).
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`Likewise, there would have been no reason for the POSA to look to Park to
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`further modify the teachings of Steinacker, absent improper hindsight reliance on
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`the teachings of the ’674 Patent. Petitioner argues that the POSA would have
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`substituted the “forced stack” transistor layout shown in Fig. 1 of Park for the
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`transistors in Doyle because Park tells us that it would reduce the leakage power
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`consumption of CMOS circuits. Petition at 21-22. But Steinacker does not
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`recognize, much less address, any problem relating to leakage power in its level
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`detector. Nor does Doyle say anything about a need to reduce leakage. Thus, even
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`if the POSA were somehow to use Doyle’s inverter to implement Steinacker’s level
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`detector, there would be no motivation to further modify Doyle’s circuit to improve
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`leakage power consumption because leakage in the level detector is not a concern in
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`Steinacker’s system. It is only through hindsight reliance on the different problems
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`solved by the specific circuit applications described and claimed in the ’674 Patent
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`that the POSA could have combined the references in the jigsaw puzzle-like fashion
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`proposed by Apple.
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`Apple attempts the argumentative equivalent of bait-and-switch by relying on
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`Steinacker, instead of Doyle or Park, as the primary reference in Ground 1 of the
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`petition. Steinacker is, at best, marginally relevant to the general teachings of
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`the ’674 Patent because it relates to a system with circuit blocks operating at different
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`supply voltages; but Steinacker provides almost no details that are relevant to the
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`claims of the ‘674 Patent. Doyle is really Apple’s primary reference, but is from a
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`completely different technology. Because no one would look to the 1986 CMOS-
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`TTL interface in Doyle for an up/down detector, however, Apple attempts to make
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`the reference appear more relevant by relying first on the generic disclosure of an
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`inverting amplifier in Steinacker. But as explained above, Apple presents no
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`legitimate reason, absent impermissible hindsight reconstruction, why the POSA
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`would piece the unrelated Steinacker, Doyle and Park references together into the
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`very specific circuits recited in claims 1, 2 and 5-7 of the ’674 Patent. For at least
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`this reason, Ground 1 should be denied.
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`B.
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`Park Teaches Away from the Petitioner’s Hypothetical
`Combination
`Apple claims that the POSA would be motivated to combine Park’s forced
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`stack technique with the hypothetical Steinacker/Doyle circuit to “improve leakage
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`current.” Petition at 21-22. But even if the POSA would have been motivated to
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`use the teachings of Park to lower leakage current, she would not have done so using
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`the forced stack circuit from Park. Rather, the POSA would have used the superior
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`“sleepy stack” technique that is the focus of Park. See generally Ex. 1007 (Park),
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`titled “Sleepy Stack Leakage Reduction.”
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`As described in Section III.C above, Park’s sleepy stack technique combines
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`and improves upon “two major prior approaches, the sleep transistor technique and
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`the forced stack technique.” Id. at 1. Park explains that its new “sleepy stack” design
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`“can achieve more power savings than the forced stack technique,” and more
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`particularly can achieve an improvement of “up to two orders of magnitude leakage
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`power reduction compared to the forced stack.” Id. at 1-2. “Therefore