IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Chang Kwon, et al.
`In re Patent of:
`8,063,674 Attorney Docket No.: 39521-0053IP1
`U.S. Patent No.:
`November 22, 2011
`
`Issue Date:
`Appl. Serial No.: 12/365,559
`
`Filing Date:
`February 4, 2009
`
`Title:
`MULTIPLE SUPPLY-VOLTAGE POWER-UP/DOWN
`DETECTORS
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 8,063,674 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`TABLE OF CONTENTS
`
`I. 
`
`II. 
`
`REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ............................ 1 
`A.  Grounds for Standing Under 37 C.F.R. § 42.104(a)................................. 1 
`B.  Challenge Under 37 C.F.R. § 42.104(b) and Relief Requested ............... 1 
`SUMMARY OF THE ’674 PATENT ............................................................. 3 
`A.  Brief Description ....................................................................................... 3 
`B.  Summary of the Prosecution History of the ’674 Patent .......................... 8 
`C.  Claim Construction under 37 C.F.R. §§ 42.104(b)(3) .............................. 9 
`1. 
`“processing circuitry” (claim 1) .................................................... 10 
`III.  MANNER OF APPLYING CITED PRIOR ART TO EVERY CLAIM FOR
`WHICH AN IPR IS REQUESTED, THUS ESTABLISHING A
`REASONABLE LIKELIHOOD THAT AT LEAST ONE CLAIM OF THE
`’674 PATENT IS UNPATENTABLE .......................................................... 10 
`A.  [GROUND 1] – Steinacker in view of Doyle and Park Render Claims 1,
`2, and 5-7 Obvious .................................................................................. 11 
`1.  Overview of Steinacker ................................................................. 11 
`2.  Overview of Doyle ........................................................................ 13 
`3.  Overview of Park ........................................................................... 15 
`4. 
`The Combination of Steinacker, Doyle, and Park ........................ 17 
`5.  Motivation to Combine Steinacker, Doyle, and Park ................... 21 
`6. 
`Claim 1 .......................................................................................... 22 
`7. 
`Claim 2 .......................................................................................... 33 
`8. 
`Claim 5 .......................................................................................... 35 
`9. 
`Claim 6 .......................................................................................... 36 
`10.  Claim 7 .......................................................................................... 36 
`B.  [GROUND 2a] – Applicant’s Admitted Prior Art in view of
`Majcherczak Renders Claims 1, 2, 5, and 6 Obvious ............................. 37 
`1.  Overview of AAPA ....................................................................... 37 
`2.  Overview Majcherczak.................................................................. 39 
`3. 
`Combination of AAPA and Majcherczak ..................................... 43 
`4.  Motivation to Combine AAPA and Majcherczak ......................... 45 
`5. 
`Claim 1 .......................................................................................... 46 
`6. 
`Claim 2 .......................................................................................... 57 
`7. 
`Claim 5 .......................................................................................... 59 
`8. 
`Claim 6 .......................................................................................... 61 
`C.  [GROUND 2b] – AAPA, Majcherczak, and Matthews Render Claim 7
`Obvious ................................................................................................... 62 
`
`i
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`IV.  CONCLUSION .............................................................................................. 64 
`V.  MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1) ......................... 64 
`A.  Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1) .............................. 64 
`B.  Related Matters Under 37 C.F.R. § 42.8(b)(2) ....................................... 64 
`C.  Lead And Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) ................... 65 
`D.  Service Information ................................................................................ 65 
`
`
`
`
`
`
`ii
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
`
`
`EXHIBITS
`
`APPLE-1001
`
`U.S. Patent No. 8,063,674 to Kwon et al. (“the ’674 patent”)
`
`APPLE-1002
`
`Excerpts from the Prosecution History of the ’674 Patent (“the
`Prosecution History”)
`
`APPLE-1003
`
`Declaration of Dr. Robert Horst
`
`APPLE-1004
`
`Curriculum Vitae of Dr. Robert Horst
`
`APPLE-1005
`
`U.S. Patent No. 7,279,943 to Steinacker (“Steinacker”)
`
`APPLE-1006
`
`U.S. Patent No. 4,717,836 to Doyle (“Doyle”)
`
`APPLE-1007
`
`Jun Cheol Park and Vincent J. Mooney, Sleepy Stack Leakage
`Reduction, 14 IEEE Transactions On Very Large Scale Integra-
`tion (VLSI) Systems 1251 (2006) (“Park”)
`
`APPLE-1008
`
`U.S. Pat. Appl. Pub. No. 2002/0163364 to Majcherczak et al.
`(“Majcherczak”)
`
`APPLE-1009
`
`U.S. Patent No. 6,646,844 to Matthews (“Matthews”)
`
`APPLE-1010
`
`APPLE-1011
`
`APPLE-1012
`
`G. W. Griffiths, “A Review of Semiconductor Packaging and
`Its Role in Electronics Manufacturing,” 8th IEEE/CHMT Inter-
`national Conference on Electronic Manufacturing Technology
`Symposium (1990)
`
`Wang-Chang Albert Gu, “RF Front-End Modules in Cellular
`Handsets,” 2004 IEEE Compound Semiconductor Integrated
`Circuit Symposium (2005)
`
`Kaushik Roy et al., “Leakage current mechanisms and leakage
`reduction techniques in deep-submicrometer CMOS circuits,”
`91 Proceedings of the IEEE 2, pp. 305-327 (Apr. 2003) (“Roy”)
`
`iii
`
`

`

`APPLE-1013
`
`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`Yangyang Ye et al., “A new technique for standby leakage re-
`duction in high-performance circuits,” 1998 Symposium on
`VLSI Circuits. Digest of Technical Papers (Cat.
`No.98CH36215), Honolulu, HI, USA, 1998, pp. 40-41
`(“Borkar”)
`
`APPLE-1014
`
`U.S. Patent No. 7,049,865 to Parker et al. (“Parker”)
`
`APPLE-1015
`
`Qadeer A. Khan et al., “A Sequence Independent Power-on-Re-
`set Circuit for Multi-Voltage Systems,” 2006 IEEE Interna-
`tional Symposium on Circuits and Systems (Sep. 2006)
`
`APPLE-1016
`
`Declaration of Jacob Munford (with attachments)
`
`
`
`
`iv
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`Apple Inc., (“Petitioner” or “Apple”) petitions for Inter Partes Review
`
`(“IPR”) under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42 of claims 1, 2, and 5-7
`
`(“the Challenged Claims”) of U.S. Patent No. 8,063,674 (“the ’674 patent”). As
`
`explained in this petition, there exists a reasonable likelihood that Apple will pre-
`
`vail with respect to at least one of the Challenged Claims.
`
`The Challenged Claims are unpatentable based on teachings set forth in at
`
`least the references presented in this petition. Apple respectfully submits that an
`
`IPR should be instituted, and that the Challenged Claims should be canceled as un-
`
`patentable.
`
`I.
`
`REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a)
`Apple certifies that the ’674 Patent is available for IPR. The present petition
`
`is being filed within one year of service of a complaint against Apple in ITC inves-
`
`tigation of Certain Mobile Electronic Devices and Radio Frequency and Pro-
`
`cessing Components Thereof (Inv. No. 337-TA-1093); and Qualcomm Inc. v. Ap-
`
`ple Inc., 3:17-CV-02398 (S.D. Cal.).
`
`Apple is not barred or estopped from requesting this review challenging the
`
`Challenged Claims on the below-identified grounds.
`
`B. Challenge Under 37 C.F.R. § 42.104(b) and Relief Re-
`quested
`Apple requests an IPR of the Challenged Claims on the grounds set forth in
`
`1
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`the table shown below, and requests that each of the Challenged Claims be found
`
`unpatentable. An explanation of how the Challenged Claims are unpatentable un-
`
`der the statutory grounds identified below is provided in the form of detailed de-
`
`scription and claim charts that follow, indicating where each element can be found
`
`in the cited prior art, and the relevance of that prior art. Additional explanation and
`
`support for each ground of rejection is set forth in Exhibit APPLE-1003, the Decla-
`
`ration of Dr. Robert Horst (“Expert Declaration”), referenced throughout this Peti-
`
`tion.
`
`Ground
`Ground 1
`
`’674 Patent Claims
`1, 2, 5-7
`
`Ground 2a 1, 2, 5, and 6,
`
`Ground 2b 7
`
`
`
`Basis for Rejection
`§103: Steinacker in view of Doyle and
`Park
`§103: Applicants Admitted Prior Art
`(AAPA) in view of Majcherczak
`§103: AAPA in view of Majcherczak
`and Matthews
`
`Steinacker, Doyle, Park, Majcherczak, and Matthews each qualify as prior
`
`art under 35 U.S.C § 102(b). Specifically, Steinacker (APPLE-1005) is a patent
`
`that was published on October 9, 2007. Doyle (APPLE-1006) is a patent that was
`
`published on January 5, 1988. Park (APPLE-1007) is a paper that was published at
`
`least as early as December, 2006. See generally APPLE-1016 (establishing that
`
`Park was “made accessible and publicly available . . . no later than December 4,
`
`2006”). Majcherczak (APPLE-1008) is a U.S. Patent Application Publication that
`
`2
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`published of November 7, 2002. Matthews (APPLE-1009) is a patent that was
`
`published on November 11, 2003. Thus, each was published more than a year be-
`
`fore the February 4, 2009 earliest proclaimed priority date of the ’674 Patent (i.e.,
`
`the “Critical Date”).
`
`II.
`
`SUMMARY OF THE ’674 PATENT
`A. Brief Description
`Generally, the ’674 patent relates to “power up/down detectors for multiple
`
`supply voltages devices.” APPLE-1001, 1:6-8. In its background, the ’674 Patent
`
`describes that “many newer integrated circuit devices include dual power supplies:
`
`one lower-voltage power supply for the internally operating or core applications,
`
`and a second higher-voltage power supply for the I/O circuits and devices.” Id. at
`
`1:22-25. The “core network” of these newer integrated circuit devices include ad-
`
`vanced circuits (e.g., microprocessors) that are “smaller and have lower voltage re-
`
`quirements, while still operating at high-speeds.” Id. at 1:14-17. In order to fur-
`
`ther reduce power consumption, these core network devices can be powered down
`
`when no device operations are pending or in progress. Id. at 1:29-34.
`
`However, these advanced, lower-voltage core network devices still have to
`
`interface with older, higher-voltage I/O devices. See id. at 1:17-22. Level shifters
`
`can be used to permit communication between circuits operating at different supply
`
`3
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`voltages. Id. at 1:28-29; see also APPLE-1003, ¶ 57. These level shifters effec-
`
`tively translate a logic ‘1’ from approximately the value of the lower supply volt-
`
`age (or a function thereof) to approximately the value of the higher supply voltage
`
`(or a function thereof) and vice versa. APPLE-1003, ¶ 57. As a result, the logic
`
`signals communicated between the core network devices and the I/O network de-
`
`vices are translated into the appropriate voltage levels. Id.
`
`The ’674 Patent identifies a problem that may arise due to this need for com-
`
`munication between core network devices and the I/O network devices:
`
`Because the I/O devices are connected to the core devices through
`level shifters, problems may occur when the core devices are pow-
`ered-down. Powering down or power collapsing is a common tech-
`nique used to save power when no device operations are pending or in
`progress. For example, if the core network is power collapsed, it is
`possible that the level shifters, whether through stray currents or the
`like, could send a signal to the I/O devices for transmission. The I/O
`devices assume that the core devices have initiated this communica-
`tion, and will, therefore, transmit the erroneous signal into the external
`environment.
`APPLE-1001, 1:29-40; see also APPLE-1003, ¶ 58.
`
`To avoid this problem of erroneous communications between the core net-
`
`work devices and the I/O network devices, the ’674 Patent suggests utilizing a
`
`“power-on/off-control (POC)” device. See id. at 1:41-57. A POC device effec-
`
`4
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`tively monitors the core network supply voltage and sends a signal to the I/O de-
`
`vices and/or level shifters indicating when the core network supply voltage is pow-
`
`ered down or power collapsed. See APPLE-1001, 1:55-57; see also APPLE-1003,
`
`¶ 59. This signal can be leveraged by the recipient I/O devices and/or level shifters
`
`to trigger a transition by those devices into a “known state” in which those devices
`
`will not process erroneous signals output by the powered down core network de-
`
`vices. See APPLE-1001, 1:34-57; see also APPLE-1003, ¶ 59.
`
`In its background section, the ’674 Patent acknowledges that a “standard”
`
`POC system 10 for multiple supply voltage devices was known at the time of the
`
`filing of the ’674 Patent. See APPLE-1001, 1:57-2:39. This known POC system
`
`10 is labeled as “PRIOR ART” in FIG. 1 and is shown to include a power-up/down
`
`detector 100, a signal amplifier 101, and an output stage 102. See id. at FIG. 1,
`
`1:57-62. The main difference between this prior art POC system 10 and the pur-
`
`ported invention of the ’674 Patent is the addition of a feedback network 310. AP-
`
`PLE-1003, ¶ 60. A comparison of FIG. 1 and FIG. 4 illuminates this straightfor-
`
`ward difference. Id.
`
`5
`
`

`

`power up/
`down detector
`
`signal processor
`
`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`feedback 
`network
`signal processor
`
`power up/
`down detector
`
`
`
`The ’674 Patent describes that the prior art POC system 10 suffered from
`
`“leakage current between I/O power supply 104 and ground” and/or slower
`
`“switching/detecting times” (i.e., the speed with which the prior art POC system 10
`
`detects that the core supply voltage has powered down). See APPLE-1001, 2:25-
`
`3:11; see also APPLE-1003, ¶ 61. The feedback network 310 increases the current
`
`capacity when it is “on,” resulting in increased sensitivity. See APPLE-1001, 5:16-
`
`23; see also APPLE-1003, ¶ 61. Conversely, the feedback network 310 decreases
`
`the current capacity when it is “off,” which “will limit and reduce the amount of
`
`leakage current that may be dissipated through the power up/down detector.” See
`
`APPLE-1001, 5:29-38; see also APPLE-1003, ¶ 61.
`
`Notably, each of the three implementations of the feedback network 310—
`
`corresponding to FIGS. 4, 5, and 6 of the ’674 Patent—will increase and decrease
`
`the current capacity as described above. APPLE-1003, ¶ 62. For example, in FIG.
`
`4, the transistor M8 is in parallel with the transistor M4. APPLE-1001, 6:4-5. Due
`
`6
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`to its configuration, transistor M8 is generally “on” when the transistor M4 is “on”
`
`and is “off” when the transistor M4 is “off” (except for a short delay during transi-
`
`tions in Vcore). See APPLE-1001, 6:4-28; see also APPLE-1003, ¶ 62. When both
`
`transistors M4 and M8 are “on” (i.e., Vcore is off), the transistor M8 increases the
`
`current capacity of the power up/down detector 306, because it effectively allows
`
`more current to flow from the source to the drain of transistor M4 than otherwise
`
`would have been possible. See APPLE-1001, 6:5-12; see also APPLE-1003, ¶ 62.
`
`In other words, when both transistors M4 and M8 are “on” (i.e., Vcore is off), the
`
`transistor M8 increases the current capacity of the power up/down detector 306.
`
`See id.
`
`On the other hand, when both transistors M4 and M8 are “off” (i.e., Vcore is
`
`on), “the power up/down detector 306 has a decreased current capacity, i.e.,
`
`smaller current will flow through the transistor M8 because of the amplified low
`
`signal.” APPLE-1001, 6:12-18 (emphasis added); see also APPLE-1003, ¶ 63. In
`
`other words, when both transistors M4 and M8 are “off” (i.e., Vcore is on), the tran-
`
`sistor M8 decreases the current capacity of the power up/down detector 306. See
`
`id. A similar principal holds for the implementations of the ’674 Patent’s feedback
`
`network shown in FIGS. 5 and 6, which similarly show feedback transistors in par-
`
`allel with transistors of the power up/down detector. APPLE-1003, ¶ 63.
`
`
`
`7
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`B.
`Summary of the Prosecution History of the ’674 Patent
`The ’674 Patent issued on November 22, 2011 from U.S. Patent Application
`
`No. 12/365,559, which was filed on February 4, 2009 with 27 claims. See APPLE-
`
`1002. The ‘559 application did not include a priority claim.
`
`During prosecution, the Examiner issued two non-final office actions. See
`
`APPLE-1002, pp. 102-113, 142-153. In the first office action, the Examiner re-
`
`jected original claims 1, 7-10, and 19-25 based on U.S. Patent 6,577,166 to Lim.
`
`Id. at 147. Further, the Examiner indicated that original claims 2-5 and 11-15 were
`
`allowable. Id. at 151. In response, the applicant amended independent claim 1 to
`
`incorporate the features of dependent claim 2 and amended independent claims 10
`
`and 20 to incorporate the features of corresponding dependent claim 11. Id. at
`
`129-137.
`
`In a subsequent non-final office action, the Examiner rejected claims 1, 3, 7-
`
`10, 12, 15, and 19-25 as anticipated or rendered obvious in part by U.S. Patent No.
`
`5,723,990 to Rhooparvar. Id. at 105-110. The Examiner also indicated that claims
`
`4, 5, 13, and 14 were allowable. Id. at 111. In response, applicant amended each
`
`of the independent claims to recite “at least one third transistor coupled in series
`
`between the at least one first transistor and the at least one second transistor,” or a
`
`variation thereof. Id. at 89-95. With this amendment, applicant explained that:
`
`each embodiment of the application that is shown in Figures 4-6 in-
`cludes at least three transistors in series with each other and having a
`
`8
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`commonly connected gate. For example, the at least one third transis-
`tor could be either M5 or M6 [or] both according to the amended
`claims. Roohpaver does not teach or suggest a third transistor config-
`ured in series between the claimed at least one first transistor and the
`claimed at least one second transistor.
`Id. at 96-97 (emphasis added). Subsequent to this amendment to include the “third
`
`transistor,” the Examiner issued a Notice of Allowance. Id. at 68-72.
`
`Thus, in allowing the ’674 Patent, the Examiner did not consider or rely
`
`upon Steinacker, Doyle, or Park. See generally APPLE-1002. Moreover, though
`
`Majcherczak was cited in an information disclosure statement, Majcherczak was
`
`not even applied by the Examiner in a rejection. See id. at 102-113, 142-153. Nor
`
`did the Examiner ever appear to consider a rejection based on Applicant’s own Ad-
`
`mitted Prior Art (“AAPA”), as reflected in FIGS. 1 and 2 and the background sec-
`
`tion of the ’674 Patent. See id. Accordingly, neither the grounds presented in this
`
`petition nor substantially similar grounds have been presented by or to the USPTO.
`
`C. Claim Construction under 37 C.F.R. §§ 42.104(b)(3)
`Unless otherwise noted below, Petitioner submits that all terms should be
`
`given their plain meaning, but reserves the right to respond to any constructions
`
`that may later be offered by the Patent Owner or adopted by the Board. Petitioner
`
`is not waiving any arguments concerning indefiniteness or claim scope that may be
`
`raised in litigation.
`
`
`
`9
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`1.
`“processing circuitry” (claim 1)
`The ’674 Patent does not define the term “processing circuitry,” but it pro-
`
`vides examples of its implementation, which includes an inverting amplifier. See
`
`APPLE-1003, ¶¶ 65-67. While expressly caveating “that each of the figures is pro-
`
`vided for the purpose of illustration and description only and is not intended as a
`
`definition of the limits of the present disclosure,” the ’674 Patent describes that the
`
`“processing circuitry 307 is made up of a signal processor 308 and an output buffer
`
`309” and that “signal processor 308 [as shown in FIGS. 4-6] comprises an invert-
`
`ing amplifier 400.” See APPLE-1001, 4:7-10, 5:5-6, 6:35-37, 8:14-42. Thus, at
`
`least an inverting amplifier constitutes “processing circuitry,” as that term is used
`
`in the ’674 Patent. See APPLE-1003, ¶ 66.
`
`Therefore, the terms “processing circuitry” should be construed at least
`
`broadly enough to encompass the embodiment described in the ’674 Patent, which
`
`is an amplifying inverter. APPLE-1003, ¶¶ 65-69.
`
`III. MANNER OF APPLYING CITED PRIOR ART TO EVERY
`CLAIM FOR WHICH AN IPR IS REQUESTED, THUS ESTAB-
`LISHING A REASONABLE LIKELIHOOD THAT AT LEAST
`ONE CLAIM OF THE ’674 PATENT IS UNPATENTABLE
`This request shows how the primary references above, alone or in combina-
`
`tion with other references, disclose the limitations of the Challenged Claims,
`
`thereby rendering the Challenged Claims unpatentable. As detailed below, this re-
`
`quest shows a reasonable likelihood that the Requester will prevail with respect to
`
`10
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
`the Challenged Claims.
`
`A.
`
`[GROUND 1] – Steinacker in view of Doyle and Park Ren-
`der Claims 1, 2, and 5-7 Obvious
`1. Overview of Steinacker1
`Steinacker describes “a circuit arrangement having at least two circuit blocks
`
`operated at different supply voltages which is able to ensure reliable operation of
`
`the circuit arrangement regardless of turn-on profiles for the different supply volt-
`
`ages in the circuit blocks.” APPLE-1005, 2:14-19. Steinacker acknowledges the
`
`problem addressed by the ’674 Patent, as Steinacker likewise notes, “[t]he fact that
`
`the circuit blocks operate at different supply voltages and that the supply voltages
`
`can be turned on and off independently of one another means that reliable opera-
`
`tion of the circuit arrangement is not always ensured.” Id. at 1:49-52. Indeed, con-
`
`sistent with the approach proposed by the ’674 Patent, “[a] basic concept behind
`
`[Steinacker’s] invention is that the second circuit block is deactivated [i.e., put in a
`
`known state] when the first supply voltage is still too low in order to ensure safe
`
`
`1 Petitioner hereby expressly incorporates the entirety of the discussion of the
`
`Steinacker, Doyle, and Park combination set forth in Sections III.A.1-5 into the el-
`
`ement-by-element analysis of Ground 1, infra.
`
`11
`
`

`

`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`operation of the first circuit block.” Id. at 2:35-38. In other words, Steinacker de-
`
`scribes a similar solution to the same problem as the power-on/off-control (POC)
`
`described in the ’674 Patent. APPLE-1003, ¶ 86.
`
`In more detail, Steinacker describes a “circuit arrangement 1 [that] has a first
`
`supply voltage domain 1.1 and a second supply voltage domain 1.2.” APPLE-
`
`1005, 4:5-7. “In the case of a mixed-signal circuit, for example, the voltage level
`
`of the first supply voltage is lower than the value of the second supply voltage.”
`
`Id. at 4:14-16. In circuit arrangement 1, a first circuit block 2 is supplied by the
`
`first supply voltage and a second circuit block 3 is supplied by the second supply
`
`voltage. See id. at FIG. 1, 4:23-27. In order to interface between the first circuit
`
`block 2 and the second circuit block 3, the circuit arrangement 1 includes a voltage
`
`level shifting unit 4. See id. at FIG. 1, 4:23-35.
`
`Steinacker’s circuit arrangement 1 also includes a voltage level detector 5.
`
`APPLE-1005, FIG. 1, 4:45-64. The voltage level detector 5 performs a similar
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`function to the POC network described in the ’674 Patent. APPLE-1003, ¶ 91.
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`Specifically, Steinacker describes that “the voltage level detector 5 sends a first
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`control signal in the form of a voltage level at the level of the second supply volt-
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`age—that is to say a logic value ‘l’—to the voltage level shifting unit 4 if the first
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`supply voltage is lower than a threshold value from the voltage level detector 5.”
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`APPLE-1005, 4:56-61. Like the POC network of the ’674 Patent, the signal output
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`by the voltage level detector 5 indicates “when the logic gates in the first supply
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`voltage domain 1.1 or in the second supply voltage domain 1.2 are not yet operat-
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`ing reliably.” APPLE-1005, 4:61-64; see also APPLE-1003, ¶ 92.
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`As for voltage level detector 5, Steinacker provides a list of the types of cir-
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`cuits that can be used as the voltage level detector 5 and describes how such a cir-
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`cuit would be connected into the circuit arrangement 1. See id. In particular,
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`Steinacker describes that voltage detector 5 can take “the form of a Schmitt trigger
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`with an inverting output . . . an inverter circuit, a comparator circuit or comparable
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`circuits.” Id. at 4:49-55. Additionally, Steinacker describes that “[t]he voltage
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`level detector 5 is supplied with the second supply voltage” (i.e., the higher supply
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`voltage) and the first supply voltage (i.e., the lower supply voltage) is its input. Id.
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`at 4:45-49. This is the same general manner of connecting the supply voltages as
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`shown in FIGS. 1, 4, 5, and 6 of the ’674 Patent. APPLE-1003, ¶ 93. Yet,
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`Steinacker assumes a person of ordinary skill in the art as of the Critical Date
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`(hereinafter “POSITA”) capable of identifying a Schmitt trigger, inverter circuit, a
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`comparator circuit or comparable circuit to implement the voltage detector 5. Id.
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`2. Overview of Doyle
`Doyle describes an improved CMOS inverter circuit. See APPLE-1006, Ab-
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`stract, 1:7-13, 2:37-40. In FIG. 2A, Doyle illustrates a “basic well-known CMOS
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`inverter structure” and describes various reasons why its trip point (i.e., the thresh-
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`old at which a rising or falling input voltage causes the output of the inverter to
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`change) can be unstable. See id. at 4:3-5:59. Accordingly, as illustrated in FIG. 2
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`(reproduced below with comparable labels from the ’674 Patent), Doyle describes
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`“a CMOS inverter circuit having a trip point that is relatively stable with respect to
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`temperature and/or to certain CMOS manufacturing process parameters.” Id. at
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`2:37-40; see also APPLE-1003, ¶ 95.
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`
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`Specifically, “P channel MOSFET 17 and N channel MOSFET 16 have their
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`gates connected to Vin and their drains connected to conductor 21.” Id. at 5:61-64.
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`“[A] second inverter including P channel MOSFET 19 and N channel MOSFET 20
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`has its input connected to Vout conductor 21,” and the output of the second inverter
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`is connected to conductor 25. Id. at 6:9-14. “Feedback is provided from the output
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`conductor 25 to the gate of a P channel MOSFET 18 connected in parallel with P
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`channel MOSFET 17.” Id. at 6:14-17. Additionally, “the input of an inverter
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`driver can be provided, which inverter driver includes P channel MOSFET 22 and
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`N channel MOSFET 23.” Id. at 19-21.
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`The circuit shown in FIG. 2 of Doyle is nearly identical to the POC network
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`shown in FIG. 4 of the ’674 Patent, except that Doyle’s first inverter (i.e., the
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`power up/down detector highlighted in green) includes only one P channel
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`MOSFET and only one N channel MOSFET. See APPLE-1003, ¶¶ 96-102. Yet,
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`as described by Park, it was well known at the time of the ’674 Patent to split each
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`of the P channel MOSFET 17 and N channel MOSFET 16 into two MOSFETs.
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`APPLE-1003, ¶ 102.
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`3. Overview of Park
`Park describes that “power consumption is one of the top concerns of VLSI
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`circuit design, for which CMOS is the primary technology.” APPLE-1007, p. 1.
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`As part of discussing ways to reduce power consumption, Park begins by describ-
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`ing certain “low-power techniques that primarily target reducing leakage power
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`consumption of CMOS circuits.” Id. One “technique to reduce leakage power is
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`transistor stacking.” Id. at 2. According to Park, “[t]ransistor stacking exploits the
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`stack effect; the stack effect results in substantial subthreshold leakage current re-
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`duction when two or more stacked transistors are turned off together.” Id. In other
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`words, to decrease leakage current, it was known to replace a single transistor with
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`two stacked transistors. APPLE-1003, ¶ 109.
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`Park illustrates this stacking technique in FIG. 11, which is reproduced be-
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`low at left. Id. at 7. “Fig. 11 shows the forced stack technique, which forces a
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`stack structure by breaking down an existing transistor into two half size transis-
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`tors.” Id. at 5-6. Furthermore, FIG. 1(a), which is reproduced below at right, illus-
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`trates this forced stack technique applied to an inverter. Id. at 2; see also APPLE-
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`1003, ¶ 110.
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`4.
`The Combination of Steinacker, Doyle, and Park
`As described in Section III.A.1, supra, Steinacker further describes that the
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`voltage level detector 5 can take the form of an inverter. APPLE-1005, 4:49-55.
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`As to implementation of the inverter, a POSITA would have understood from
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`Doyle and Park the claimed details. See APPLE-1003, ¶¶ 103-108, 111-122. Spe-
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`cifically, Doyle describes “a CMOS inverter circuit having a trip point that is rela-
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`tively stable with respect to temperature and/or to certain CMOS manufacturing
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`process parameters.” Id. at 2:37-40.
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`Notably, Doyle refers to Vdd as the “power supply voltage” and Vin as the
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`“input voltage.” APPLE-1006, 2:57-58, 4:23-24 (emphasis added). When con-
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`necting the inverter taught by Doyle into the circuit arrangement 1 of Steinacker as
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`the voltage detector 5, Steinacker teaches that the “first supply voltage [i.e., a
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`lower supply voltage—or Vcore in the terminology of the ’674 Patent] is supplied to
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`it via a first input.” APPLE-1005, 4:48-49 (emphasis added). Thus, a POSITA
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`would have found it obvious that the lower supply voltage (Vcore) would be con-
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`nected to the VIN (i.e., “input voltage”) terminal of Doyle’s inverter. APPLE-
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`1003, ¶ 105. Furthermore, when connecting the inverter taught by Doyle into the
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`circuit arrangement 1 of Steinacker as the voltage detector 5, Steinacker teaches
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`that the inverter “is supplied with [a] second supply voltage” (i.e., a higher supply
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`voltage—or VI/O in the terminology of the ’674 Patent). APPLE-1005, 4:47-48
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`(emphasis added). Thus, a POSITA would have found it obvious that the higher
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`supply voltage (VI/O) would be connected to the Vdd (i.e., “power supply voltage”)
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`terminal of Doyle’s inverter, which is the only terminal other than the “input” to
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`which a voltage can be “supplied.” APPLE-1003, ¶ 105.
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`Based on these combined teachings of Steinacker and Doyle, a POSITA
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`would have found it obvious that the voltage detector 5 of Steinacker’s circuit ar-
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`rangement 1 to be implemented as shown in the following reproduction of Doyle’s
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`FIG. 2 in which black annotations describing how the inverter would be connected
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`in the circuit arrangement have been added. See APPLE-1003, ¶¶ 105-106.
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`
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`Doyle describes its inverter as a CMOS inverter circuit, and Park describes
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`techniques for further improving CMOS circuits. APPLE-1006, 2:37-40; APPLE-
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`1007, p. 1. One such technique is the forced stack technique, which replaces each
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`transistor with two stacked transistors. APPLE-1007, 2, 5-7; APPLE-1003, ¶ 111.
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`Employing Park’s forced stacking