IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Chang Ki Kwon et al.
`In re Patent of:
`8,063,674
`U.S. Patent No.:
`November 22, 2011
`Issue Date:
`Appl. Serial No.: 12/365,559
`Filing Date:
`February 4, 2009
`Title:
`Multiple supply-voltage power-up/down detectors
`
`SUPPLEMENTAL DECLARATION OF ROBERT W. HORST, PH.D.
`
`I, Robert W. Horst, Ph.D., of San Jose, CA, declare that:
`
`I.
`
`1.
`
`Introduction
`
`This declaration supplements the declaration entitled “Declaration of
`
`Robert W. Horst, Ph.D.” dated June 17, 2018 (hereinafter “Original Declaration”).
`
`The statements made and opinions rendered therein can be assumed to be
`
`incorporated into this supplemental declaration, except as may be explicitly noted
`
`otherwise herein.
`
`2.
`
`In addition to the materials I reviewed in preparation of my Original
`
`Declaration—which were noted in paragraph 7—I have reviewed the following list
`
`of materials in preparation of this declaration:
`
`• Patent Owner Response to Petition (Paper 12)
`
`• Dr. Massoud Pedram’s Declaration (Ex. 2002)
`
`• Horst Declaration Transcript (Ex. 2003)
`
`• Pedram Deposition Transcript (APPLE-1017)
`
`1
`
`Exhibit 1018
`Apple v. Qualcomm
`IPR2018-01315
`
`
`
`Chang Ki Kwon et al.
`In re Patent of:
`8,063,674
`U.S. Patent No.:
`November 22, 2011
`Issue Date:
`Appl. Serial No.: 12/365,559
`Filing Date:
`February 4, 2009
`Title:
`Multiple supply-voltage power-up/down detectors
`
`SUPPLEMENTAL DECLARATION OF ROBERT W. HORST, PH.D.
`
`I, Robert W. Horst, Ph.D., of San Jose, CA, declare that:
`
`I.
`
`1.
`
`Introduction
`
`This declaration supplements the declaration entitled “Declaration of
`
`Robert W. Horst, Ph.D.” dated June 17, 2018 (hereinafter “Original Declaration”).
`
`The statements made and opinions rendered therein can be assumed to be
`
`incorporated into this supplemental declaration, except as may be explicitly noted
`
`otherwise herein.
`
`2.
`
`In addition to the materials I reviewed in preparation of my Original
`
`Declaration—which were noted in paragraph 7—I have reviewed the following list
`
`of materials in preparation of this declaration:
`
`• Patent Owner Response to Petition (Paper 12)
`
`• Dr. Massoud Pedram’s Declaration (Ex. 2002)
`
`• Horst Declaration Transcript (Ex. 2003)
`
`• Pedram Deposition Transcript (APPLE-1017)
`
`1
`
`Exhibit 1018
`Apple v. Qualcomm
`IPR2018-01315
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`• U. Daya Perera, Reliability of Mobile Phones, 1995 IEEE Proceedings
`
`Annual Reliability and Maintainability Symposium (Jan. 1995) (AP-
`
`PLE-1019)
`
`• U.S. Patent No. 5,386,153 (“Voss”) (APPLE-1022)
`
`• Wikipedia Entry for “LTspice” available at
`
`https://en.wikipedia.org/wiki/LTspice (accessed on July 17, 2019)
`
`(APPLE-1023)
`
`• John F. Wakerly, DIGITAL DESIGN PRINCIPLES AND PRACTICES 4th Ed.
`
`(2006) (APPLE-1024)
`
`• Bruce Jacob, ENEE 359a Digital VLSI Design - Transistor Sizing &
`
`Logical Effort, available at
`
`https://ece.umd.edu/courses/enee359a.S2007/ (APPLE-1025)
`
`II. Dr. Pedram’s Analysis of the Prior Art is Incorrect and Incom-
`plete
`
`A.
`
`SPICE simulation shows a Steinacker/Doyle/Park
`combination that does not result in increased leakage
`current, DC fighting conditions, or a breakdown in circuit
`functionality.
`
`3.
`
`Dr. Pedram has claimed that the Steinacker/Doyle/Park combination
`
`would not function in the same manner as the ’674 patent and could suffer from
`
`increased leakage current, DC fighting conditions, or a breakdown in circuit
`
`functionality.
`
`2
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`Ex. 1017, 167:13-23.
`
`
`
`4.
`
`However, Dr. Pedram did not run any simulations or include detailed
`
`analysis to support his conclusions. See Ex. 1017, 40:15-41:13, 167:20-23, 171,
`
`20-172:1, 180:6-16. I do not agree with his conclusions and have run SPICE
`
`circuit simulations to show that he is incorrect or has analyzed the circuits under
`
`unspecified conditions that introduce such problems. Based on my analysis and
`
`simulations, the prior art combinations operate nearly identically to the circuit
`
`3
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`shown in Figure 4 of the ’674 Patent (hereinafter referred to as the “’674 Figure 4
`
`circuit”) and do not introduce the presumed problems described by Dr. Pedram.1
`
`5.
`
`SPICE is a widely-available, well-known circuit simulation program
`
`which is often used for the development and analysis of analog circuits. For the
`
`following simulations, I used LTSpice XVII from Analog Devices, a widely used
`
`and free circuit electronic circuit simulator2. See generally Ex. 1023. SPICE
`
`circuit simulations were run to verify the operation of the ’674 Figure 4 circuit, the
`
`prior art circuits, and the combinations described in my Original Declaration.
`
`6.
`
`The simulations use a power supply with Vdd=5V (VI/O) and test the
`
`ability of the circuit to detect power up and down of a 3.3V supply (Vcore). Power
`
`up is detected at ~3V, and power down at ~2.5V. MOSFET thresholds have been
`
`
`1 The ’674 Figure 4 circuit is one of three preferred embodiments described in the
`
`’674 Patent—Figures 5 and 6 being the other two. The ’674 Figure 4 circuit in-
`
`cludes various limitations that are not required by the claims of the ’674 Patent. In
`
`fact, Dr. Pedram agrees the specific transistor configuration (including number of
`
`PMOS transistors and location of feedback) of the ’674 Figure 4 circuit is not a re-
`
`quirement of any independent claim. See Ex. 1017, 80:19-86:21.
`
`2 The tool is available at https://www.analog.com/en/design-center/design-tools-
`
`and-calculators/ltspice-simulator.html
`
`4
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`set based on these voltages, and all simulations of the ’674 Figure 4 circuit and
`
`prior art combinations use the same threshold settings. Dr. Pedram agreed that the
`
`’674 Figure 4 circuit could operate at these voltages:
`
`Ex. 1017, 108:13-18.
`
`
`
`7.
`
`SPICE requires setting parameters to match the circuit being
`
`simulated. Some of the required parameters for this circuit include the thresholds
`
`for the inverters and the thresholds and strengths (width and length) of the
`
`transistors. The ’674 patent has no guidance for these parameters and expects
`
`someone applying the circuits to have sufficient expertise and experience to set the
`
`parameters appropriately. Where possible, I used channel length and width
`
`parameters based on the Voss reference (Ex. 1022) that was available prior to the
`
`critical date of the ’674 patent. For other parameters, such as transconductance, I
`
`relied on the LTSpice default settings.
`
`8.
`
`The following SPICE simulations specify the turn-on thresholds and
`
`channel width and length, but use defaults for the other MOSFET parameters. The
`
`thresholds were set to make the circuits operable to detect power up and down for a
`
`5
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`5V I/O supply detecting the power up of a core voltage at about 3V. The
`
`simulations show the core (input) voltage ramping from 0 to 3.3V and back to
`
`zero, but in normal system operation, the circuit would stay above the threshold for
`
`long periods of time while the core voltage is on (i.e., when the electronic device
`
`that utilizes the simulated circuits is in use). Channel width and length are process
`
`dependent. Values were chosen for P and N transistors corresponding to values
`
`from the input stage of the power up/down detector described in Voss. Voss
`
`Figure 3 shows a slightly different power up/down circuit, but it has an input stage
`
`with NMOS and PMOS transistors width and length specified (25 µ/.8 µ for
`
`NMOS, 5 µ/.8 µ for PMOS). These are the same length and width I used for most
`
`NMOS and CMOS transistors in the following simulations.
`
`
`
`Voss Figure 3 showing transistor width/length for the input state to a power
`up/down detector.
`
`
`
`6
`
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`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`9.
`
`The’674 Figure 4 circuit simulations use the Voss values for the width
`
`and length of the transistors in the input stage. A different value was chosen for
`
`the width for the feedback P-channel to make this transistor weaker than in the
`
`Voss circuit due to the difference in the circuits. The “.model” statements below
`
`show that simulations of the prior art circuits use the same transistor parameters as
`
`the ’674 Figure 4 circuit simulations. These simulations also use the same type of
`
`triangle-wave ramp of input voltage from 0 to maximum to zero as used by Voss in
`
`his Figure 4 SPICE simulations.
`
`10. The following figure shows diagrams of the 674 Figure 4 circuit and
`
`the Steinacker/Doyle/Park circuit:
`
`The 674 circuit from Fig. 4 (left) and Steinaker/Doyle/Park (right). The
`Steinacker voltage level detector is implemented with the Doyle circuit using
`stacked P channel MOSFETs according to Park.
`
`
`
`
`
`7
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`11. These circuits differ primarily in the connection to the drain of the
`
`feedback transistor. In the ’674 Figure 4 circuit, the feedback transistor is
`
`connected in parallel with only the upper P-channel transistor, while the prior art
`
`circuit, it is in parallel with both of the stacked P-channel transistors. The
`
`Steinaker/Doyle/Park circuit shows Doyle’s resistor set to 135 ohms3, which is one
`
`of the values suggested in Doyle Figure 6. When the circuit is built with a non-
`
`zero resistor, the combination enjoys the added reliability benefit of temperature
`
`compensation presented in Doyle, but temperature-dependent threshold variations
`
`were not simulated. The reliability improvement from temperature compensation
`
`is a motivation to select the Doyle circuit for Steinaker’s voltage detection circuit.
`
`12. The strength of the stacked P channel transistors has been set
`
`according to Park. When replacing the Doyle P-channel with Park’s pair of
`
`stacked transistors, the W/L ratio was halved from 5/0.8 to 2.5/0.8. Park suggests
`
`adjusting the W/L parameters in this way when replacing a transistor with a pair of
`
`stacked transistors. Ex. 1007, 5-7 (“When we apply the forced stack technique, we
`
`replace each existing transistor with two half sized transistors as shown in Fig.
`
`11.”). The strength of the P-channel transistor before stacking is the same as in the
`
`
`3 Simulations were also done with a 0 ohm resistor (equivalent to a wire) with no
`
`visible difference in the waveforms.
`
`8
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`simulated ’674 Figure 4 circuit. The resulting Steinacker/Doyle/Park combination
`
`has nearly identical performance to the ’674 Figure 4 circuit as shown by the
`
`following simulation results:
`
`Simulations of the 674 Figure 4 circuit (left) and Steinacker/Doyle/Park circuit
`(right). Waveforms are nearly identical.
`
`
`
`
`
`
`13.
`
` In the simulation results, the top pane shows the input voltage ramp
`
`along with the signal to the gate of the feedback P-channel FET. The place where
`
`they cross shows the detection thresholds when the input is rising or falling. The
`
`rising crossing is always higher than the falling crossing, indicating that both
`
`circuits exhibit hysteresis. Note that Steinacker draws the symbol for an input
`
`detector with hysteresis for voltage level detector 5 in Fig. 1 indicating the
`
`preference for a voltage level detector with hysteresis.
`
`9
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`14. The second pane shows the junction of the P and N channels and
`
`output of the second inverter. This shows how the slow detection signal is cleaned
`
`up by the amplification and threshold of the inverters.
`
`15. The third pane shows the current through the feedback P-channel
`
`FET. The current drops to effectively zero when its gate goes high. This shows
`
`that both feedback circuits reduce the current when the feedback transistor is
`
`turned off. In both cases the feedback circuit is configured to “adjust the current
`
`capacity”, as required by the ’674 claims. The magnitude of the feedback current
`
`is nearly identical in both circuits, with the current slightly lower in the ’674 Figure
`
`4 circuit. Neither circuit has significant crowbar or “glitch” current.
`
`16. The fourth pane shows the current through the input stack of N and P
`
`FETs. This is the normal current spike that flows through a CMOS circuit as one
`
`transistor begins to turn on while the complementary transistor has not yet fully
`
`turned off. The ’674 Figure 4 circuit has slightly higher current spikes, but the
`
`magnitude is low. Neither circuit has significant crowbar or “glitch” current.
`
`17. The fifth pane shows the power dissipated in the whole circuit
`
`excluding the inverters. It shows how power drops when the feedback FET is
`
`turned off. Power is computed as 5V (Vdd or VI/O) times the sum of the feedback
`
`current (third panel) and stack current (fourth panel). The ’674 Figure 4 circuit
`
`dissipates slightly less power on the rising input voltage transition, and slightly
`
`10
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`more power on the falling transition, but the magnitude of the differences are
`
`small. The low power dissipation shows that neither circuit has strong crowbar
`
`currents or instabilities.
`
`18. The slightly higher peak current of the Steinacker/Doyle/Park circuit
`
`on the rising edge causes the peak power dissipation to be about 50 microwatts
`
`greater than the 400 microwatts of the ’674 Figure 4 circuit. However, this circuit
`
`is used for power up/down detection and the input voltage passes through this
`
`transition very infrequently. It occurs, for instance, during the brief period when
`
`the voltage is first reaching a valid level during the time a portable device is
`
`powered up. The small increased power would occur perhaps a maximum of a few
`
`times per hour (much less than 1 cycle per second), not at GHz frequencies (a
`
`billion times per second) as implied by Dr. Pedram. Ex. 1017, 180:17-181:9.
`
`Thus, a POSITA would not have been dissuaded from making the proposed
`
`Steinacker/Doyle/Park combination based on these small differences in power.
`
`19. The simulations show results that are almost identical. There are
`
`small differences in the stack and feedback currents, but the resulting power graphs
`
`are nearly indistinguishable. See Ex. 1017, 162:6-163:2 (Dr. Pedram agreeing that
`
`small differences in the milliwatt to microwatt range make the results in FIG. 17(b)
`
`of Park no better or worse than one another).
`
`11
`
`
`
`20. The simulations show that with the chosen simulation parameters, the
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`Steinacker/Doyle/Park circuit does not exhibit the problems imagined by Dr.
`
`Pedram. The leakage current is not significantly increased, there are no DC
`
`fighting conditions, and there is no breakdown in circuit functionality4.
`
`
`
`
`
`
`4 Any of these conditions could be caused by incorrect circuit parameters (e.g.
`
`poorly chosen thresholds or transistor strengths), but the ’674 Figure 4 circuit
`
`would be similarly affected by poorly chosen parameters. There is little point in
`
`analyzing the differences in inoperable circuits.
`
`12
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`
`
`B.
`
`SPICE simulation shows an AAPA/Majcherczak
`combination that does not result in increased leakage
`current, DC fighting conditions, or a breakdown in circuit
`functionality.
`
`21.
`
` Dr. Pedram incorrectly states that the AAPA/Majcherczak
`
`combination must have a large amount of leakage current from VI/O to VSS
`
`(ground):
`
`during periods when the Vcore voltage in Fig. 1 of the
`
`’674 Patent is on, in a high state, the AAPA design of the
`
`Power U/D Detector 100 would result in a large amount
`
`of leakage current from VI/O to VSS due to non-
`
`existence of the stacked PMOS transistors in the pull-up
`
`section of the detector (and hence the absence of the
`
`leakage-reducing stack effect of series-connected
`
`transistors.) Moreover, the addition of Majcherczak’s
`
`transistor M6 would result in increased leakage current in
`
`the power-up/down detector 100 because the transistor
`
`M6 adds a leakage path.
`
`Ex. 2002, ¶ 70 (emphasis added).
`
`
`22. This presumption is wrong because when the appropriate thresholds
`
`and strengths are used, there are no long periods of time when both PMOS and
`
`NMOS transistors are conducting. At most, there may be very brief periods when
`
`they are both weakly conducting, but the resulting amount of current is relatively
`
`13
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`small and would be acceptable to a POSITA. This is illustrated by the following
`
`simulation in which identical transistor parameters are chosen for both the ’674
`
`Figure 4 circuit and AAPA/Majcherczak circuit simulations:
`
`
`
`
`
`
`The ’674 circuit from Fig. 4 (left) and AAPA+Majcherczak circuit (right).
`
`
`
`23. These circuits are identical except for the insertion of an additional
`
`stacked P channel transistor in the ’674 Figure 4 circuit. The circuit simulations
`
`below show that impact of the additional transistor is almost imperceptible.
`
`14
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`
`Simulations of the ’674 Figure 4 circuit (left) and AAPA+ Majcherczak (right).
`Waveforms are nearly identical.
`
`
`
`24.
`
`In the simulation results, the top pane shows the input voltage ramp
`
`along with the signal to the gate of the feedback P-channel FET. The place where
`
`they cross shows detection thresholds when the input is rising or falling. In both
`
`circuits, the rising crossing is always higher than the falling crossing, indicating
`
`that both of these circuits exhibit hysteresis. The voltages where the circuits
`
`switch are similar.
`
`25. The second pane shows the junction of the P and N channels and
`
`output of the second inverter. This shows how the slow detection signal is cleaned
`
`up by the amplification and threshold of the inverters. The times when the
`
`inverters switch is nearly identical in both circuits.
`
`15
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`26. The third pane shows the current through the feedback P-channel
`
`FET. It drops to zero when its gate goes high. This shows that both feedback
`
`circuits reduce the current when the feedback transistor is turned off. In both cases
`
`the feedback circuit is configured to “adjust the current capacity,” as required by
`
`the ’674 claims. The peak magnitude of the feedback current is similar in both
`
`circuits. The small current through the feedback transistor does not show “large
`
`amount of leakage current from VI/O to VSS” as predicted by Dr. Pedram. See
`
`Ex. 2002, ¶ 70.
`
`27. The fourth pane shows the current through the input stack of N and P
`
`FETs. This is the normal current that flows in a CMOS circuit as one transistor
`
`begins to turn on while the complementary transistor has not yet fully turned off.
`
`Both circuits show no significant crowbar current. (Both circuits use weak
`
`transistors with high on resistance and do not produce large crowbar currents even
`
`when both are conducting.) There is a small difference in the magnitude of the
`
`peak currents, but the difference is so small that the resulting power dissipated is
`
`nearly identical in both circuits. During the rising transition, before reaching
`
`threshold, the current is primarily determined by the subthreshold N-channel FETs,
`
`and those are identical in both circuits. In the falling transition, the current is
`
`primarily determined by identical P-channel transistors connected to VI/O (which
`
`are the first to switch off as the input voltage drops).
`
`16
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`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`28. The fifth pane shows the power dissipated in the whole circuit
`
`excluding the inverters. It shows how power drops when the feedback FET is
`
`turned off. Power is computed as VI/O (5V) times the sum of the feedback current
`
`(third panel) and stack current (fourth panel). Both circuits have the same power
`
`within a few microwatts.
`
`29. The simulations show results that are almost identical. There are small
`
`differences in the stack and feedback currents, but the magnitude of these
`
`differences is small, and the resulting power graphs are nearly indistinguishable.
`
`See Ex. 1017, 162:6-163:2 (Dr. Pedram agreeing that small differences in milliwatt
`
`microwatt range make the results in FIG. 17(b) of Park no better or worse than one
`
`another).
`
`30. These graphs show no effect from the inverter delay. There is no “DC
`
`fighting condition,” “complete circuit breakdown,” or “stability issues” as
`
`imagined by Dr. Pedram. See Ex. 2002, ¶¶ 83-85.
`
`31. Note that all circuits exhibit a small current glitch when the detection
`
`circuit is near the threshold when power is rising, and have another glitch when
`
`power is falling. This is the normal behavior of any CMOS inverter which
`
`dissipates power when switching. None of the circuits show excessive crowbar
`
`current or any instabilities as claimed by the Dr. Pedram. The similarity in the
`
`17
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`simulations strongly contradicts the notion that circuit operation could be
`
`considered a reason not to combine the circuits as proposed.
`
`C. There is no “highly unstable metastable operating regime”
`in the power detection circuit of the AAPA/Majcherczak
`combination
`
`32. Dr. Pedram incorrectly states:
`
`Moreover, this DC fighting condition at the output of the
`
`power U/D detector 100 during the inverter delay period
`
`can cause a downstream ripple effect such that Inverter
`
`105 (highlighted in yellow) becomes unstable (including
`
`entering a highly undesirable metastable operating
`
`regime in which its input and output voltages are at the
`
`same level equal to one half of the VI/O), causing further
`
`instability in the “feedback network” (highlighted in
`
`blue), and potentially resulting in a complete circuit
`
`breakdown
`
`Ex. 2002, ¶ 108 (emphasis added).
`
`
`33. Metastability is typically encountered in digital systems when the
`
`input to a clocked register or latch changes nearly simultaneously with the active
`
`clock transition. This is a well-known problem and one I have analyzed many
`
`times while designing digital systems. Based on my experience, Dr. Pedram’s
`
`concern is completely misplaced with regard to this design because the
`
`AAPA/Majcherczak combination circuit has no storage elements or latches at all.
`
`In this case, there is no need to simulate or analyze anything related to
`
`18
`
`
`
`metastability because there is no clock that could transition while an input is
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`changing.
`
`
`
`III. The Steinaker/Doyle/Park combination is motivated and not dis-
`couraged
`
`A. The number of transistors in the combination is not
`increased or any increase is insignificant
`
`34. Dr. Pedram states:
`
`Finally, Apple does not consider or address the
`
`disadvantages that would result from implementing
`
`Steinacker’s inverter with the CMOS-TTL interface of
`
`Doyle. A conventional inverter includes just two (2)
`
`FETs. e.g., Ex. 1006 (Doyle) at Fig. 2A. Apple’s
`
`proposed combination replaces this conventional
`
`inverter with a circuit having nine (9) FETs and a
`
`resistor. See, e.g., Petition at 25. The seven additional
`
`FETs required under Apple’s combination would result
`
`in additional layout area, input-to-output delay, and
`
`switching power consumption that would discourage the
`
`POSA from making the proposed combination.
`
`Ex. 2002, ¶ 108 (emphasis added).
`
`
`35. First, Steinaker does not say that a conventional inverter is preferred.
`
`Instead, Steinaker Figure 1 shows an inverter with a hysteresis symbol inside; the
`
`Doyle circuit is such an inverter with hysteresis. Thus, the notion that the
`
`proposed combination adds transistors is incorrect.
`
`19
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`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`
`
`Annotated excerpt of Figure 1 of Steinacker showing an inverter with hysteresis
`for voltage level detector 5.
`
`
`
`36. Moreover, as Dr. Pedram acknowledged, a typical Schmitt trigger,
`
`such as Steinacker explicitly recommends, has on the order of 8 transistors. Ex.
`
`1017, 143:12-18. Thus, the Doyle circuit is in line with this (having seven
`
`transistors before the obvious combination with Park, and having nine transistors
`
`after employing Park’s forced stack technique to reduce power consumption).
`
`37. Second, even if a few more transistors were required, those few
`
`transistors would have represented an insignificant area addition to an integrated
`
`circuit in the timeframe of interest. By 2005, four years before the ’674 priority
`
`date, integrated circuits with over 100 million transistors were available. APPLE-
`
`1025, 25. Adding a few more transistors to the power-on circuit of such a device
`
`would have had little impact on the desirability of using that circuit.
`
`20
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`B. Motivation to utilize Doyle’s inverter with hysteresis as
`Steinacker’s voltage detector 5
`
`38. Steinacker describes that “the voltage level detector 5 is in the form of
`
`a Schmitt trigger with an inverting output. However, it is likewise conceivable for
`
`the voltage level detector 5 to be in the form of an inverter circuit, a comparator
`
`circuit or comparable circuits.” Ex. 1005, 4:49-53 (emphasis added). As I
`
`explained in my Original Declaration, Steinacker assumes a POSITA capable of
`
`identifying a Schmitt trigger, inverter circuit, a comparator circuit or comparable
`
`circuit to implement the voltage detector 5. Ex. 1003, ¶ 93.
`
`39. As I noted above, Steinacker provides further guidance to direct a
`
`POSITA in the selection of an appropriate voltage level detector 5. Specifically,
`
`Steinaker Figure 1 shows an inverter with a hysteresis symbol inside, which would
`
`have led a POSITA seeking to implement Steinacker’s circuit arrangement of
`
`Figure 1 to select a Schmitt trigger, inverter, comparator, or comparable circuit that
`
`has both an inverting output and hysteresis.
`
`40. A POSITA seeking an inverter circuit with hysteresis for use as a
`
`voltage level detector in a multiple supply voltage system would naturally have
`
`considered Doyle’s inverter circuit, which satisfies each of these requirements.
`
`21
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`Doyle describes a multiple supply voltage system5 that uses an inverter with a
`
`feedback circuit to perform voltage level detection with hysteresis. See APPLE-
`
`1006, 2:37-46, 3:7-14. Specifically, Doyle’s improved inverter of FIG. 2 includes
`
`a “second P-channel pullup MOSFET . . . provided in parallel with the first, and
`
`has its gate coupled to a feedback signal produced by a second CMOS inverting
`
`stage in order to provide a ‘polarized’ hysteresis characteristic of the MOS level
`
`shifting circuit, making the trip point or switching point of the MOS level shifting
`
`circuit relatively independent of the power supply voltage applied across the
`
`CMOS level shifting circuit.” APPLE-1006, 3:7-14 (emphasis added). The
`
`feedback transistor 18 in FIG. 2 is the source of the hysteresis effect, and provides
`
`Doyle’s advantage of a “stable trip point or switching point.” See id.
`
`41. As I noted in paragraphs 52 and 53 of my Original Declaration, a
`
`POSITA would have understood how the teachings of Doyle were specifically
`
`applicable to the role of the voltage level detector 5 in Steinacker. In particular, I
`
`noted that hysteresis is especially desirable for detection of power voltages because
`
`these voltages change slowly, and the processor should remain reset until the input
`
`voltage is reliably above the higher threshold. Ex. 1003, ¶ 51. In fact, Steinacker
`
`
`5 The TTL and CMOS logic levels referred to in Doyle are based on two different
`
`standard voltages and would ordinarily rely upon different power supplies.
`
`22
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`specifically notes that it sought for its circuit to operate effectively even where the
`
`power supplies exhibit “slow turn-on profiles.” Ex. 1005, 3:12-14. Doyle
`
`similarly assumed and optimized his circuit for power supplies with slow turn-on
`
`profiles. See Ex. 1006, 6:28-41. It was well known that signals with slow turn-on
`
`profiles were more prone to being affected by noise. APPLE-1024, 87-89. Thus, a
`
`POSITA would have had additional motivation to select Doyle’s improved inverter
`
`when implementing Steinacker’s voltage detector 5, because Doyle described its
`
`improved inverter as providing “relatively high noise immunity.” See Ex. 1006,
`
`2:14-26.
`
`42. The additional benefit of Doyle’s inverter as being “very independent
`
`of temperature” (realized via resistor R) is also relevant to Steinacker, because
`
`Steinacker intended its circuit arrangement to be used in mobile communication
`
`devices (see APPLE-1005, 1:18-20, 3:19-22) and it was well known that a
`
`“[m]obile phone is subjected to very harsh environmental conditions compared to
`
`many commercial products” including “temperature and or humidity extremes and
`
`dusty conditions.” APPLE-1019, 2, 5. That Doyle’s patent application was filed
`
`in 1986 would have been of no consequence to a POSITA, as Steinacker gave no
`
`requirement that its voltage level detector be a contemporaneous design. (To the
`
`contrary, the original Schmitt trigger specifically mentioned in Steinacker was
`
`invented in 1934.) Further, Doyle’s description of its improved inverter as a “level
`
`23
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`shifting circuit” would have only further motivated a POSITA to use Doyle’s
`
`inverter in Steinacker, where the voltage level detector 5 crosses two voltage
`
`domains. See APPLE-1002, 4:45-49. In light of all these teachings, I believe that
`
`a POSITA would have been motivated to use Doyle’s improved inverter when
`
`implementing Steinacker’s voltage detector 5, and would have had a reasonable
`
`expectation of success when doing so.
`
`C. Motivation to utilize Park’s forced stack technique
`
`43. Dr. Pedram incorrectly states that:
`
`But even if the POSA would have been motivated to use
`
`the teachings of Park to lower leakage current, he would
`
`not have done so using the forced stack circuit from Park.
`
`Rather, the POSA would have used the superior “sleepy
`
`stack” technique that is the focus of Park. generally Ex.
`
`1007 (Park), titled “Sleepy Stack Leakage Reduction.”
`
`Ex. 2002, ¶ 110. I disagree for at least the following reasons.
`
`
`44. When seeking to integrate Doyle’s improved inverter with hysteresis
`
`into Steinacker’s circuit arrangement 1 as voltage level detector 5, a POSITA
`
`would have been mindful of Steinacker’s goal of using its circuit arrangement of
`
`Figure 1 in applications “with a limited resource for the second supply voltage, for
`
`example a battery or a storage battery” and applications “with limited current
`
`resources, such as in the case of mobile electronic appliances.” APPLE-1005,
`
`24
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`3:19-22, 3:48-54. The POSITA would have correspondingly considered well-
`
`known ways to conserve power.
`
`45. The Park reference describes several techniques for lowering the
`
`power consumption of CMOS circuits for use in mobile applications such as the
`
`mobile radio technology described in Steinacker. APPLE-1007, 1. According to
`
`Park, “[t]oday’s focus on low power is not only because of the recent growing
`
`demands of mobile applications. Even before the mobile era, power consumption
`
`has been a fundamental problem.” Ex. 1007, 1 (emphasis added). Among the
`
`different types of CMOS circuits for which Park provides power reducing
`
`techniques are inverters, like Doyle’s. APPLE-1007, 2, FIG. 1. Thus, the power
`
`reducing techniques described by Park are explicitly intended for both the
`
`Steinacker (which sought to lower power consumption so its circuit could be used
`
`in mobile devices) and Doyle (which taught an improved inverter) applications.
`
`46. Park describes several techniques for reducing power consumption of
`
`an inverter, including a previously known “forced stack” technique shown in FIG.
`
`1a and a new proposed “sleepy stack” technique shown in FIG. 2. See APPLE-
`
`1007, 2-3. As I explained in my Original Declaration, a POSITA, reading Park,
`
`would have been motivated to implement Park’s forced stack technique in order to
`
`reduce power consumption by lowering leakage current. See Ex. 1003, ¶¶ 111-
`
`112.
`
`25
`
`
`
`Supplemental Declaration of Robert W. Horst, Ph.D.
`U.S. Patent No. 8,063,674
`
`47. Park teaches that the forced stack technique includes four transistors
`
`with their gates all driven by the same input signal A. See APPLE-1007, 2, FIG.
`
`1(a).
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