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`Paper No. 7
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
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`DELL INC.
`
`Petitioner,
`
`v.
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`ALACRITECH INC.,
`
`Patent Owner
`________________
`
`Case IPR2018-01307
`U.S. Patent 8,805,948
`________________
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`PATENT OWNER’S RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
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`I.
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`II.
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`U.S. Patent No. 8,805,948
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION .................................................................................1
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`OVERVIEW OF THE ’948 PATENT ..................................................2
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`A.
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`B.
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`The ’948 Patent Specification .....................................................2
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`The ’948 Patent Claims ...............................................................7
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`III.
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`PROSECUTION HISTORY OF THE ’948 PATENT .........................7
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART .................................8
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`A.
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`B.
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`C.
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`Thia, A Reduced Operation Protocol Engine (ROPE) for
`a Multiple-layer Bypass Architecture (1995) (“Thia”) ...............8
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`Tanenbaum, Computer Networks, 3rd ed. (1996)
`(“Tanenbaum”) ......................................................................... 13
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`Stevens, TCP/IP Illustrated Volume 2: The
`Implementation (“Stevens”) (Ex. 1063) ................................... 16
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`V.
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`CLAIM CONSTRUCTION ............................................................... 17
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`VI. STEVENS IS NOT AVAILABLE AS PRIOR ART ..................... 18
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`VII. PETITIONER HAS NOT SUFFICIENTLY SHOWN A
`MOTIVATION TO COMBINE THIA WITH TANENBAUM
`OR STEVENS .................................................................................... 20
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`VIII. PETITIONER HAS NOT SHOWN A DISCLOSURE OF
`PACKET PROCESSING FOR THE “CHECKING”
`LIMITATIONS OF THE CHALLENGED CLAIMS ....................... 23
`
`IX. THE BOARD SHOULD DENY THE PETITION BECAUSE
`IT IS TIME BARRED UNDER 35 U.S.C. § 315(B) AND
`RECENT PRECEDENT .................................................................... 30
`
`A.
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`B.
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`C.
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`D.
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`Procedural Background ............................................................ 33
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`Burden of Proof ........................................................................ 37
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`Dell, CenturyLink, and Wistron Benefit From Intel’s
`IPRs and Are Real Parties in Interest ....................................... 37
`
`The Established Relationships Among Intel, Dell,
`CenturyLink, and Wistron Justify the Finding of Real
`Parties-in-Interest ..................................................................... 39
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`E.
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`F.
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`Finding Dell, CenturyLink, and Wistron Are Real
`Parties-in-Interest Is Consistent with Legislative Intent .......... 41
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`Patent Owner Is Not Able to Amend Claims Due to
`Petitioner’s Late Filing ............................................................. 43
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`G.
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`Intel’s Independent Interest Is Not a Defense .......................... 43
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`X.
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`CONCLUSION .................................................................................. 45
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`TABLE OF AUTHORITIES
`
`Page
`
`Cases
`Applications in Internet Time, LLC v. RPX Corp.,
`897 F.3d 1336 (Fed. Cir. 2018) ................................... 32, 35, 37, 39, 41, 44
`Beckman Instruments v. LKB Produkter AB,
`892 F.2d 1547 (Fed. Cir. 1989) ................................................................... 9
`Cisco Systems, Inc. v. C-Cation Techs., LLC,
`IPR2014-00454 (PTAB Aug. 29, 2014) ................................................... 19
`Coalition for Affordable Drugs IV LLC v. Pharmacyclics, Inc,
`IPR2015-01076, slip op. 6 (PTAB Oct.19, 2015) ..................................... 19
`In re CSB-System International, Inc.,
`832 F.3d 1335 ............................................................................................ 43
`Dynamic Drinkware LLC v. Nat’l Graphics, Inc.,
`800 F.3d 1375 (Fed. Cir. 2015) ................................................................. 20
`Intel v. Alacritech,
`IPR2017-01395 (PTAB November 22, 2017) .......................................... 18
`Symbol Techs. Inc. v. Opticon Inc.,
`935 F.2d 1569, 19 USPQ2d 1241 (Fed. Cir. 1991)..................................... 9
`Wi-Fi One, LLC v. Broadcom Corp.,
`878 F.3d 1364 (Fed. Cir. 2018) ................................................................. 30
`Wi-Fi One, LLC v. Broadcom Corp.,
`887 F.3d 1329 (Fed. Cir. 2018) ................................................................. 32
`Worlds Inc. v. Bungie, Inc.,
`Case. Nos. 2017-1481, -- F.3d -- (Fed. Cir. Sept. 7, 2018) ....................... 32
`
`
`
`Statutory Authorities
`Fed. R. Civ. P. 24 .................................................................................... 33, 38
`
`Rules and Regulations
`35 U.S.C. § 21 ................................................................................................. 1
`35 U.S.C. § 313 ............................................................................................... 1
`35 U.S.C. § 312(a)(2) .................................................................................... 32
`35 U.S.C. § 314(a) ........................................................................................ 45
`35 U.S.C. § 315(b) ............................................................ 1, 30, 32, 36, 43, 45
`35 U.S.C. § 315(c) ............................................................................ 30, 33, 45
`37 C.F.R. § 42.107(a) ..................................................................................... 1
`37 CFR §§ 42.8(b)(1), 42.104(a) .................................................................. 32
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`Other Authorities
`H.R. Rep. No. 112–98 (2011) ....................................................................... 41
`Office Patent Trial Practice Guide,
`77 Fed. Reg. 48,756, 48,759 (Aug. 14, 2012) ........................................... 32
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`PATENT OWNER’S LIST OF EXHIBITS
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`Ex. 2051
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`Intel’s Motion to Intervene Dell
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`Ex. 2052
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`Intel’s Motion to Intervene CenturyLink
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`Ex. 2053
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`Intel’s Motion to Intervene Wistron
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`Ex. 2054
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`Kyriacou Declaration
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`Ex. 2055
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`Cavium Motion to Intervene Dell
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`Ex. 2056
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`Belli Declaration
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`Ex. 2057
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`Petition History
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`Ex. 2058
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`Alacritech v. Dell docket
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`Ex. 2059
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`Alacritech v. Wistron docket
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`Ex. 2060
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`Alacritech v. CenturyLink docket
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`I.
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`INTRODUCTION
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`Petitioner Dell Inc. (“Dell”) filed its Petition (Paper 2, IPR 2018-01307,
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`hereinafter “Petition”) requesting Inter Partes Review (“IPR”) of claims 1, 3, 6-8,
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`17, 19, and 21-22 of U.S. Patent No. 8,805,948 (“the ’948 patent”). Pursuant to 35
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`U.S.C. § 313 and 37 C.F.R. § 42.107(a), Patent Owner Alacritech, Inc.
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`(“Alacritech”) files this Preliminary Response with arguments and information as
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`to why the Board should not institute review on Dell’s Petition.1
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`Dell’s Petition is time barred because it was filed more than one year after
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`the date on which Alacritech’s Complaint for infringement was served on Dell
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`Corporation. See 35 U.S.C. § 315(b). Allowing Dell to proceed with this Petition
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`would therefore violate the one-year bar requirement.
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`Other reasons support denial here as well. First, Dell failed to cure the
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`deficiencies in Intel’s petition surrounding the Stevens reference to show that it is
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`available prior art in this proceeding. To wit, Dell relies primarily on the identical
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`Stansbury exhibit (Ex. 1063) and identical arguments in support of its alleged
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`public availability in Intel’s petition. See Section VI. Dell’s new evidence does
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`not remedy the problems with Stevens or the Stansbury exhibit. Accordingly, Dell
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`1 This submission is timely under 35 U.S.C. § 21, as it is filed within three months
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`following the July 24, 2018 accorded filing date. (Paper 4, IPR 2018-01307.)
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`still has not made a sufficient threshold showing that Stevens qualifies as a
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`“printed publication” in this proceeding.
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`Second, Dell has not sufficiently shown a motivation to combine Thia with
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`Tanenbaum or Stevens, nor the claimed “check[ing] . . . the packets” limitations in
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`the relied-upon references. See Sections VII - VIII. These deficiencies infect
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`Dell’s entire Petition, and the appropriate remedy is to deny institution.
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`For all these reasons, Dell’s Petition does not give rise to a reasonable
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`likelihood that Dell will prevail with respect to any challenged claim of ’948
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`patent, and the Board should therefore deny institution of review.
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`II. OVERVIEW OF THE ’948 PATENT2
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`A. The ’948 Patent Specification
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`The ’948 patent is directed to accelerated network processing using an
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`intelligent network interface card (INIC) that provides “a fast-path that avoids host
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`protocol processing for most large multipacket messages, greatly accelerating data
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`communication.” Ex. 1001 at Abstract. As explained in the patent background,
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`2 The ’948 patent is assigned to Alacritech and is the subject of co-pending
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`litigation, Alacritech, Inc. v. CenturyLink, Inc., 2:16-cv-00693-JRG-RSP (E.D.
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`Tex.); Alacritech, Inc. v. Wistron Corp., 2:16-cv-00692-JRG-RSP (E.D. Tex.); and
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`Alacritech, Inc. v. Dell Inc., 2:16-cv-00695-RWS-RSP (E.D. Tex.), which were all
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`consolidated for pre-trial purposes (“the Litigations”).
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`when a conventional NIC prepares to send data from a first host to a second host,
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`“some control data is added at each layer of the first host regarding the protocol of
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`that layer, the control data being indistinguishable from the original (payload) data
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`for all lower layers of that host.” Id. at 2:39-42. For example,
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`an application layer attaches an application header to the payload data and
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`sends the combined data to the presentation layer of the sending host, which
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`receives the combined data, operates on it and adds a presentation header to
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`the data, resulting in another combined data packet. The data resulting from
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`combination of payload data, application header, and presentation header is
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`then passed to the session layer, which performs required operations
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`including attaching a session header to the data and presenting the resulting
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`combination of data to the transport layer. This process continues as the
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`information moves to lower layers, with a transport header, network header,
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`and data link header and trailer attached to the data at each of those layers,
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`with each step typically including data moving and copying, before sending
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`the data as bit packets over the network to the second host.
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`Id. at 2:42-57.
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`This process of adding a layer header to the data from the preceding layer is
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`sometimes referred to as “encapsulation” because the data and layer header is
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`treated as the data for the immediately following layer, which, in turn, adds its own
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`layer header to the data from the preceding layer. Each layer is generally not
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`aware of which portion of the data from the preceding layer is the preceding layer
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`header of user data; as such, each layer treats the data it receives from the
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`preceding layer as a generic payload. Id.
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`On the receiving side, the receiving host generally performs the reverse of
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`the sending process, beginning with receiving the bit packets from the network. Id.
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`at 2:58-60. Headers are removed, one at a time, and the received data is processed,
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`in order, from the lowest (physical) layer to the highest (application) layer before
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`transmission to a destination within the receiving host (e.g., to the operating system
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`space where the received data may be used by an application running on the
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`receiving host). Id. at 2:60-63. Each layer of the receiving host recognizes and
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`manipulates only the headers associated with that layer, since to that layer the
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`higher layer header data is included with and indistinguishable from the payload
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`data. Id. at 2:63-66. “Multiple interrupts, valuable central processing unit (CPU)
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`processing time and repeated data copies may also be necessary for the receiving
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`host to place the data in an appropriate form at its intended destination.” Id. at
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`2:66-3:3.
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`The host CPU processes the data by constructing (transmit side) or
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`destructing (receive side) the packet. The host CPU must be interrupted at least
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`one time per layer and, in response, the host CPU processes each layer, which
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`typically involves a copy and data manipulation operation (for example a
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`checksum computation operation). An interrupt is a signal to the processor emitted
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`by hardware or software indicating an event that needs immediate attention. An
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`interrupt alerts the processor to a high-priority condition requiring the interruption
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`of the current code the processor is executing. Id. This process involved with
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`traditional network interface cards results in “repeated copying and interrupts to
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`the CPU” of the host computer. Id. at 3:59-62. When the host CPU is interrupted,
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`it generally must stop all other tasks it is currently working on, including tasks
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`completely unrelated to the network processing. Frequent interrupts to the host
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`CPU can be very disruptive to the host system generally and cause system
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`instability and degraded system performance. Id.
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`The invention of the ’948 patent allows “data from the message to be
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`processed via a fast-path which accesses message data directly at its source or
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`delivers it directly to its intended destination.” Id. at 3:53-57. The fast-path
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`“bypasses conventional protocol processing of headers that accompany the data”
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`and “employs a specialized microprocessor designed for processing network
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`communication, avoiding the delays and pitfalls of conventional software layer
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`processing, such as repeated copying and interrupts to the CPU.” Id. at 3:57-62.
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`One embodiment of the fast-path is shown in Figure 6 of the ’948 patent,
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`which is reproduced below. In this embodiment, the INIC performs at least the
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`network and transport layer processing (e.g., IP and TCP layer processing in
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`TCP/IP), freeing up the CPU on the host (“client”) computer to do other tasks. The
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`fast-path also reduces or eliminates the number of interrupts sent to the CPU on the
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`host/client. An embodiment of the more traditional “slow-path” is also shown,
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`where the host/client is responsible for the IP and TCP layer processing. In the
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`slow-path, the CPU on the host/client is interrupted at least one time for each layer
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`for processing.
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`Advantageously, the claimed invention allows for more efficient network
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`processing by relieving the host CPU of per-frame processing and reducing the
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`number of interrupts. Id. at 9:1-5. For fast-path communications, only one
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`interrupt occurs at the beginning and end of an entire upper-layer message
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`transaction, and “there are no interrupts for the sending or receiving of each lower
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`layer portion or packet of that transaction.” Id. at 9:5-10. As stated above, the
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`claimed arrangement allows for enhanced network and system performance, faster
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`data throughput, increased system stability, and an overall better user experience.
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`B.
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`The ’948 Patent Claims
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`The ’948 patent includes three independent claims. Notably, for this
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`Preliminary Response, both independent claims 1 and 17, which are at issue in the
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`Petition recite, inter alia, “checking […] whether the packets have certain
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`exception conditions, including […] whether the packets are IP fragmented, […]
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`have a FIN flag set, [and/or] […] are out of order.” Id. at 19:43-20:7, 22:1-25.
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`As explained in Section VIII, this claimed feature is not found in any of the
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`references cited by Petitioner. Dependent claims 3, 6-8, 19, 21 and 22, all of
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`which are also at issue in the Petition, incorporate the same limitation missing in
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`independent claims 1 and 17.
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`III. PROSECUTION HISTORY OF THE ’948 PATENT
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`The ’948 patent was filed on September 26, 2013 as Application No.
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`14/038,297, which was a continuation of Application No. 09/692,561, filed
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`October 18, 2000, which was a continuation of Application No. 09/067,544, filed
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`April 27, 1998, which claims the benefit of Provisional Application No.
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`60/061,809, filed on October 14, 1997.
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`The ’948 patent was subject to a thorough examination by Examiner
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`Moustafa M. Meky, who allowed the application on June 20, 2014 after
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`considering references (including Thia and Tanenbaum) disclosed by the Applicant
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`and after conducting the Examiner’s own prior art search on June 16, 2014. Ex.
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`1002 at .111-.149. In connection with the allowed claims, the Examiner stated:
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`None of the prior art of record taken singularly or in combination teaches or
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`suggests a network interface of a host computer for checking whether
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`received packets have a certain exception conditions, including whether
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`the packets are IP fragmented, have a FIN flag set, or out of order;
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`processing any of the received packet that have the exception conditions,
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`and storing payload data of the received packets that do not have any of
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`the exception conditions in a buffer of the host computer and without any
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`TCP header stored between the payload data of the received packets.
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`Ex. 1002 at .117 (emphasis added). An Issue Notification was mailed on July 23,
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`2014, and the ‘948 patent issued on August 12, 2014.
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`IV. OVERVIEW OF THE ALLEGED PRIOR ART
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`As described above, Dell relies on Thia, Tanenbaum, and Stevens, which
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`Dell has not established as prior art. These references, each alone or in
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`combination, fail to teach or suggest all the limitations recited in the claims of the
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`’948 patent. For example, the references are completely silent as to bypass
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`exception conditions that involve checking whether the packets are IP fragmented.
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`The sections below summarize the references and underscore their shortcomings.
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`A. Thia, A Reduced Operation Protocol Engine (ROPE) for a
`Multiple-layer Bypass Architecture (1995) (“Thia”)
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`Thia appears on the face of the ’948 patent under “References Cited” and
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`was initialed by the Examiner in an Information Disclosure Statement (IDS) dated
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`June 15, 2014. Ex. 1002 at .120-.144. Thia was therefore already considered and
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`allowed over by the Examiner during the prosecution of the ’948 patent.
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`As an initial matter, Thia presents a “feasibility study for a new approach to
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`hardware assistance” and the “final step of generating a chip layout for fabrication
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`and fault analysis was not performed.” Ex. 1015 at .002 and .008. Since Thia at
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`best discloses an inoperative device, it is a non-enabling reference. A non-
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`enabling reference is prior art under 35 U.S.C. § 103 only “for all that it teaches.”
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`Beckman Instruments v. LKB Produkter AB, 892 F.2d 1547, 1551, 13 USPQ2d
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`1301, 1304 (Fed. Cir. 1989); see Symbol Techs. Inc. v. Opticon Inc., 935 F.2d
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`1569, 1578, 19 USPQ2d 1241, 1247 (Fed. Cir. 1991). The feasibility study
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`discloses at a high level the idea of offloading session and transport layer
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`processing to a Reduced Operation Protocol Engine (“ROPE”) chip, but does not
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`teach many of the implementation details.
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`Thia describes a bypass stack such as the ROPE chip that provides a
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`hardware “fast path” for bulk data transfer. Id. at .002-.003.
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`Id. at .003, Fig. 1. Regarding the receive bypass test, Thia merely discloses a test
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`that matches headers of incoming data packets with a template using header
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`prediction:
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`Id. at .003. Thia does not address exception conditions relating to the bypass test.
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`Table 1 of Thia “identifies procedures which are strong candidates for
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`implementation in the bypass chip, and those which are better handled by the host,
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`during the data transfer phase.” Id. at .006.
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`Id. As shown in the table, Thia identifies bypassable functions in the presentation
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`layer, the session layer, the transport layer, and all three of those layers. Thia,
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`however, does not address the bypass test or bypassable functions in relation to the
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`network layer, which is where fragmentation/segmentation occurs. Indeed, Thia
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`assumes that any packets that have been fragmented have been reassembled at the
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`receiver before being passed to the Transport layer. Id. at .013-.014 (stating: “In
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`an ATM system we assume that the segmentation and reassembly or SAR
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`operation would also be in hardware, since it is done frequently”; “The
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`Segmentation and Reassembly sublayer of the ATM adaption layer is a good place
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`for [segmentation/reassembly] functions”).
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`B.
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`Tanenbaum, Computer Networks, 3rd ed. (1996) (“Tanenbaum”)
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`Tanenbaum is the third edition of a textbook relating to computer networks.
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`As acknowledged by Petitioner, it too was already considered by the Examiner
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`during prosecution of the ’948 patent, which was found to be allowable over
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`Tanenbaum. Petition at n.5. On pages 583-586, Tanenbaum describes “fast”
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`transport protocol data unit (“TPDU”) processing. Ex. 1006 at .583-86. On the
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`sending side, Tanenbaum notes that “[i]n the normal case, the headers of
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`consecutive data TPDUs are almost the same.” Id. at .583. In view of this
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`observation, a “prototype header” is defined. Id. In order to construct a packet for
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`transmission, at the TCP layer, the TCP prototype header is copied into the output
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`buffer, the sequence number is filled in, the TCP checksum is computed, and the
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`sequence number is incremented in memory. Id. at .584. Then, the TCP header
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`and data is handed “to a special IP procedure” at the IP layer, where the IP
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`prototype header is copied into the output buffer, the “Identification” field is
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`inserted, and the IP checksum is computed. Id. The packet is then ready for
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`transmission.
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`On the receive side, a “connection record” is stored in a hash table for
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`lookup (or the last record is tried first). Id. at .585. Then conditions for a special
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`“fast path” TCP procedure are checked:
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`The TPDU is then checked to see if it is a normal one: the state is
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`ESTABLISHED, neither side is trying to close the connection, the TPDU is a
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`full one, no special flags are set, and the sequence number is the one
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`expected. These tests take just a handful of instructions. If all conditions are
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`met, a special fast path TCP procedure is called.
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`Id. at 585. The connection record is updated, and data is copied to the user. Id.
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`During the copy process, the fast path computes the checksum. Id. Tanenbaum
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`explains that this general scheme of first making a quick check to see if the header
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`is what is expected, and having a special procedure to handle that case, is called
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`“header prediction.” Id. Tanenbaum, however, discloses conditions that relate to
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`checking TPDUs, i.e. transport protocol data units, and not packets. The test is
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`performed at the transport layer and not the network layer where packets are
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`processed to generate TPDUs to be passed on to the transport layer.
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`Further, Tanenbaum teaches away from performing any TCP/IP protocol
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`processing on anything other than the host CPU. Tanenbaum is aware of the
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`possibility of a transport entity being on a network interface card:
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`The hardware and/or software within the transport layer that does the work
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`is called the transport entity. The transport entity can be in the operating
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`system kernel, in a separate user process, in a library package bound into
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`network applications, or on the network interface card.
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`Id. at .498 (bold in original). Petitioner points to this to assert that Tanenbaum
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`“teaches that the transport entity may be built into the network interface card.”
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`Petition at 45. However, Tanenbaum clearly teaches away from doing so:
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`A tempting way to go fast is to build fast network interfaces in hardware.
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`The difficulty with this strategy is that unless the protocol is exceedingly
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`simple, hardware just means a plug-in board with a second CPU and its own
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`program. To avoid having the network coprocessor be as expensive as the
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`main CPU, it is often a slower chip. The consequence of this design is that
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`much of the time the main (fast) CPU is idle waiting for the second (slow)
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`CPU to do the critical work. It is a myth to think that the main CPU has
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`other work to do while waiting. Furthermore, when two general-purpose
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`CPUs communicate, race conditions can occur, so elaborate protocols are
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`needed between the two processors to synchronize them correctly. Usually,
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`the best approach is to make the protocols simple and have the main CPU do
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`the work.
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`Id. at .588-89.
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`C.
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`Stevens, TCP/IP Illustrated Volume 2: The Implementation
`(“Stevens”) (Ex. 1063)
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`Stevens is a reference on the implementation of TCP/IP.3 Ex. 1013 at .023.
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`Stevens discloses header prediction in which “[i]f TCP is receiving data, the next
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`expected segment for this connection is the next in-sequence data segment. . . . [A]
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`small set of tests determines if the next expected segment has been received, and if
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`so, it is handled in-line, faster than the general processing.” Id. at .961. Stevens
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`discusses six conditions for a segment to be the next in-sequence data segment:
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`3 Stevens is not available as prior art in this proceeding. Although Petitioner
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`alleges “Stevens[] was published no later than April 7, 1995 and is prior art under
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`102(b),” Petitioner has not provided sufficient evidence that Stevens qualifies as a
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`“printed publication” against the challenged ’948 patent claims. See Section VI.
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`Id. at .962-63. However, as acknowledged in the Petition, “[t]he code above is
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`implemented at the TCP layer, and thus, does not check for IP fragmentation
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`because the IP layer reassembles fragmented IP packets.” Petition at 55. Further,
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`Stevens does not address offloading protocol processing to a network interface
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`chip.
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`V. CLAIM CONSTRUCTION
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`The Petition does not assert that the challenged claims require express
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`construction by the Board, and Patent Owner agrees.
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`VI. STEVENS IS NOT AVAILABLE AS PRIOR ART
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`In IPR2017-01395, the Board ruled not once, but twice, that the Stansbury
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`exhibit (Ex. 1063) that Petitioner submitted in an attempt to show that Stevens was
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`available as prior art in that proceeding is deficient, and that therefore Stevens was
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`not shown to be prior art. See Intel v. Alacritech, IPR2017-01395, slip op. 7-8
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`(PTAB November 22, 2017) (Paper 8 – Decision on Institution), slip op. 3-5
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`(PTAB January 25, 2018) (Paper 13 – Decision on Rehearing). In fact, the Board
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`went a step further on at least some of Intel’s new arguments and evidence in its
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`decision on rehearing: “even considering Petitioner’s new arguments and evidence
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`(Exs. 1095 and 1096), we still find the evidence of record insufficient to
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`demonstrate a reasonable likelihood that Stevens2 qualifies as a printed publication
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`prior art reference.” (Paper 12, IPR2017-01395, at 7.)
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`In this proceeding, Petitioner submits the identical Stansbury exhibit (Ex.
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`1063)4 and identical arguments simply hoping for a different result the third time
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`around, without making any changes to the exhibit to address the Board’s concerns
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`with it. See Intel v. Alacritech, IPR2017-01395, slip op. 7-8 (PTAB November 22,
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`2017) (Paper 8 – Decision on Institution) (discussing, among other things, failure
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`to describe indexing and cataloging), slip op. 3-5 (PTAB January 25, 2018) (Paper
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`13 – Decision on Rehearing) (discussing, among other things, failure to describe
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`4 Compare Petition Ex. 1063 with Ex. 1063 in IPR2017-01395 .
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`indexing and cataloging and use of the phrase “as best [she] can determine”). For
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`example, the Petition (and the Stansbury exhibit) fails to discuss any details of
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`indexing and cataloging of Stevens and Ms. Stansbury offers the same uncertain
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`opinion on the public availability of Stevens by saying “As best I can determine,
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`the publication was publicly available at the Cornell University Library as of April
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`7, 1995.” Ex 1063 at 1. (Emphasis added.)
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`Dell’s attempts to remedy the defects in the Stansbury exhibit by identifying
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`a handful of new exhibits (Ex. 1100, Ex. 1103-1109) that cite or refer to Stevens
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`generically.5 However, the Petition does not present any evidence or argument to
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`satisfy the “threshold showing that [any of] the [Ex. 1100, Ex. 1103-1109]
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`reference[s] is a prior art ‘printed publication.’” Coalition for Affordable Drugs IV
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`LLC v. Pharmacyclics, Inc, IPR2015-01076, slip op. 6 (PTAB Oct.19, 2015)
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`(Paper 33) (Decision Denying Institution); see also Cisco Systems, Inc. v. C-Cation
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`Techs., LLC, IPR2014-00454, slip op. 7-10 (PTAB Aug. 29, 2014) (Paper 12)
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`(Decision Denying Institution) (Informative, Expanded Panel) (Information
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`contained in exhibits or portions of exhibits, but not discussed, is not incorporated
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`5 Dell also relies on a quote from U.S. Provisional Application 60/61809
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`referencing Stevens, which, in any event, is cumulative of its other new exhibits.
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`See Petition at 18.
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`merely by the exhibits’ presence in the record.). None of these documents is
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`meaningfully discussed, explained or authenticated and there is no proof of their
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`dates or value in fixing the defects in the Stevens and the Stansbury exhibit. Mere
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`citation Stevens fails to provide sufficient evidence and assurance of identity and
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`publication. See, e.g. Ex. 1102.010 (citing to “Stevenson”).
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`Accordingly, Dell fails to make a sufficient threshold showing that Stevens
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`is available as prior art in this proceeding, as required under Dynamic Drinkware
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`LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1379 (Fed. Cir. 2015) (“Dynamic
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`Drinkware”) and its progeny, and the Board should deny institution.
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`VII. PETITIONER HAS NOT SUFFICIENTLY SHOWN A MOTIVATION
`TO COMBINE THIA WITH TANENBAUM OR STEVENS
`
`The Petition fails to establish that a person skilled in the art would have had
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`the requisite motivation to combine Thia with either Tanenbaum or Stevens at the
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`time of the challenged ’948 patent claims. This deficiency affects all challenged
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`claims, and the Board should deny institution for this additional reason.
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`Petitioner asserts that one skilled in the art reading Thia in combination with
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`Tanenbaum would have been motivated to combine because “both are based on
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`Jacobson’s TCP/IP Header Prediction,” and one skilled in the art would have been
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`motivated “to reduce the burden of protocol processing on the host processor such
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`that it may perform other necessary functions.” (Pet.