`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Jentsung Lin
`In re Patent of:
`7,693,002 Attorney Docket No.: 39521-0054IP1
`U.S. Patent No.:
`April 6, 2010
`
`Issue Date:
`Appl. Serial No.: 11/548,132
`
`Filing Date:
`October 10, 2006
`
`Title:
`DYNAMIC WORD LINE DRIVERS AND DECODERS FOR
`MEMORY ARRAYS
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 7,693,002 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`
`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`TABLE OF CONTENTS
`
`I.
`
`4.
`
`REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ............................ 1
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a)................................. 1
`B. Challenge Under 37 C.F.R. § 42.104(b) and Relief Requested ............... 1
`C. LEVEL OF ORDINARY SKILL ............................................................. 2
`D. CLAIM CONSTRUCTION ...................................................................... 3
`1.
`“static precharge state” .................................................................... 3
`2.
`“conditional clock generator” .......................................................... 3
`3.
`“means for decoding a first portion of a memory address of a
`memory array” (claim 11) ............................................................... 5
`“means for selectively providing a clock signal to a selected group
`of wordline drivers based on the first portion of the memory
`address [of a memory array]” (claims 11 and 27) ........................... 5
`“means for decoding a second portion of the memory address”
`(claims 11 and 14) ........................................................................... 6
`“means for activating a particular wordline driver of the selected
`group of wordline drivers according to the second portion of the
`memory address” (claims 11 and 27) .............................................. 6
`“means for applying the second portion of the memory address to
`a shared address line” (claim 14) .................................................... 7
`
`5.
`
`6.
`
`7.
`
`II.
`
`BACKGROUND ............................................................................................. 7
`A. ’002 patent ................................................................................................ 7
`B. Prosecution History ................................................................................... 9
`
`III. APPLICATION OF PRIOR ART TO CHALLENGED CLAIMS ................ 9
`A. Claim 1 is Obvious Over Sato [GROUND-1] .......................................... 9
`Overview of Sato ....................................................................................10
`B. Claim 1 is Obvious Over Asano in view of Itoh [GROUND-2] ............33
`Overview of Asano .................................................................................33
`Overview of Itoh and its Integration with Asano ...................................35
`C. Claims 2-28 and 31-37 Are Obvious Over Sato [GROUND-1]; Claims
`2-17, 20-28, and 31-36 Are Obvious Over Asano in view of Itoh
`[GROUND-2] .........................................................................................51
`
`IV. PAYMENT OF FEES – 37 C.F.R. § 42.103 .................................................81
`
`V.
`
`CONCLUSION ..............................................................................................81
`
`VI. MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1) .........................82
`A. Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1)..............................82
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2) .......................................82
`
`i
`
`

`

`C. Lead And Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) ...................82
`D. Service Information ................................................................................82
`
`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`
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`ii
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`
`
`EXHIBITS
`
`APPLE-1001
`
`U.S. Patent No. 7,693,002 to Jentsung Lin (“the ’002 patent”)
`
`APPLE-1002
`
`Prosecution History of the ’002 patent (“the Prosecution
`History”)
`
`APPLE-1003
`
`Declaration of Dr. Robert Horst, Ph.D
`
`APPLE-1004
`
`Curriculum Vitae of Dr. Horst
`
`APPLE-1005
`
`U.S. Patent No. 4,951,259 to Yoichi Sato (“Sato”)
`
`APPLE-1006
`
`U.S. Patent Pub. No. 2006/0098520 to Toru Asano et al.
`(“Asano”)
`
`APPLE-1007
`
`Kiyoo Itoh, VLSI Memory Chip Design, (Springer 2001)
`(“Itoh”)
`
`APPLE-1008
`
`U.S. Patent No. 5,291,076 to Jeffrey T. Bridges (“Bridges”)
`
`APPLE-1009
`
`Stephen Brown et al., Fundamentals of Digital Logic with
`Verilog Design, (McGraw Hill 2003) (“Brown”)
`
`APPLE-1010
`
`Declaration of Edward G. Faeth (Authentication of APPLE-
`1007 and APPLE-1009)
`
`APPLE-1011
`
`U.S. Patent No. 6,483,771 to Tae-jeen Shin (“Shin”)
`
`APPLE-1012
`
`U.S. Patent No. 5,602,796 to Kenichiro Sugio (“Sugio”)
`
`
`
`iii
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`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`Apple Inc., (“Petitioner” or “Apple”) petitions for Inter Partes Review
`
`(“IPR”) under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42 of claims 1-28 and 31-37
`
`(“the Challenged Claims”) of U.S. Patent No. 7,693,002 (“the ’002 patent”). As
`
`explained in this petition, there exists a reasonable likelihood that Apple will
`
`prevail with respect to at least one of the Challenged Claims.
`
`The Challenged Claims are unpatentable based on teachings set forth in at
`
`least the references presented in this petition. Apple respectfully submits that an
`
`IPR should be instituted, and that the Challenged Claims should be canceled as
`
`unpatentable.
`
`I.
`
`REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a)
`
`Apple certifies that the ’002 Patent is available for IPR. The present petition
`
`is being filed within one year of service of a complaint against Apple in ITC
`
`investigation Mobile Electronic Devices and Radio Frequency and Processing
`
`Components (ITC-337-TA-1093); and Qualcomm Inc. v. Apple Inc., 3:17-CV-
`
`02398 (S.D. Cal.).
`
`Apple is not barred or estopped from requesting this review challenging the
`
`Challenged Claims on the below-identified grounds.
`
`B. Challenge Under 37 C.F.R. § 42.104(b) and Relief
`Requested
`
`Petitioner requests IPR on the gourds in the table below, as explained herein
`
`1
`
`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`and in APPLE-1003, the Declaration of Dr. Robert Horst.
`
`Ground
`
`’002 Patent Claims
`
`Basis for Rejection
`
`Ground 1 1-28, 31-37
`
`§103: Sato
`
`Ground 2 1-17, 20-28, 31-36
`
`§103: Asano in view of Itoh
`
`
`
`Each reference qualifies as prior art to the 10/10/06 (“Critical date”).
`
`Reference
`
`Date
`
`Sato
`
`Asano
`
`Itoh
`
`
`
`8/21/1990 (issued)
`
`11/5/2004 (filed)
`
`2001 (published)
`
`Section
`
`§102(b)
`
`§102(e)
`
`§102(b)
`
`C. LEVEL OF ORDINARY SKILL
`
`The ’002 patent is directed to decoding circuits for semiconductor memories.
`
`The patent specification and figures include CMOS circuits and memory system
`
`block diagrams. A person of ordinary skill in the art (“POSITA”) as of October
`
`10, 2006 would have had at least an undergraduate degree in electrical engineering,
`
`or a related field, and three years of experience in the design of memory systems
`
`and circuits. APPLE-1003, ¶¶27-29. Alternatively, a person of ordinary skill with
`
`less than the amount of experience noted above would have had a correspondingly
`
`greater amount of educational training such a graduate degree in a related field.
`
`See id.
`
`
`
`2
`
`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`D. CLAIM CONSTRUCTION
`
`Unless otherwise noted below, Petitioner submits that all terms should be
`
`given their plain meaning, but reserves the right to respond to any constructions
`
`that may later be offered by the Patent Owner or adopted by the Board. Petitioner
`
`is not waiving any arguments concerning indefiniteness or claim scope that may be
`
`raised in litigation.
`
`1.
`
`“static precharge state”
`
`Claims 18 and 37 recite: “wherein other wordline drivers of the group of
`
`wordline drivers are in a static precharge state.” The evidence most relevant to
`
`construction–e.g., recitations in the specification and expert testimony concerning
`
`plain meaning–leads to a construction of the claim term “static precharge state”
`
`that includes a state in which a fixed voltage level is applied to a wordline driver.
`
`Specifically, when differentiating a “dynamic evaluation state” from a “static
`
`precharge state,” the ’002 patent specification states: “in a static precharge state
`
`(e.g., a fixed voltage level, such [as] a voltage high signal, is applied).” APPLE-
`
`1001, 3:55-57;1 see also 3:52-62; APPLE-1003, ¶¶43-44.
`
`2.
`
`“conditional clock generator”
`
`Claim 2 recites “conditional clock generator to receive the clock signal
`
`and to selectively apply the clock signal to the selected clock output.” Claims
`
`
`1 All emphases added unless otherwise noted.
`
`3
`
`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`3, 9, 13, 20-22, 27, 31, 32, and 37 recite similar language. The evidence most
`
`relevant to construction–e.g., recitations in the specification and expert testimony
`
`concerning plain meaning–leads to a construction of the claim term “conditional
`
`clock generator” that includes a circuit component that applies a clock signal to
`
`one of several output terminals, selectively. Specifically, the ’002 patent
`
`specification explains that a “conditional clock generator 110 receives a clock
`
`signal via the clock input 118 and selectively applies the clock signal to a selected
`
`one of the clock outputs 124, 126, 128 and 130.” APPLE-1001, 3:28-31. In some
`
`cases, a “conditional clock generator 110 may derive the clock outputs 124, 126,
`
`128 and 130 from a single clock.” APPLE-1001, 3:34-36. Based on this
`
`description in the ’002 patent, a POSITA would have understood the conditional
`
`clock generator to operate by either directly applying an input clock signal to one
`
`of the outputs of the conditional clock generator, or by deriving an output clock
`
`signal based on an input clock signal and applying the derived output clock signal
`
`to one of the outputs of the conditional clock generator. APPLE-1001, 3:28-36,
`
`5:31-34; APPLE-1003, ¶¶45-46. In other words, the output of the conditional
`
`clock generator could be a near exact reproduction of the input clock or simply
`
`derived based on the input clock. Id. The proposed construction of a “conditional
`
`clock generator” as a circuit component that applies a clock signal to one of several
`
`output terminals reasonably incorporates both of the ’002 patent’s descriptions of
`
`4
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`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`the term. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004)
`
`(“claim language should be read in light of the specification as it would be
`
`interpreted by one of ordinary skill in the art.”).
`
`3.
`
`“means for decoding a first portion of a memory address
`of a memory array” (claim 11)
`
`This term includes the phrase “means for,” which creates a presumption that
`
`the term is governed by §112 ¶6. Williamson v. CitrixOnline, LLC, 792 F.3d 1339,
`
`1348 (Fed. Cir. 2015) (en banc).
`
`The corresponding structure for “decoding a first portion of a memory address
`
`of a memory array” is described in the ’002 patent as a “decoder.” APPLE-1001,
`
`3:9-28, 3:37-45, 3:62-4:8, 6:12-19, 9:45-52, 9:64-10:27, 11:19-21, 13:2-10; APPLE-
`
`1003, ¶¶47-48. Thus, the corresponding structure is a “decoder.” Id.
`
`4.
`
`“means for selectively providing a clock signal to a
`selected group of wordline drivers based on the first
`portion of the memory address [of a memory array]”
`(claims 11 and 27)2
`
`This term includes the phrase “means for,” which creates a presumption that
`
`the term is governed by §112 ¶6. Williamson, 792 F.3d at 1348.
`
`The corresponding structure for “selectively providing a clock signal to a
`
`selected group of wordline drivers based on the first portion of the memory address
`
`
`2 Claim 27 includes “of a memory array.”
`
`5
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`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`[of a memory array]” is described in the ’002 patent as a “conditional clock
`
`generator.” APPLE-1001, 3:9-36, 4:3-8, 5:31-34, 5:54-57, 6:8-19, 9:48-58, 10:27-
`
`32, 11:11-18, 12:4-10, 12:48-67; APPLE-1003, ¶¶49-50. Thus, the corresponding
`
`structure is a “conditional clock generator.” Id.
`
`5.
`
`“means for decoding a second portion of the memory
`address” (claims 11 and 14)
`
`This term is the same as the term “means for decoding a first portion of a
`
`memory address of a memory array,” except that the term replaces “first” with
`
`“second” and omits “of a memory array.” Thus, for reasons discussed above, the
`
`term is governed by §112 ¶6 and the corresponding structure is a “decoder.” APPLE-
`
`1003, ¶¶51-52.
`
`6.
`
`“means for activating a particular wordline driver of the
`selected group of wordline drivers according to the
`second portion of the memory address” (claims 11 and
`27)
`
`This term includes the phrase “means for,” which creates a presumption that
`
`the term is governed by §112 ¶6. Williamson, 792 F.3d at 1348.
`
`The corresponding structure for “activating a particular wordline driver of the
`
`selected group of wordline drivers according to the second portion of the memory
`
`address” is described in the ’002 patent as the four-to-sixteen decoder. APPLE-
`
`1001, 1:35-38, 3:18-25, 3:37-49, 3:62-4:8, 5:65-6:7, 9:40-44; APPLE-1003, ¶¶53-
`
`54. Thus, the corresponding structure is a “decoder.” Id.
`
`6
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`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`7.
`
`“means for applying the second portion of the memory
`address to a shared address line” (claim 14)
`
`This term includes the phrase “means for,” which creates a presumption that
`
`the term is governed by §112 ¶6. Williamson, 792 F.3d at 1348.
`
`The corresponding structure for “applying the second portion of the memory
`
`address to a shared address line” is described in the ’002 patent as the four-to-sixteen
`
`decoder. APPLE-1001, 3:37-49, 3:62-67, 4:40-43, 10:32-37, 14:13-16; APPLE-
`
`1003, ¶¶55-56. Thus, the corresponding structure is a “decoder.” Id.
`
`II. BACKGROUND
`
`A.
`
`’002 patent
`
`The ’002 patent describes a “wordline driver system” for a “memory array.”
`
`APPLE-1001, 2:53-56, Figure 1 (below). The system separately decodes a “first
`
`portion” and a “second portion” of a memory address. APPLE-1001, 1:29-38.
`
`The “first logic” decodes the “first portion” of the memory address (e.g., the 2-to-4
`
`decoder 112) and selectively provides a clock signal “to a selected group of
`
`wordline drivers based on a first portion of the memory address of the memory
`
`array” (e.g., conditional clock generator 110). APPLE-1001, 9:35-38; see also
`
`1:29-35. This selective application of the clock signal is said to reduce “the clock
`
`driver’s capacitance loading” and “reduces power consumption.” APPLE-1001,
`
`1:66-2:5. The “second logic” (e.g., 4-to-16 decoder 108) decodes the “second
`
`portion” of the memory address and “selectively activates a particular wordline
`
`7
`
`

`

`driver of the selected group of wordline drivers.” APPLE-1001, 1:35-37.
`
`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`Selected
`Group of
`WL Drivers
`
`Clock Outputs
`
`Second
`Logic
`
`First
`Logic
`
`Second Portion of
`Memory Address
`
`First Portion of
`Memory Address
`
`
`
`The ’002 patent includes 38 claims, of which claim 1, 7, 11, 17, 21, 23-27
`
`and 29 are independent.
`
`
`
`8
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`

`

`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`B.
`
`Prosecution History
`
`The ’002 patent issued on April 6, 2010 from U.S. Patent Application No.
`
`11/548,132 (“the ’132 application”), which was filed on October 10, 2006 with 27
`
`claims. See Ex. 1002. This application does not include a priority claim.
`
`III. APPLICATION OF PRIOR ART TO CHALLENGED CLAIMS
`
`Petitioner will prevail on the Challenged Claims.
`
`A. Claim 1 is Obvious Over Sato [GROUND-1]
`
`A claim may be rendered unpatentable by a single reference if a POSITA
`
`would have been motivated to modify that reference in an obvious way. SIBIA
`
`Neurosciences, Inc. v. Cadus Pharm. Corp., 225 F.3d 1349, 1356 (Fed. Cir. 2000).
`
`Notably, motivations to modify may be found implicitly in the prior art based on
`
`what the teachings of the art, a POSITA’s knowledge, and the nature of the
`
`problem to be solved would have suggested to a POSITA. See In re Kahn, 441
`
`F.3d 977, 987-88 (Fed. Cir. 2006); see also Cross Medical Prods., Inc. v.
`
`Medtronic Sofamor Danek, Inc., 424. F.3d 1293, 1322 (Fed. Cir. 2005) (motivation
`
`“equally can be found in the knowledge generally available to” a POSITA). The
`
`law credits a POSITA with ordinary creativity, and recognizes that the POSITA
`
`can draw upon both their knowledge and common sense to find motivation to make
`
`an obvious modification in view of disclosures in the art. See also KSR Intern. Co.
`
`v. Teleflex Inc., 550 U.S. 398, 420-21 (2007) (“Common sense teaches, however,
`
`that familiar items may have obvious uses beyond their primary purposes … A
`
`9
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`person of ordinary skill is also a person of ordinary creativity, not an automaton.”).
`
`Overview of Sato3
`
`Sato forms the basis of the Ground-1 in this Petition. As shown in Figure 3
`
`below, Sato selectively applies a clock signal ((cid:1)ce) to wordline drivers in a group
`
`of wordline drivers using a wordline decoder circuit (X address decoder XDCR)
`
`and separate logic circuitry (predecoder (PDCR)).
`
`First
`Address
`Portion
`
`Clock
`Outputs
`
`First
`Logic
`
`Group of
`Wordline
`Drivers
`
`Second
`Address
`Portion
`
`Second
`Logic
`
`Clock
`
`
`3 Petitioner hereby expressly incorporates the entirety of this Sato discussion into the
`
`element-by-element analysis of Ground 1, infra.
`
`
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`10
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`Sato, Figure 3 (annotated)
`
`Similar to the conditional clock generator of the ’002 patent, Sato’s “PDCR
`
`decodes the lower 2-bit complementary internal address signals ax0 and ax1 . . .
`
`and generates selection signals (cid:1)x0-(cid:1)x3.” APPLE-1005, 5:25-26. Sato explains
`
`in detail how “[t]hese selection signals (cid:1)x0-(cid:1)x3 are formed selectively in
`
`accordance with the complementary internal address signals ax0 and ax1.”
`
`APPLE-1005, 5:28-31; see also 5:31-42. Furthermore, the timing signal (cid:1)ce is
`
`also “supplied to the pre-decoder PDCR.” APPLE-1005, 10:36-39. The PDCR
`
`“output signal, that is, the selection signal (cid:1)x0-(cid:1)x3, is generated in accordance
`
`with this timing signal (cid:1)ce.” Id.
`
`Furthermore, Sato’s decoding NAND gate circuits are supplied with the
`
`remaining “complementary internal address signals ax2-axi” similar to the ’002
`
`patent’s four-to-sixteen decoder. APPLE-1005, 5:20-22. The decoding NAND
`
`gate circuits decode these remaining address signals to produce a selection signal
`
`(e.g., selection signal S0(cid:4)(cid:4)(cid:4)), which, along with one of the PDCR outputs, is used to
`
`activate one of the wordline drivers in each group of four drivers. APPLE-1005,
`
`5:43-6:59; APPLE-1003, ¶57.
`
`Claim 1–[1.0]: A circuit device comprising: first logic . . . and second logic . . .
`
`Sato discloses a “circuit device comprising: first logic . . . and second
`
`logic . . .” See APPLE-1005, Figure 3, 9:44-10:59, Claim 1. Specifically, Sato
`
`11
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`discloses the details of an “X address decoder XCDR of [a] CMOS static RAM,”
`
`the circuit elements of which are “formed on one semiconductor substrate.”
`
`APPLE-1005, 3:3-5, 9:31-32. Sato’s Figure 3 is “a circuit diagram” showing one
`
`embodiment of Sato’s “X address decoder of the static RAM.” APPLE-1005,
`
`2:57-59. As recited in Sato’s first claim, the XCDR includes a “first logic
`
`decoding means coupled to receive a first group of address signals,” and “second
`
`logic decoding means coupled to receive another group of address signals.”
`
`APPLE-1005, 12:49-50, 12:39-40. For example, in Figure 3 (below) “the X
`
`address decoder XDCR of the CMOS static RAM includes the pre-decoder PDCR
`
`[green-below] which receives the lower 2-bit complementary internal address
`
`signals ax0 and ax1[,] and k+1 decoding NAND gate circuits NAG0-NAGk [e.g.,
`
`NAG0 depicted in orange below] to which the complementary internal address
`
`signals ax2-axi other than the lower two bits in respective combinations are
`
`supplied.” APPLE-1005, 5:16-22; see also 9:44-48. Accordingly, Sato’s PDCR
`
`and NAND gate circuits represent first and second logic of a circuit device.4
`
`
`4 Sato’s reference to “first logic” and “second logic” in the claims is opposite to
`
`that of the ’002 patent solely on a labeling basis. Sato’s “second logic” performs
`
`functions equivalent to those performed by the ’002 patent’s “first logic” and
`
`12
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
`
`Clock
`Outputs
`
`First
`Logic
`
`Group of
`Wordline
`Drivers
`
`Second
`Logic
`
`
`
`
`
`First
`Address
`Portion
`
`Second
`Address
`Portion
`
`Clock
`
`
`
`
`
`
`Sato’s “first logic” performs functions equivalent to those performed by the ’002
`
`patent’s “second logic.”
`
`13
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`[1.1]: [the first logic] to receive a clock signal and a first portion of a
`memory address of a memory array,
`
`Sato discloses “first logic to receive a clock signal and a first portion of a
`
`memory address of a memory array” See e.g., APPLE-1005, Figure 3 (below),
`
`5:16-24, 9:44-54. Sato’s pre-
`
`decoder PDCR (green)
`
`represents the “first logic” as
`
`recited in the ’002 patent’s
`
`claims. The PDCR receives a timing signal (cid:1)ce (blue line) and address signals ax0
`
`and ax1 along with their complements (purple).
`
`More specifically, the PDCR “receives the lower 2-bit complementary
`
`internal address signals ax0 and ax1,” i.e., signals ax0, ax(cid:4)(cid:4)(cid:4)0, ax1, and ax(cid:4)(cid:4)(cid:4)1. APPLE-
`
`1005, 5:16-19. The internal address signals represent externally supplied memory
`
`address signals, along with the complement of each address signal, for addressing
`
`memory cells in a memory array (M-ARY). See APPLE-1005, 3:9-15, 3:50-59.
`
`Sato explains, “[t]he X address buffer XADB receives the X address signals AX0-
`
`AXi supplied through external terminals AX0-AXi and generates the
`
`complementary internal address signals ax(cid:4)(cid:4)(cid:4)0-ax(cid:4)(cid:4)(cid:4)i on the basis of these signals AX0-
`
`AXi and supplies them to the X address decoder XDCR.” APPLE-1005, 4:6-11.
`
`Timing signal (cid:1)ce represents or renders obvious a clock signal. APPLE-
`
`1003, ¶¶64-69. A POSITA would have “viewed the function of the timing signal
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`14
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`(cid:1)ce as similar to or equivalent to that of a clock signal because 1) “clock” is
`
`another name for a timing signal, 2) the Greek symbol phi ((cid:1)) is frequently used in
`
`the art to indicate clock signals, 3) this signal performs the same function as the
`
`clock signal in the ’002 patent and 4) (cid:1)ce performs the same function as the clock
`
`signal in a clocked decoder such as that described by Bridges.” Id., ¶64; APPLE-
`
`1005, 1:10-11, 12:4-6; APPLE-1001, 3:28-62; APPLE-1008, 3:1-4:24, Figure 1;
`
`APPLE-1011, 1:23-42. Indeed, even the examiner and Patent Owner recognized a
`
`timing signal as being equivalent to a clock signal during prosecution of the ’002
`
`patent. See APPLE-1002, 231 (9/11/2007 Office Action rejecting claims as
`
`anticipated by U.S. Patent 5,602,796 (“Sugio”) [APPLE-1012] and equating the
`
`claimed clock outputs with timing control signal outputs of Sugio’s timing control
`
`circuit 1.), see also 216-217 (Patent Owner’s response admitting that a “clock
`
`signal (CK) is used to drive all the wordline drivers” in Sugio through the timing
`
`control circuit 1.)(emphasis in original). Furthermore, Sato states that his
`
`invention “can be applied widely to semiconductor memory devices having at least
`
`a clocked static type address decoder” and that “CMOS static RAMs including
`
`clocked static decoders are known in the art,” which further corroborates Dr.
`
`Horst’s opinion. APPLE-1005, 1:10-11, 12:4-6; APPLE-1003, ¶64. In addition,
`
`Dr. Horst explains it would have been obvious to a POSITA that in order for Sato’s
`
`memory to operate properly, the timing signal must oscillate between subsequent
`
`15
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`memory operations; otherwise, a selected wordline may not be properly reset.
`
`APPLE-1003, ¶¶68-69.
`
`The function of the timing signal in Sato’s PDCR as described in reference
`
`to Figure 3, is also similar to that of a prior art clocked decoder as disclosed in a
`
`patent to Bridges (APPLE-1008). APPLE-1003, ¶¶67-68; APPLE-1008, 3:1-4:24,
`
`Figure 1. Indeed, Dr. Horst demonstrates that a POSITA would have recognized
`
`the operational similarity between Bridge’s clocked decoder and Sato’s PDCR. Id.
`
`In view of the apparent similarity, Horst explains that a POSITA would have
`
`concluded that Sato’s timing signal provides a comparable function for the PDCR
`
`as a clock signal does for a clocking clocked decoder. Id. Dr. Horst also notes that
`
`Sato’s timing signal provides a comparable function as the clock 118 signal of the
`
`’002 patent. Id., ¶¶65-66. Consequently, the POSITA would have reasonably
`
`viewed Sato’s timing signal as disclosing or rendering obvious a clock signal.
`
`In addition, various portions of Sato’s disclosure describe (cid:1)ce as a timing
`
`signal. APPLE-1005, 1:10-11, 3:59-4:2, 4:22-32, 5:7-12, 5:43-6:21, 6:60-7:30,
`
`9:44-10:55, 12:4-6. Although Sato includes an obscure statement suggesting that
`
`the timing signal could be kept at a high level, in contrast, a POSTIA would not
`
`have read this statement as one embodiment, distinct of other aspects described
`
`within the Sato disclosure. See APPLE-1005, 3:59-65. As Dr. Horst explains, a
`
`POSITA would have understood that the Sato system would perform poorly or
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`malfunction if the timing signal in Sato were kept at a high level throughout
`
`operation. APPLE-1003, ¶¶68-69. Thus, in the context of Sato’s disclosure, a
`
`POSITA would reasonably have understood that (cid:1)ce would be kept high at most
`
`for only a portion of a memory operation.
`
`In addition, Sato’s PDCR corresponds to the ’002 patent’s conditional clock
`
`generator 110 and 2 to 4 decoder 112 of the ’002 patent. Id., ¶84. For example,
`
`compare Figure 1 of the ’002 patent with Figure 3 of Sato (both reproduced
`
`below). Like the first logic in the ’002 patent (conditional clock generator 110 and
`
`decoder 112-green outline) Sato’s PDCR (green) receives both a clock signal
`
`(blue) and a first portion of a memory address (purple). APPLE-1001, Figure 1,
`
`3:18-36; APPLE-1003, ¶¶65-66.
`
`Sato FIG. 3
`
`
`
`Thus, Sato discloses this limitation or at least renders it obvious.
`
`
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`[1.2]: the first logic to decode the first portion of the memory address
`
`and
`
`Sato discloses “the first logic to decode the first portion of the memory
`
`address.” See APPLE-1005, Figure 3, 5:25-31, 9:44-48, 11:54-56, Claim 1.
`
`Drawing on this disclosure, Sato’s claim 1 recites, and thus, further discloses
`
`“logic decoding means coupled to receive a . . . group of address signals.”
`
`APPLE-1005, Claim 1. Second, Sato describes, in reference to Figure 1, that the
`
`“PDCR decodes the lower 2-bit complementary internal address signals.” APPLE-
`
`1005, 5:25-26. The PDCR operates similarly in the embodiment shown in Figure
`
`3. See APPLE-1005, 9:30-48 (“In FIG. 3, the X address decoder XDCR . . . of this
`
`embodiment includes one pre-decoder PDCR and k+1 decoding NAND gate
`
`circuits NAG0~NAGk in the same way as in the foregoing embodiments.”). Thus,
`
`Sato’s first logic (PDCR) decodes the first portion of the memory address.
`
`APPLE-1003, ¶70.
`
`[1.3]: [the first logic . . .] to apply the clock signal to a selected clock
`output of a plurality of clock outputs associated with a selected group of a
`plurality of wordline drivers that are associated with the memory array;
`
`Sato renders obvious that the PDCR “appl[ies] the clock signal to a selected
`
`clock output of a plurality of clock out-puts associated with a selected group of a
`
`plurality of wordline drivers that are associated with the memory array.” See
`
`APPLE-1005, Figure 3 (below), 5:25-31, 6:40-55, 9:30-51, 9:52-65, 10:36-39,
`
`Claim 1.
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`18
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`First, Sato mimics disclosure within the ’002 patent and, as such, provides
`
`disclosure that would have rendered obvious to a POSITA what is claimed by the
`
`‘’002 patent with respect to the application of a timing signal by the first logic to
`
`its output. APPLE-1003, ¶¶14, 65-72. For instance, the PDCR applies a clock
`
`signal to one of a plurality of outputs similar to the conditional clock generator 110
`
`of the ’002 patent. Id. For example, compare the Figure 1 of the ’002 patent with
`
`Figure 3 of Sato (both reproduced below). Like the conditional clock generator
`
`110 (green outline) in the ’002 patent, the PDCR (green) applies the clock signal
`
`(blue) to one of four outputs (red) according to the first portion of the memory
`
`address (purple). Compare APPLE-1001, 3:26-36 with APPLE-1005, 5:25-31,
`
`10:36-39; see also APPLE-1003, ¶¶14, 65-72.
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`19
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`‘002 Pat. FIG. 1
`
`Sato FIG. 3
`
`
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`20
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`Next, Sato discloses or renders obvious to a POSITA that the PDCR (green)
`
`applies (cid:1)ce to one of the four outputs (red lines) associated with selection signals
`
`(cid:1)x0-(cid:1)x3. For instance, with reference to the third embodiment, in describing the
`
`PDCR’s output signal, Sato states, “the selection signal (cid:1)x0-(cid:1)x3, is generated in
`
`accordance with [the] timing signal (cid:1)ce.” APPLE-1005, 10:36-39. The PDCR
`
`selects a particular one of the outputs “in
`
`accordance with the complementary
`
`internal address signals ax0 and ax1.”
`
`APPLE-1005, 5:29-31; see also 5:31-42.
`
`The PDCR then applies the timing signal
`
`(cid:1)ce to the selected output by generating
`
`the selection signal “in accordance with
`
`this timing signal (cid:1)ce.” APPLE-1005,
`
`10:39. In the third embodiment, when the
`
`“timing signal (cid:1)ce is set to the high logic
`
`level . . . the output signal of the pre-
`
`decoder PDCR, that is, the selection signal (cid:1)x0-(cid:1)x3, is set selectively to the high
`
`logic level.” APPLE-1005, 9:56-59.
`
`Furthermore, Dr. Horst explains that a POSITA would have understood
`
`Sato’s PDCR as applying the input clock signal ((cid:1)ce) to one of the four clock
`
`21
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`Attorney Docket No. 39521-0054IP1
`IPR of U.S. Patent No. 7,693,002
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`outputs based on the values of address bits ax0 and ax1. APPLE-1003, ¶¶14, 60-
`
`63, 71-72. Dr. Horst demonstrates by reference to an illustration of what a
`
`POSITA would have understood to be an accurate depiction of the internal logic of
`
`Sato’s PDCR (right),
`
`such that the “outputs
`
`(cid:1)x0-(cid:1)x3 follow[] the
`
`same low-to-high and
`
`high-to-low transitions as
`
`the input clock signal
`
`(cid:1)ce.” APPLE-1003,
`
`PDCR
`
`(cid:1)ce
`
`ax0
`
`ax0
`
`ax1
`
`ax1
`
`1 1
`
`0 1
`
`1 0
`
`0 0
`
`=
`
`(cid:1)ce
`
`0
`
`0
`
`0
`
`(cid:1)x0
`(cid:1)x1
`(cid:1)x2
`(cid:1)x3
`Illustration of the PDCR decoder with ax0=ax1=0
`
`¶71; see also APPLE-1009, 314-315, Figure 6.16. Dr. Horst continues:
`
`Th[is] illustration shows that [when the input address is 00], (cid:1)x1–(cid:1)x3
`
`are forced low because at least