IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Attorney Docket No.:39521-0054IP1
`
`
`Jentsung Lin
`In re Patent of:
`7,693,002
`U.S. Pat. No.:
`April 6, 2010
`Issue Date:
`Appl. Serial No.: 11/548,132
`Filing Date:
`October 10, 2006
`Title:
`DYNAMIC WORD LINE DRIVERS AND DECODERS FOR
`MEMORY ARRAYS
`
`
`
`DECLARATION OF EDWARD G. FAETH
`
`
`I, Edward G. Faeth, of Rockville, MD, declare:
`
`
`1.
`
`My name is Edward G. Faeth. I am over the age of 21, and I have personal
`
`knowledge of the facts contained herein unless otherwise indicated. I am an
`
`employee at Fish & Richardson P.C.
`
`2.
`
`On March 27, 2018, I visited the Jefferson Building of the Library of
`
`Congress in Washington, D.C., where I previously requested a copy of the book
`
`identified below to compare the electronic copy of the book, submitted as an exhibit
`
`with this petition, with the physical copy maintained by the Library of Congress.
`
`3.
`
`Using the Library of Congress record for APPLE-1007 (“Itoh”) (Appendix
`
`A), located through the title and author of APPLE-1007, I requested a copy of
`
`CALL NUMBER TK7895.M4 I876 2001 from the library system. I compared the
`
`contents of APPLE-1007 to the physical copy provided to me by the Library of
`
`Congress and the appearance, contents, substance, and other characteristics of
`
`APPLE 1010
`
`1
`
`

`

`APPLE-1007 appeared to be the same as the copy maintained by the Library of
`
`Congress.
`
`1.
`
`On April 10, 2018, I again visited the Jefferson Building of the Library of
`
`Congress in Washington, D.C., where I previously requested a copy of the book
`
`identified below to compare the electronic copy of the book, submitted as an exhibit
`
`with this petition, with the physical copy maintained by the Library of Congress.
`
`2.
`
`Using the Library of Congress record for APPLE-1009 (“Brown”)
`
`(Appendix B), located through the title and author of APPLE-1009, I requested a
`
`copy of CALL NUMBER TK7868.L6 B76 2002 from the library system. I
`
`compared the contents of APPLE-1009 to the physical copy provided to me by the
`
`Library of Congress and the appearance, contents, substance, and other
`
`characteristics of APPLE-1009 appeared to be the same as the copy maintained by
`
`the Library of Congress.
`
`I declare that all statements made herein of my own knowledge are true and
`
`that all statements made on information and belief are believed to be true; and
`
`further that these statements were made with the knowledge that willful false
`
`statements and the like so made are punishable by fine or imprisonment, or both,
`
`under 18 U.S.C. § 1001.
`
`Date: April 10, 2018
`
`
`
`
`
`
`
`
`
`
`
`
`By:
`
`
`
`
`/Edward G. Faeth/
`Edward G. Faeth, Rockville, MD
`
`2
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`APPENDIX A
`
`APPENDIX A
`
`3
`
`

`

`Page 1 of 1
`
`1. VLSI memory chip design
`
`00068735
`Book
` -1941Itoh, Kiyoo,
`
`
`design / Kiyoo Itoh.VLSI memory chip
`
`2001.Berlin ; New York : Springer,
`
`xi, 495 p. : ill. ; 25 cm.
`Publisher description
`http://www.loc.gov/catdir/enhancements/fy0816/00068735
`Table of contents only
`http://www.loc.gov/catdir/enhancements/fy0816/00068735
`3540678204 (alk. paper)
`I876 2001TK7895.M4
`
`Semiconductor storage
`devices
`--
`Design and construction.
`Integrated circuits
`Very large scale integration
`construction.Design and
`--
`--
`
`488) and index.
`references (p. [473]Includes bibliographical
`
`-
`Springer series in advanced microelectronics ; 5
`621.39/732
`
`-
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`d.html
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`-
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`t.html
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`TK7895.M4 I876 2001
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`‘J'
`
`.
`w Sprmger
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`I‘-
`
`I :f.
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`5
`
`

`

`RONI CS
`
`rovides systematic information on
`manufacturing of microelectronic
`rchers or engineers in their fields,
`:h as wafer processing, materials,
`fLSI implementation, and subsys(cid:173)
`l physics and engineering and the
`is research scientists.
`
`ss Communication
`
`Kiyoo Itoh
`
`VLSI
`Memory Chip Design
`
`With 416 Figures and 26 Tables
`
`ooks/ssam/
`
`'
`
`Springer
`
`6
`
`

`

`Dr. Kiyoo Itoh
`Hitachi Ltd., Central Research Laboratory
`1-280, Higashi-Koigakubo
`Kokubunji-shi
`Tokyo185-8601
`Japan ·
`e-mail: k-itoh@crl.hitachi.co.jp
`
`Series Editors:
`
`Dr. Kiyoo Itoh
`Hitachi Ltd., Central Research Laboratory
`1-280 Higashi-Koigakubo
`Kokubunji-shi
`Tokyo 185-8601
`Japan
`
`Professor Takayasu Sakurai
`Center for Collaborative Research
`University of Tokyo
`7-22-1 Roppongi, Minato-ku,
`Tokyo 106-8558
`Japan
`
`Library of Congress Cataloging-in-Publication Data
`
`Itoh, Kiyoo, 1941-
`VLSI memory chip design / Kiyoo ltoh.
`p. cm. -.- <Spring~r series in advance? microelectronics ; 5)
`Includes b1bhographical references and mdex.
`ISBN 3540678204 (a!k. paper)
`I. Semiconductor storage devices--Design and construction. 2. Integrated
`circuits-Very large scale irttegration--Design and construction. I. Title. 11. Series.
`
`TK7895.M41876 2001
`62 l .39'732--dc21
`
`00-068735
`
`ISSN 1437-0387
`ISBN 3-540-67820-4 Springer-Verlag Berlin Heidelberg New York
`
`This work is subject to copyright. All rights .are reserved, whether the whole or part of the material is
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`Type~ctting by the author.
`Data conversion and hgure processmg by LE-'l'EX- Jelonek, Schmidt & Vtickler GbR, 04229 Leipzig.
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`Cover concept by eStudio Calmar Steinen using a background picture from Photo Studio "SONO". Courtesy
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`7
`
`

`

`tance, the basic technologies
`! peripheral circuits are des(cid:173)
`cy are explained. Chapter 4
`.M which strongly influences
`, in the chip. The relation(cid:173)
`ving/ sensing is explained in
`: on-chip voltage generators
`.tors are essential for power(cid:173)
`apter 6 discusses subsystem(cid:173)
`mportant in providing wide
`S. Chapters 7 and 8 describe
`3izing the importance of the
`f lowering power-supply vol-
`1old-current reduction which
`
`leagues and the office admi-
`0 hta, at Hitachi Ltd. They
`. to finalize my work. Special
`inuing support and patience
`
`Kiyoo Itoh
`
`Contents
`
`1
`1. An Introduction to Memory Chip Design . . . . . . . . . . . . . . . . .
`1
`1.1
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.2 The Internal Organization of Memory Chips . . . . . . . . . . . . . . .
`3
`1.2.1 The Memory Cell Array............. . ............. 3
`1.2.2 The Peripheral Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`5
`1.2.3 The I/O Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . .
`6
`1.3 Categories of Memory Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`6
`1.4 General Trends in DRAM Design and Technology . . . . . . . . . . 11
`1.4.1 The History of Memory-Cell Development . . . . . . . . . . . 11
`1.4.2 The Basic Operation of The 1-T Cell . . . . . . . . . . . . . . . 15
`1.4.3 Advances in DRAM Design and Technology . . . . . . . . . 19
`1.5 General Trends in SRAM Design and Technology . . . . . . . . . . . 24
`1.5.1 The History of Memory-Cell Development . . . . . . . . . . . 24
`1.5.2 The Basic Operation of a SRAM Cell . . . . . . . . . . . . . . . 26
`1.5.3 Advances in SRAM Design and Technology . . . . . . . . . . 29
`1.6 General Trends in Non-Volatile Memory Design
`and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
`1.6.l The History of Memory-Cell Development . . . . . . . . . . . 31
`1.6.2 The Basic Operation of Flash Memory Cells . . . . . . . . . 34
`1.6.3 Advances in Flash-Memory Design and Technology . . . 46
`
`2. The Basics of RAM Design and Technology . . . . . . . . . . . . . . 49
`2.1
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`2.2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`2.2.1 MOSFETs ...................................... 49
`2.2.2 Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`2.2.3 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`2.2.4 Wiring and Wiring Materials . . . . . . . . . . . . . . . . . . . . . . 61
`2.2.5 Silicon Substrates and CMOS Latch-Up . . . . . . . . . . . . . 65
`2.2.6 Other Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`2.3 NMOS Static Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`2.3.1 The de Characteristics of an Inverter . . . . . . . . . . . . . . . 68
`2.3.2 The ac Characteristics of an Inverter.. . . . . . . . . . . . . . . 70
`2.3.3 The Improved NMOS Static Inverter... . . ...... . .... 74
`
`8
`
`

`

`VIII Contents
`
`2.4 NMOS Dynamic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`2.4.1 The Dynamic Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`~.4.~ 'l'he Bootstrap Dnver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`'/'I
`2.5 CMOS Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
`2.5.1 The de Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
`2.5.2 The ac Characteristics .... .'. . . . . . . . . . . . . . . . . . . . . . . 82
`2.6 Basic Memory Circuits.................... . . . . . . . . . . . . . . 83
`2.6.1 The Inverter and the Basic Logic Gate . . . . . . . . . . . . . . 83
`2.6.2 The Current Mirror................. . ............. 83
`2.6.3 The Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 83
`2.6.4 The Voltage Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
`2.6.5 The Level Shifter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
`2.6.6 The Ring Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
`2.6.7 The Counter....................... .............. 89
`2. 7 The Scaling Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`2. 7.1 Constant Electric-Field Scaling. . . . . . . . . . . . . . . . . . . . . 90
`2. 7.2 Constant Operation-Voltage Scaling . . . . . . . . . . . . . . . . 92
`2. 7.3 Combined Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
`2.8 Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`2.9 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
`
`3. DRAM Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
`3.1
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
`3.1.1 High-Density Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 98
`3.1.2 High-Performance Circuits ........................ . 100
`3.2 The catalog Specifications of the Standard DRAM ......... . 102
`3.2.1 Operational Conditions .......................... . 102
`3.2.2 Modes of Operation and Timing Specifications ...... . 105
`3.3 The Basic Configuration and Operation of the DRAM Chip . . 110
`3.3.l Chip Configuration .............................. . 110
`3.3.2 Address Multiplexing ............................ . 111
`3.4 Fundamental Chip Technologies ......................... . 113
`3.4.1 A Larger Memory Capacity and Scaled-Down Devices . 113
`3.4.2 High S/N Ratio Circuits ......................... . 116
`:l.4.:l Luw Power Cin:uiL:,; .............................. . 117
`3.4.4 High-Speed Circuits ............................. . 123
`3.4.5 The Multidivision of a Memory Array .............. . 128
`3.5 The Multidivided Data Line and Word Line .............. . 131
`3.5.1 The Multidivided Data Line ...................... . 132
`3.5.2 The Multidivided Word Line ...................... . 139
`3.6 Read and Relevant Circuits ............................. . 141
`3.G.1 The Address Buffer .............................. . 141
`3.6.2 The Address Decoder ............................ . 144
`3.6.3 The Word Dri~er ................................. 147
`3.6.4 The Sensing Circuit ............................. . 157
`
`9
`
`

`

`.... . ....... ...... 76
`.................. 76
`77
`.. .. ........... . . . 79
`80
`.. ..... .. .... ..... 82
`83
`:iate ............. . 83
`.. ..... ..... . ..... 83
`83
`.............. . ... 87
`.. . ... ... . .... ... . 88
`88
`89
`90
`. ... ........... . .. 90
`ig . . . . . . . . . . . . . . . . 92
`. .. .... . .... . . .. .. 92
`93
`.... . . . ... .... .... 94
`
`... .... ... ... ... . . 97
`....... . . . . ....... 97
`.................. 98
`.. . ..... . ...... ... 100
`d DRAM ...... . . . . 102
`.................. 102
`pecifications ..... .. 105
`1f the DRAM Chip . . 110
`.... . . . .. .. . . ..... 110
`........... . ...... 11.1
`. .. ...... ......... 113
`caled-Down Devices. 113
`.... .. .. ... . . . ... . 116
`. .. .. . ......... ... 117
`. .. . .............. 123
`:ray ....... . ....... 128
`ine .. . . . . . ........ 131
`.... . ... . . . ....... 132
`.. .. ... .. . ........ 139
`.. . . . ... . ..... .... 141
`. . ...... .. ........ 141
`................. . 144
`.... . .. . . . ...... .. 147
`.... . ......... . ... 157
`
`Contents
`
`IX
`
`3.6.5 The Common I/0-Line Relevant Circuit ........... . 167
`3.6.6 The Data-Output Buffer ........................ .. 172
`3.7 Write and Relevant Circuits ........................... .. 174
`3.8 Refresh-Relevant Circuits .............................. .. 175
`3.8.1 Refresh Schemes ............................... .. 175
`3.8.2 The Extension of Data-Retention Time
`in Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
`3.8.3 Current Reduction Circuits in Data-Retention Mode .. 176
`3.9 Redundancy Techniques ............................... .. 178
`Issues for Large-Memory-Capacity Chips .......... .. 184
`3.9.1
`Intra-Subarray Replacement Redundancy .......... .. 185
`3.9.2
`Inter-Subarray Replacement Redundancy .......... .. 189
`3.9.3
`3.9.4 The Repair of de-Characteristics Faults ........... . . 191
`3.10 On-Chip Testing Circuits .............................. . . 192
`
`4. High Signal-to-Noise Ratio
`DRAM Design and Technology ................ .. ..... . . . . 195
`Introduction ................................ ........... 195
`4.1
`4.2 Trends in High S/N Ratio Design .............. .. ..... .. .. 195
`4.2.l The Signal Charge ..................... ........... 197
`4.2.2 Leakage Charge ....................... . .......... 204
`4.2.3 The Soft-Error Critical Charge .......... ..... .. .... 208
`4.2.4 The Data-Line Noise Charge ............ . ..... ..... 210
`4.3 Data-Line Noise Reduction ................... ........... 210
`4.3.l Noise Sources and Their Reduction ...... .. . ...... .. 210
`4.3.2 Word-Line Drive Noise ................. . .. . ... .... 213
`4.3.3 Data-Line and Sense-Amplifier Imbalances ..... .. .. . . 217
`4.3.4 Word-Line to Data-Line Coupling Noise .. ........... 230
`4.3.5 Data-Line Interference Noise ............ . .. . ...... . 237
`4.3.6 Power-Supply Voltage Bounce ........... ......... . . 240
`4.3. 7 Variation in the Reference Voltage ....... . .. .... . ... 241
`4.3.8 Other Noises .......................... ........... 244
`4.4 Summary ................................... .. ......... 247
`
`G. On-Chip Voltage Generators .... . ..... . ..... . . .. . . .. . ..... 249
`.5.1
`Tntro<'l11dion ............................. . .. ........... 249
`5.2 The Substrate-Bias Voltage (VBB) Generator . ............. . 251
`5.2.1 The Roles of the VBB generator ....... .... . ...... . . 251
`5.2.2 Basic Operation and Design Issues .... ... .. ..... ... . 256
`5.2.3 Power-On Characteristics ............. ............. 258
`5.2.4 Characteristics in the High-Vnn Region ............ . 264
`5.2.5 The VBB Bump .................... ..... .... .. ... 266
`5.2.6 Substrate-Current Generation ........ .............. 269
`5.2. 7 Triple-Well Structures .............. ... .... ... . ... 272
`5.2.8 Low-Power VBB Generators .......... ...... . ...... . 273
`
`10
`
`

`

`X
`
`Contents
`
`5.3 The Voltage Up-Converter .............. . ..... . .. . .. . .. .. 276
`5.3.l The Roles of the Voltage Up-Converter ............ .. 276
`5.3.2 Design Approaches and Issues ........... . .......... 278
`5.3.3 High Boost-Ratio Converters ........... . ........ . . 283
`5.3.4 Low-Power, High Supply Current Converters .... . ... . 285
`5.4 The Voltage Down-Converter ........ .. ....... . ..... . .. . . 290
`5.4.l The Roles of the Voltage Down-Converter . ....... ... 290
`5.4.2 The Negative-Feedback Converter and Design Issues . . 293
`5.4.3 Optimum Design .............................. ... 297
`5.4.4 Phase Compensation .......................... .... 301
`5.4.5 Reference-Voltage Generators ........... . ........ . . 316
`5.4.6 Burn-In Test Circuits .......................... . . . 323
`5.4. 7 Voltage Trimming .......... . .................. . .. 327
`5.4.8 Low-Power Circuits ............................... 329
`5.5 The Half-Voo Generator ...... . .... . . .. ... . .. . .......... 332
`5.6 Examples of Advanced On-Chip Voltage Generators ..... .. . 333
`
`6. High-Performance Subsystem Memories .... . ......... .. .. 339
`6.1
`Introduction .......................... . .. . .. . ...... . .. . 339
`6.2 Hierarchical Memory Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
`6.2.1 Memory Hierarchy .................. . ......... . .. . 341
`6.2.2
`Improvements in Memory-Subsystem Performance .... 344
`6.2.3 Memory-Chip Performance ....... . .. . .. . ...... . . .. 349
`6.3 Memory-Subsystem Technologies ........... . ......... . ... 354
`6.3.l Wide-Bit I/O Chip Configurations . . ........... . .. .. 354
`6.3.2 Parallel Operation of Multidivided Arrays ....... .. .. 354
`6.3.3 Multibank Interleaving ....................... . . .. . 357
`6.3.4 Synchronous Operation . . ..... . ..... .. ........ .... 358
`6.3.5 Pipeline/Prefetch Operations ................. . . . .. 362
`6.3.6 High-Speed Clocking Schemes ................. .... . 363
`6.3. 7 Terminated I/O Interfaces ........ . ............ ... . 363
`6.3.8 High-Density Packaging .......... . .. . ..... . .. .. ... 364
`6.4 High-Performance Standard DRAMs ...................... 365
`6.4.1 Tremlti in Chip Development ............ . ..... .... . 365
`6.11.2 Synchronous DRAM ............. .. .......... .. ... 368
`6.4.3 Rambus DRAM ................. . ........... .. . . . 380
`6.5 Embedded Memories .... . ........... . .. . . .. .. . ... . . ... .. 383
`
`7. Low-Power Memory Circuits ...................... . . .. . . . 389
`7.1
`Introduction .............................. .. . . . ... ... . . 389
`7.2 Sourr.P.8 and Reduction of Power Dissipation
`in a RAM Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
`7.2.l Wide-Bit I/O Chip Configuration .. .... . . .. .. . .. . . . 393
`7.2.2 Small Package ...................... .... .. . . . .. . . 394
`7.2.3 The Low-Voltage Data-Bus Interface . .. . . . . . .. . . . .. . 396
`
`11
`
`

`

`Contents
`
`XI
`
`7.3 Sources of Power Dissipation in the RAM Chip ... ..... ..... 402
`7.3.l Active Power Sources ................ .. .. ....... . . 402
`7.3.2 Data-Retention Power Sources ................ . . . .. 405
`7.4 Low-Power DRAM Circuits ................. ...... .. . . . . . 406
`7.4.1 Active Power Reduction . ..... . .... . . .............. 406
`7.4.2 Data-Retention Power Reduction ... . .. . ... ...... .. . 412
`7.5 Low-Power SRAM Circuits .................... . ......... 413
`7.5.1 Active Power Reduction ...... . ....... ... .. .. . . .... 413
`7.5.2 Data-Retention Power Reduction ........ .. .... . ... . 423
`
`8. Ultra-Low-Voltage Memory Circuits ...................... 425
`8.1
`Introduction .................................... ....... 425
`8.2 Design Issues for Ultra-Low-Voltage RAM Circuits .. ... .... 426
`8.2.l Reduction of the Subthreshold Current ...... . . . . .. .. 426
`8.2.2 Stable Memory-Cell Operation ..... . .... ........ ... 432
`8.2.3 Suppression of, or Compensation for,
`Design Parameter Variations ......... . . . .. . . ..... . . 433
`8.2.4 Power-Supply Standardization . ........... .. .. .. ... 435
`8.3 Ultra-Low-Voltage DRAM Circuits ....................... 437
`8.3.1 Gate Boosting Circuit ... . ............... .. .. ... .. . 439
`8.3.2 The Multi-VT Circuit ....................... . . .... 440
`8.3.3 The Gate-Source Back-Biasing Circuit .... . ......... 442
`8.3.4 The Well Control Circuit .................... . ..... 456
`8.3.5 The Source Control Circuit ............. ...... ... .. 461
`8.3.6 The Well and Source Control Circuit ....... .. .. .... 462
`8.4 Ultra-Low-Voltage SRAM Circuits ... . .... . ...... . . .. ... . . 463
`8.5 Ultra-Low-Voltage SOI Circuits . ......... . ...... .. . . . .... 466
`
`References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 73
`
`Index ... ... ........ ... . ..... .. .. ... .... ... ...... . . . ........ ... 489
`
`--
`
`..... ... . .. . ... . .. . 276
`verter ..... . ... . . ... 276
`.... . . .. ... .. .. . ... 278
`................... 283
`Converters . . . . . . . . . 285
`. .. . ......... . . .... 290
`;onverter . . . . . . . . . . . 290
`r and Design Issues . . 293
`..... ... ...... . . ... 297
`................... 301
`...... . . . ..... . .... 316
`.. ........... .... . . 323
`. . .. . ........ . ..... 327
`................... 329
`............ .. ..... 332
`! Generators . . . . . . . . 333
`
`s . .... . .... .. .. . ... 339
`.. . ... . . . ........... 339
`.................... 341
`. ...... . . . .... ... ... 341
`;tern Performance . . . . 344
`........ . ........... 349
`.. ... .. . ........... . 354
`as ...... . . . ......... 354
`~d Arrays . . . . . . . . . . . 354
`... . ... . . .. . . ... .. .. 357
`.................... 358
`...... .... .. . . ..... . 362
`.... . . . . .... ... ... .. 363
`... . . . . . . . .. .. .. . ... 363
`................... . 364
`.......... . . . ...... . 365
`. ... ... ............. 365
`. .... ... . .. ....... .. 368
`.. .... . ... . . .... ... . 380
`... . . ... . ..... . ..... 383
`
`. .... ........ ...... . 389
`. .... .. .... . ....... . 389
`ation
`. .... . ............ . . 392
`•ll . ••. ..•••. ...• •• .. 393
`........... . . . ... ... 394
`rface ................ 396
`
`12
`
`

`

`!sh cycle
`
`4K
`
`,.16K
`........ · ~
`·K
`
`'
`
`!
`.:::e
`y
`• r102pe1
`256M 1G
`
`~c
`
`VI
`
`3.6 Read and Relevant Circuits
`
`141
`
`resistance polycide, in order to double or quadruple the number of memory
`cells to be driven. To further reduce the RC delay, a poly-Si or polycide word
`line strapped with a low-resistance aluminum line in each string of 64-128
`cells [3.17], as shown in Fig. 3.40b, has been widely accepted in commercial
`chips since the 1 Mb generation. In the 64 Mb generation, even a hybrid
`division of the two types shown in Fig. 3.40 has been proposed. However,
`the aluminum-strapped word-line structure suffers from some drawbacks. It
`becomes difficult to achieve fine patterning of aluminum at a tight pitch of
`word lines on a hilly surface, while still connecting to the poly-Si line at the
`bottom, as the memory cell is miniaturized. In addition, even the word-line
`structure starts to create quite a large RC delay as many memory cells are
`connected to a word or subword line. A multidivided word-line scheme using
`a hierarchical word-line structure [3.18, 3.19], as shown in Fig. 3.25, solves
`these problems, and is discussed later in detail.
`
`f data lines [3.3, 3.4]. A CD of 200 fF
`
`X decoder
`,_....,....-
`
`memory cell array
`
`area
`0
`
`I' ,,.
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`~ .......
`>o u c
`!'G a.
`:i u u
`0
`cu e !'G
`al ... ...
`
`I >o
`
`~
`
`WL x WL
`
`~
`
`(a)
`
`x
`
`(b)
`
`64 data-line pairs
`poly-Si.
`_ ~ _
`_ /
`WL
`!..-. ·· · ··'\· ·······----·~---··----~ ---· ·--- ~ - --····· ·1
`Al
`
`4M 256M 1G
`1ip)
`
`se amplifiers in a DRAM chip [3.4]
`
`i/ of a word line made of a resistive
`r of divisions has been determined
`Lltant area penalty. In the 64 Kb
`short and the speed requirement
`,e, as shown in Fig. 3.40a [3.9], was
`, poly-Si was replaced by a lower-
`
`Fig. 3.40. Reductions in word-line delay [3.4, 3.9, 3.17J. (a) 64Kb-256Kb. 64Kb:
`poly-Si (30 .11/0) , 64 d11,t.a-1inf! pairs per WL. 256Kb: polycide (1- 5.11/0), 256
`data-line pairs per WL. (b ) lMb and beyond: poly-Si (50S1/0), Al (O.H1/0)
`
`3.6 Read and Relevant Circuits
`
`3.6.1 The Address Buffer
`
`In the NMOS era of the 16-256 Kb generations, a differential address buffer
`using an on-chip reference voltage [3.14] was widely used. Since the 1 Mb
`
`13
`
`

`

`142
`
`3. DRAM Circuits
`
`Voo
`
`RAS1
`
`RAS4
`
`Fig. 3.41. The RAS clock buffer [3.21]
`
`generation, various simple CMOS address buffers have been proposed. In
`principle, the sa.me circuit configuration is applicable to both the row and co(cid:173)
`lumn address buffers. Recently however, a high-speed column address buffer
`has been especially important to enhance the data throughput by shortening
`the column address access time tAA, which is dominated by the address buffer
`(about 40% of tAA [3.20]) .
`Figure 3.41 shows a typical RAS-clock buffer [3.21] to control the row
`address buffers. To discriminate between the TTL logic levels of over 2.4 V or
`below 0.8 V for an input RAS signal, the logical threshold voltage is adjusted
`to be about 1.6 V by tuning the channel-width ratios of the NMOS and the
`PMOS at the first input stage. A multistage CMOS circuit controls the row
`internal circuits, using pulses with differing polarities and delays.
`Figure 3.42 shows an address buffer that features a cross-coupled differen(cid:173)
`tial amplifier [3.21]. It enables an almost constant speed due to a differential
`circuit configuration, independently of the power-supply noise. Address buf(cid:173)
`fers consisting of inverters, similar to the above RAS buffer, have also been
`widely accepted. In general, however, the operation of inverter-type buffers
`is susceptible to power-supply noise [3.20]. For example, as soon as the input
`logic signals to many buffers are simultaneously switched to the other logic
`state so that the ground (Vss) line voltage is instantaneously raised and
`maximized, the speed of each buffer is degraded, with a reduced NMOS
`gate-source voltage. For a 64 Mb design (3.20], a simultaneous switching
`of 13 address buffers caused a Vss uuise of 0.4 V and a speed diffP.rflnc.e of
`2.3 us between the inverter and cross-coupled type~, although the difference
`depended uu Lhe quality of the Vss layout. In the figure, the input voltage of
`address Ai is compared with a reference VREF (1.6 V) to discriminate between
`a high logic level (H) and a low logic level. The resultant differential signal
`developed between N 1 and N 2 is quickly amplified to a full Voo by the cross(cid:173)
`coupled amplifier, as a result of the application of RAS 2 • After that, the
`complementary addresses ai and ai are generated by the application of RAS 4
`to address latches (ALCs). Note that during standby periods (i.e. RAS: H)
`both ai and ai are kept low and there is no current path in the buffer.
`
`Fig. 3.42
`
`Figur
`although
`address c
`pulses ge
`ATD pul
`as to cor
`sition is
`the I/O •
`the tran:
`without
`can be (
`amplifiei
`
`address
`input
`
`1
`
`Fig. 3.
`buffers
`
`14
`
`

`

`3.6 Read and Relevant Circuits
`
`143
`
`RAS''-- --
`RAS1 ~
`RAS2 -----"\
`\_____
`
`-
`RAS•
`
`RASa _
`_ __,
`N1,N2 ~
`
`f-o VREF
`f--o RASs
`
`address
`latch
`
`Fig. 3.42. The cross-coupled address buffer (3.21)
`
`Figure 3.43 shows a typical address transition detector (ATD) [3.22],
`although the variations are shown in Fig. 7.18. Exclusive OR of aQ and the
`address delayed by T generates a short pulse every a~ transition. All the short
`pulses generated from all the address input transitions are summed up to one
`ATD pulse EQ. Thus, an ATD pulse is generated at any address transition so
`as to control internal circuits instead of external clocks. If any address tran(cid:173)
`sition is quickly detected by ATD and the resultant ATD signal precharges
`the I/ Oline in advance, a data line will be selected using addresses just ~er
`the transition, so that a data on the data line is outputted on the I/ O line
`without waiting for the I/O precharging. Thus, a long I/O precharging time
`can be concealed. The ATD signal reduces the power dissipation of main
`amplifier by cutting th~ de current during periods when it is not needed.
`
`address
`input
`
`array
`
`Y dee
`
`a.
`a.
`
`AB
`
`x
`dee
`
`RAS
`
`AB
`
`&'
`
`a'
`
`Fig. 3.43. The address transition detector (ATD) scheme [3.22]. AB, address
`buffers
`
`ffers have been proposed. In
`icable to both the row and co-
`1-speed column address buffer
`.ata throughput by shortening
`>minated by the address buffer
`
`.ffer [3.21] to control the row
`TL logic levels of over 2.4 V or
`1 threshold voltage is adjusted
`t ratios of the NMOS and the
`:MOS circuit controls the row
`larities and delays.
`tures a cross-coupled differen(cid:173)
`ant speed due to a differential
`rer-supply noise. Address buf(cid:173)
`re RAS buffer, have also been
`ration of inverter-type buffers
`example, as soon as the input
`ly switched to the other logic
`[s instantaneously raised and
`ided, with a reduced NMOS
`:OJ, a simultaneous switching
`4 V and a speed diffcrcncP. of
`types, although the difference
`.he figure, the input voltage of
`1.6 V) to discriminate between
`:ie resultant differential signal
`:led to a full Voo by the cross(cid:173)
`ion of RAS 2 . After that, the
`ed by the application of RAS4
`;tandby periods (i.e. RAS: H)
`~rent path in the buffer.
`
`15
`
`(cid:173)
`

`

`144
`
`3. DRAM Circuits
`
`3.6.2 The Address Decoder
`
`Major concerns for the address-decoder block are power dissipation, speed,
`and area, because the block includes a huge number of circuits and occupies
`quite a large segment of the chip.
`There are two kinds of decoder; row decoders and column decoders. In
`DRAM design unlike SRAM designs, the circuit configurations of the two
`are totally different. Each row decoder must be a dynamic circuit, while each
`column decoder can be a static circuit, as explained previously. ote that
`to precharge all the row decoders without any de current path, all of the
`complementary addresses are fixed at a low level during a precharge period,
`as shown in Fig. 3.42.
`Figure 3.44 shows dynamic and static decoders, exemplified by two-bit
`address signals. There are two kinds of dynamic decoder in DRAM appli(cid:173)
`cations; NOR and NAND decoders. First, all of the output nodes (Xo-X3)
`are precharged to Vuo by transistors Qp , while keeping all addresses low.
`Then, according to the succeeding valid address signals the output nodes
`are discharged or kept high. Obviously, in NOR decoders all output nodes
`except for a selected one are discharged, while in NAND decoders all output
`nodes except for a selected one are kept high. Thus, NOR decoders suffer
`from a drawback of the large charging and discharging power. The powP.r
`increases with memory capacity, because an increased number of the nodes
`- for example, a few thousands, for multimegabit DRAMs - is involved. On
`the other hand, in N AND decoders only one node is discharged or charged
`up, independently of memory capacity. NAND decoders, however, suffer the
`drawback of a slower speed, because the node is discharged by serially con(cid:173)
`nected (i.e. stacked)