`
`
`Jentsung Lin
`In re Patent of:
`7,693,002 Attorney Docket No.: 39521-0054IP1
`U.S. Patent No.:
`April 6, 2010
`
`Issue Date:
`Appl. Serial No.: 11/548,132
`
`Filing Date:
`October 10, 2006
`
`Title:
`DYNAMIC WORD LINE DRIVERS AND DECODERS FOR
`MEMORY ARRAYS
`
`DECLARATION OF Robert W. Horst, Ph.D.
`
`
`
`I, Robert W. Horst, Ph.D., of San Jose, CA, declare that:
`
`QUALIFICATIONS AND BACKGROUND INFORMATION
`
`1.
`
`I am currently an Adjunct Research Professor in the Department of
`
`Electrical and Computer Engineering the University of Illinois at Urbana-
`
`Champaign and am also an independent consultant at HT Consulting. I am an
`
`independent consultant with more than 30 years of expertise in the design and
`
`architecture of computer systems. I have testified as an expert witness and
`
`consultant in patent and intellectual property litigation as well as inter partes
`
`reviews and re-examination proceedings. My curriculum vitae is provided (as
`
`APPLE-1004).
`
`2.
`
`I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
`
`computer science from the University of Illinois at Urbana-Champaign after
`
`earning my B.S. (1975) in electrical engineering from Bradley University. During
`
`my master’s program, I designed, constructed and debugged a shared memory
`
`1
`
`APPLE 1003
`
`
`
`parallel microprocessor system. During my doctoral program, I designed and
`
`simulated a massively parallel, multi-threaded task flow computer.
`
`3.
`
`After receiving my bachelor’s degree and while pursuing my master’s
`
`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed
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`the micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to
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`1999, I worked at Tandem Computers, which was acquired by Compaq Computers
`
`in 1997. While at Tandem, I was a designer and architect of several generations of
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`fault-tolerant computer systems and was the principal architect of the NonStop
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`Cyclone superscalar processor. The system development work at Tandem also
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`included development of the ServerNet System Area Network and applications of
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`this network to fault tolerant systems and clusters of database servers.
`
`4.
`
`Since leaving Compaq in 1999, I have worked with several
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`technology companies, including 3Ware, Network Appliance, Tibion, and AlterG
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`in the areas of network-attached storage and biomedical devices. From 2012 to
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`2015, I was Chief Technology Officer of Robotics at AlterG, Inc., where I worked
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`on the design of anti-gravity treadmills and battery-powered orthotic devices to
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`assist those with impaired mobility.
`
`5.
`
`In 2001, I was elected an IEEE Fellow “for contributions to the
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`architecture and design of fault tolerant systems and networks.” I have authored
`
`2
`
`
`
`over 30 publications, have worked with patent attorneys on numerous patent
`
`applications, and I am a named inventor on 82 issued U.S. patents.
`
`6. My patents include those directed to memory system design including
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`U.S. Pat. No. 5,146,589 (Refresh control for dynamic memory in multiple
`
`processor system), U.S. Pat. No. 5,287,472 (Memory system using linear array
`
`wafer scale integration architecture), and U.S. Pat. No. 5,329,629 (Apparatus and
`
`method for reading, writing, and refreshing memory with direct virtual or physical
`
`access). My patents also include aspects of circuit design including U.S. Pat. No
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`5,034,964 (N:1 time-voltage matrix encoded I/O transmission system) and U.S.
`
`Pat. No. 9,893,604 (Circuit with low DC bias storage capacitors for high density
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`power conversion).
`
`7.
`
`In writing this Declaration, I have considered the following: my own
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`knowledge and experience, including my work experience in the fields of memory
`
`systems and circuit design and my experience in working with others involved in
`
`those fields. In addition, I have analyzed the following publications and materials,
`
`in addition to other materials I cite in my declaration:
`
`•
`
`U.S. Patent No. 7,693,002 (APPLE-1001), and its accompanying
`
`prosecution history (APPLE-1002)
`
`•
`
`•
`
`U.S. Patent No. 4,951,259 (“Sato”) (APPLE-1005)
`
`U.S. Patent Pub. No. 2006/0098520 (“Asano”) (APPLE-1006)
`
`3
`
`
`
`• Kiyoo Itoh, VLSI Memory Chip Design, (Springer 2001) (“Itoh”)
`
`(APPLE-1007)]
`
`• Stephen Brown et al., Fundamentals of Digital Logic with Verilog
`
`Design, (McGraw Hill 2003) (“Brown”) (APPLE-1009)
`
`• U.S. Patent No. 6,483,771 to Tae-jeen Shin (“Shin”) (APPLE-1011)
`
`
`OVERVIEW OF CONCLUSIONS FORMED
`8.
`
`This expert Declaration explains the conclusions that I have formed
`
`based on my analysis. To summarize those conclusions:
`
`• Based upon my knowledge and experience and my review of the prior
`
`art publications listed above, I believe that claims 1-28 and 31-37 of
`
`the ’002 patent are rendered obvious by Sato.
`
`• Based upon my knowledge and experience and my review of the prior
`
`art publications listed above, I believe that claims 1-17, 20-28, and 31-
`
`36 of the ’002 patent are rendered obvious by Asano and Itoh.
`
`
`BACKGROUND KNOWLEDGE ONE OF SKILL IN THE ART WOULD
`HAVE HAD PRIOR TO THE PRIORITY DATE OF THE ‘002 PATENT
`9.
`
`The technology in the ’002 patent at issue generally relates to a circuit
`
`device that includes a first and second logic to decode a memory address. The
`
`patent specification and figures include CMOS circuits and memory system block
`
`diagrams. Prior to the priority date of the ’002 patent, there existed numerous
`
`4
`
`
`
`products, publications, and patents that implemented or described the functionality
`
`claimed in the ’002 patent. Thus, the methodology of the ’002 patent was well-
`
`known in the prior art. Further, to the extent there was any problem to be solved in
`
`the ’002 patent, it had already been solved in the prior art systems before the
`
`priority date of the ’002 patent.
`
`10. Fig. 1 of the ’002 patent is a block diagram showing the elements for
`
`driving wordlines in a memory array.
`
`5
`
`
`
`’002 Fig 1
`
`
`
`
`11. The wordline drivers are partitioned into “groups,” with each group
`
`including four wordline drivers. The diagram shows the first and last group of the
`
`16 total groups. A group is selected by decoding four bits of the address with the
`
`6
`
`
`
`4-to-16 decoder, which produces the 16 decoder output signals called the “Partially
`
`Decoded Address” in this figure. This signal is also called the “common address
`
`input,” and after passing through an in inverter (shown in Fig. 3 below) is called
`
`the “shared address input,” or “shared address line.” Note that the signal after the
`
`inverter merely changes the AND decoder to a NAND decoder.
`
`the decoded output of the four-to-sixteen bit memory
`address decoder 108 may be utilized via a logical AND
`operation to selectively activate a wordline driver of the
`group of wordline drivers 104, for example.
`
`’002 patent at 4:5-9.
`
`In general, each group of wordline drivers, such as the
`group of wordline drivers 104 may share a common
`partially decoded address input, such as the partially
`decoded address line (0) 120 for the group of wordline
`drivers 104, reducing layout area usage and layout
`complexity.
`
`’002 patent at 3:46-50.
`12. The concept of decoding part of a memory address is well known in
`
`the art. There are often multiple stages of decoding before the final selection that
`
`combines the first stage decoder outputs to select the final output.
`
`13. Continuing with Fig. 1, the selected group of wordline drivers also
`
`receives four clock lines from a “conditional clock generator” that receives a clock
`
`input and four outputs from a decoder, which decodes two more bits of the
`
`memory address. The “conditional clock generator” has no diagram to show the
`
`structure, but is described as follows:
`
`7
`
`
`
`The two-to-four bit decoder112 may decode the first
`portion of the memory address and may provide the
`decoded portion to the conditional clock generator110.
`The conditional clock generator 110 receives a clock
`signal via the clock input 118 and selectively applies the
`clock signal to a selected one of the clock outputs 124,
`126, 128 and 130. . . . In a particular embodiment, the
`conditional clock generator 110 may derive the clock
`outputs 124, 126, 128 and 130 from a single clock.
`
`’002 patent at 3:26-36 (emphasis added).
`14. Here, a POSITA would have understood the clock generator to
`
`produce an output whose characteristics track those of an input clock signal. For
`
`example, a POSITA would have understood “selectively appl[ying] the clock
`
`signal” to a selected output and “deriv[ing] the clock output” to mean simply that
`
`the selected clock output generally tracks with the input clock signal. For example,
`
`the input clock could have been ANDed with the decoder outputs in such a way
`
`that the clock appears on one clock output while the other three are held low. This
`
`structure is also supported by the text that states that the other clocks are held at a
`
`ground voltage level.
`
`In a particular illustrative embodiment, a conditional
`clock generator, such as the conditional clock
`generator110 in FIG. 1, applies the clock signal to a
`selected clock output, such as the clock output 126. The
`other clocks 124, 128 and 130 may be held at a ground
`voltage level.
`
`’002 patent at 5:54-58 (emphasis added).
`
`8
`
`
`
`15. When a group of wordline drivers is selected by receiving the partially
`
`decoded address signal, only one of the clock lines will be active, with the active
`
`clock line determining which wordline to drive.
`
`16. The ’002 patent attributes particular significance to the way it drives
`
`only one of the four clocks at a time, and that the capacitance driven by these
`
`clocks is less than if a single clock were to drive all of the word lines. However, as
`
`is clear from the cited art that follows, the ’002 patent was far from the first to
`
`realize the advantage of driving more clocks with fewer loads per clock. In
`
`particular, Sato, Asano and Itoh all have the same type of conditional clock
`
`generator reducing the capacitive load on each clock.
`
`17. Fig. 2 of the ’002 patent shows four static memory cells, each
`
`represented by latches formed form a pair of inverters. Each bit connects to a word
`
`line, a bit line and a complemented bit line. This particular arrangement of the
`
`memory cell is not part of the issued claims.
`
`18. Fig. 3 shows the internal structure of the wordline drivers.
`
`9
`
`
`
`’002 Fig 3
`
`
`
`19. Each driver is formed with a P-channel and an N-channel transistor,
`
`followed by an inverter. The clock line connects to the gates of the P-channel and
`
`10
`
`
`
`N-channel transistors and the selection signal (inversion of the partially decoded
`
`address) connects to the N-channel transistor’s source terminal.
`
`20. As an example of operation, assume that the address input selects
`
`group 0 and that CLK<0> is enabled. In this case, the output of the inverter
`
`formed by Mp0 and Mn0 drives ddh0 with the inverted clock signal which is then
`
`inverted again as it passes through inverter XWL0 to drive WL<0>. Groups that
`
`are not selected cannot pull lines ddh0-3 low because their N-channel transistor
`
`source lines are not at ground potential.
`
`21. During the low clock phase, when all four CLK signals are low, Mp0-
`
`Mp3 pull all the ddh lines high which pulls all of the wordlines WL<0>-WL<3>
`
`low. A wordline driver with a low clock (and its ddh line high) is said to be in the
`
`static precharge state, and the driver with an active clock is said to be in the
`
`evaluation state.
`
`22. The particular arrangements of transistors in the 002 patent is not
`
`particular unique or noteworthy. For instance, Sato has a nearly identical structure
`
`that has a wordline driver with P and N transistors forming an inverter with input
`
`connected to a conditional clock, and with the N-channel source node connected to
`
`a NAND decoder.
`
`11
`
`
`
`23. Fig 4 of the ’002 patent shows a physical layout of transistors that
`
`could implement the structures shown in the block diagrams. No particular layouts
`
`are part of the issued claims.
`
`24. Fig. 5 is a flowchart describing the structure shown in the block
`
`diagrams. The described steps do not add new information and are largely
`
`redundant with the description of operation of the block diagrams.
`
`25.
`
`In summary, the ’002 patent is primarily disclosing a wordline
`
`decoder with part of the address decoded to select a group, and the selection within
`
`the group determined by a conditional clock based on decoding of other bits of the
`
`memory address. I find that this structure was not unique at that time and similar
`
`or identical wordline decoders were previously disclosed by others including Sato,
`
`Asano and Itoh.
`
`26. A review of other relevant literature available at the time further
`
`shows that the idea of dynamic wordline drivers and decoders for memory arrays
`
`was well known in the technical community by 2006. In addition to the references
`
`I discuss below that render obvious the ’002 patent, the following exemplary
`
`references demonstrate the prevalence of these ideas in the prior art:
`
`• U.S. Patent No. 4,338,679 to James E. O’Toole;
`
`• U.S. Patent No. 5,166,554 to Chitranjan N. Reddy, et al.;
`
`• U.S. Patent No. 5,327,026 to Kim C. Hardee, et al.;
`
`12
`
`
`
`• U.S. Patent No. 6,914,849 to Tai Anh Cao, et al.
`
`27. Thus, based on the foregoing and upon my experience in this area, a
`
`person of ordinary skill in the art in this field at the relevant time frame
`
`(“POSITA”) would have had at least an undergraduate degree in electrical
`
`engineering, or a related field, and three years of experience in the design of
`
`memory systems and circuits. Alternatively, a person of ordinary skill with less
`
`than the amount of experience noted above could have had a correspondingly
`
`greater amount of educational training such a graduate degree in a related field.
`
`28. Based on my experiences, I have a good understanding of the
`
`capabilities of a POSITA. Indeed, I have participated in organizations and worked
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`closely with many such persons over the course of my career.
`
`29.
`
`I am well qualified in the memory and circuit design technologies
`
`related to the ’002 Patent and I was a person of at least ordinary skill in the art in
`
`the ’002 timeframe.
`
`STATE OF THE ART AND OVERVIEW OF TECHNOLOGY AT ISSUE
`
`Circuit design
`30. The ’002 patent and related prior art include circuits presented as
`
`diagrams at the gate level (AND, NAND, OR, NOR and inverters) as well as
`
`diagrams showing individual transistors. The gate-level diagrams use standard
`
`notation for gates and use bubbles to indicate signal inversion.
`
`13
`
`
`
`31. The circuit level diagrams use a variety of different conventions to
`
`draw transistors. For the art cited in this report, the transistors are primarily
`
`enhancement mode metal-oxide-semiconductor field-effect transistors
`
`(MOSFETs), sometimes just called field-effect transistors (FETs). Below I have
`
`shown some of the different ways of drawing these transistors:
`
`S D
`
`’002, Bridges
`
`P-Channel
`MOSFETs
`
`G
`
`G
`
`S D
`
`Sato, Asano
`
`S
`
`D
`
`D
`
`S
`
`
`
`G
`
`Other
`
`S D
`
`G
`
`D S
`
`G
`
`G
`
`D S
`
`G
`
`D S
`
`G
`
`N-Channel
`MOSFETs
`
`32. For the purposes of analyzing the ’002 patent, the P-channel and N-
`
`channel transistors can be analyzed as if they are ideal switches, with the P-
`
`channels conducting when the gate (G) is negative relative to the source (S), and
`
`the N-channels conducting when gate is positive relative to the source.
`
`33. Note that the left two sets of transistor diagrams (as represented in the
`
`’002 patent, Bridges, Sato and Asano) have no indication to show which terminal
`
`is source (S) and which is drain (D). The orientation matters because the FETs
`
`have a “body diode” that always conducts current when the source is at a higher
`
`voltage than the drain, even if the gate voltage would otherwise cause it not to
`
`conduct. It is usually easy for a POSITA to understand which terminal should be
`
`14
`
`
`
`connected to the source because the source usually connects to a positive voltage
`
`rail for a P-channel and to ground for an N channel. However, in some circuits,
`
`more analysis may be needed to determine the transistor orientations. The right
`
`two representations for transistors do not have this ambiguity and clearly indicate
`
`which terminal is the source and which is the drain. The fact that the ’002 patent
`
`uses the ambiguous notation indicates that a POSITA should be assumed to have
`
`sufficient skill in circuit design to understand how such transistors would normally
`
`be connected.
`
`34. Most of the circuits in this report show a mix of N-channel and P-
`
`channel transistors, often configured as standard CMOS circuits. For instance, a
`
`CMOS inverter has N-channel and P-channel transistors with gates connected
`
`together, the source terminals to ground and the positive voltage rail, and the drains
`
`connected together and to the output.
`
`Clocked decoder circuits
`35. Clocked decoder circuits are well known in the art. Patent 5,291,076
`
`(the “Bridges” patent) gives several examples of clocked decoder circuits. Fig. 1
`
`of Bridges, reproduced below, shows a simple clocked decoder.
`
`15
`
`
`
`
`
`Bridges ‘076, Fig 1
`
`36. Bridges’ Fig. 1 shows a CLOCK signal that, when low, causes P-
`
`channel transistor Q4 to conduct to precharge node 12. When CLOCK transitions
`
`to high, the precharge is removed and if the A1-A3 are all high, N-channel
`
`MOSFETs Q1, Q2, Q3 and Q5 all conduct to cause 12 to be pulled low. Note that
`
`if any of the A1-A2 inputs is low, no current passes through Q1-Q4 to pull node 12
`
`low or high and the node stays at the high level until leakage or other events cause
`
`the node to drift back down to the low logic level. See e.g., Bridges, 3:1-4:24.
`
`37. A full clocked decoder circuit would include eight copies of the
`
`NAND gate of Fig 1, each with the eight different combinations of true and
`
`complement inputs A1-A3. After the precharge, one of the eight decoder outputs
`
`is pulled low and the other seven remain high, causing a single output line to be
`
`selected. This type of decoder is called a NAND decoder because each output has
`
`16
`
`
`
`the same structure as a NAND gate. The function is the same as a NAND gate in
`
`which the output is low only when all inputs are high.
`
`38. The clock input of a clocked decoder switches between two phases of
`
`operation that are often referred to as the precharge and evaluation phases.
`
`39. Other examples of clocked decoder are shown in all three of Sato’s
`
`embodiments, as shown in Sato Fig. 1, 2 and 3. These circuits employ clocked
`
`decoders controlled by the timing (clock) signal 𝜙ce. When 𝜙ce is low, these
`lines W0-W3 low. When 𝜙ce is high, the circuits evaluate the address lines
`
`circuits precharge the inputs to the final inverters which then drive all of the word
`
`causing a single input to a final inverter to be pulled low, thus causing only that
`
`word line to be driven high while the others are driven low.
`
`SRAM and DRAM
`40. The common acronyms SRAM and DRAM stand for Static Random
`
`Access Memory and Dynamic Random Access Memory. In general, these terms
`
`refer to whether the memory cells are static and hold information indefinitely, or
`
`the cells are dynamic and need to be periodically refreshed to maintain their state.
`
`Other parts of memory chips can also be static or dynamic independently of
`
`whether the memory cells are static or dynamic.
`
`41. The ’002 patent is directed to “dynamic wordline drivers and decoders
`
`for memory arrays.” ’002 patent at 1:8-9. Dynamic (clocked) drivers and
`
`17
`
`
`
`decoders can be used in both SRAMs and DRAMs. As in the ’002 patent, some of
`
`the cited prior art cited does not require any particular type of memory cell and
`
`those techniques could be applied to SRAM, DRAM or other types of memory.
`
`
`INTERPRETATIONS OF THE ’002 PATENT CLAIMS AT ISSUE
`
`42.
`
`I understand that the best indicator of claim meaning is its usage in the
`
`context of the patent specification as understood by a POSITA. I further
`
`understand that the words of the claims should be given their plain meaning unless
`
`that meaning is inconsistent with the patent specification or the patent’s history of
`
`examination before the Patent Office. I also understand that the words of the
`
`claims should be interpreted as they would have been interpreted by a POSITA at
`
`the time of the invention was made (not today). Because I do not know at what
`
`date the invention as claimed was made, I have used the earliest priority date of
`
`U.S. Patent No. 7,693,002 as the point in time for claim interpretation purposes.
`
`That date was October 10, 2006. I have been asked to provide my interpretation of
`
`the following terms and phrases of the ’002 patent set forth below.
`
`Claim Constructions
`
`“static precharge state”
`
`43. Claims 18 and 37 recite: “wherein other wordline drivers of the
`
`group of wordline drivers are in a static precharge state.” In my opinion, the
`
`plain meaning of the claim term “static precharge state” in view of the ’002
`
`18
`
`
`
`patent specification would include a state in which a fixed voltage level is applied
`
`to a wordline driver. See my analysis at paragraphs 19-21 and the ’002 patent at
`
`3:52-57; 7:11-15.
`
`44. Based upon my knowledge and experience in this field, I believe that
`
`a POSITA would have understood that this interpretation is consistent with the
`
`plain meaning of this term and is consistent with the ’002 patent specification.
`
`“conditional clock generator”
`
`45. Claim 2 recites “conditional clock generator to receive the clock
`
`signal and to selectively apply the clock signal to the selected clock output.”
`
`Claims 3, 9, 13, 20-22, 27, 31, 32, and 37 recite similar language. In my opinion,
`
`the plain meaning of the claim term “conditional clock generator” in view of the
`
`’002 patent specification would include a circuit component that applies a clock
`
`signal to one of several output terminals. See my analysis at paragraphs 13-15 and
`
`the ’002 patent at 3:26-31; 5: 54-58.
`
`46. Based upon my knowledge and experience in this field, I believe that
`
`a POSITA would have understood that this interpretation is consistent with the
`
`plain meaning of this term and is consistent with the ’002 patent specification.
`
`“means for decoding a first portion of a memory address of a memory
`
`array”
`
`19
`
`
`
`47. Claim 11 recites: “means for decoding a first portion of a memory
`
`address of a memory array.” In my opinion, the ’002 patent specification
`
`describes a “decoder” as a structure for performing the function of “decoding a
`
`first portion of a memory address of a memory array.” See my analysis at
`
`paragraphs 13-15; 35-39 and the ’002 patent at 3:26-31; 5: 54-58.
`
`48. Based upon my knowledge and experience in this field, I believe that
`
`a POSITA would have understood that this interpretation is consistent with the
`
`plain meaning of this term and is consistent with the ’002 patent specification.
`
`“means for selectively providing a clock signal to a selected group of
`
`wordline drivers based on the first portion of the memory address [of a
`
`memory array]”
`
`49. Claims 11 and 27 recite: “means for selectively providing a clock
`
`signal to a selected group of wordline drivers based on the first portion of the
`
`memory address [of a memory array].” In my opinion, the ’002 patent
`
`specification describes a “conditional clock generator” as a structure for
`
`performing the function of “selectively providing a clock signal to a selected
`
`group of wordline drivers based on the first portion of the memory address [of
`
`a memory array].” See my analysis at paragraphs 13-15 and the ’002 patent at
`
`3:26-31; 5: 54-58.
`
`20
`
`
`
`50. Based upon my knowledge and experience in this field, I believe that
`
`a POSITA would have understood that this interpretation is consistent with the
`
`plain meaning of this term and is consistent with the ’002 patent specification.
`
`“means for decoding a second portion of the memory address”
`
`51. Claim 11 recites: “means for decoding a second portion of the
`
`memory address.” In my opinion, the ’002 patent specification describes a
`
`“decoder” as a structure for performing the function of “decoding a second
`
`portion of the memory address.” See my analysis at paragraphs 11-12, 35-39
`
`and the ’002 patent at 3:46-50; 4:5-9.
`
`52. Based upon my knowledge and experience in this field, I believe that
`
`a POSITA would have understood that this interpretation is consistent with the
`
`plain meaning of this term and is consistent with the ’002 patent specification.
`
`“means for activating a particular wordline driver of the selected group
`
`of wordline drivers according to the second portion of the memory
`
`address”
`
`53. Claims 11 and 27 recite: “means for activating a particular
`
`wordline driver of the selected group of wordline drivers according to the
`
`second portion of the memory address.” In my opinion, the ’002 patent
`
`specification describes a “decoder” as a structure for performing the function of
`
`“activating a particular wordline driver of the selected group of wordline
`
`21
`
`
`
`drivers according to the second portion of the memory address.” See my
`
`analysis at paragraphs 11-12, 18-22 and the ’002 patent at 3:46-50; 4:5-9.
`
`54. Based upon my knowledge and experience in this field, I believe that
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`a POSITA would have understood that this interpretation is consistent with the
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`plain meaning of this term and is consistent with the ’002 patent specification.
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`“means for applying the second portion of the memory address to a
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`shared address line”
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`55. Claim 14 recites: “means for applying the second portion of the
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`memory address to a shared address line.” In my opinion, the ’002 patent
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`specification describes a “decoder” as a structure for performing the function of
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`“decoding a second portion of the memory address.” See my analysis at
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`paragraphs paragraphs 11-12, 18-22 and the ’002 patent at 3:46-50; 4:5-9.
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`56. Based upon my knowledge and experience in this field, I believe that
`
`a POSITA would have understood that this interpretation is consistent with the
`
`plain meaning of this term and is consistent with the ’002 patent specification.
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`ANALYSIS OF SATO
`57. Sato discloses an X address decoder XCDR for either an SRAM or
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`DRAM memory array. Sato’s XCDR decodes a memory address (AX0-AXi) to
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`drive selected wordlines (WD0-WDm) of a memory array as indicated by the
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`address. The XCDR includes a pre-decoder PDCR and NAND decoder circuits
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`22
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`
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`(NAG0-NAGk) which each decode a portion of the memory address to activate an
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`appropriate wordline driver.
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`58. As I illustrated in the annotated Fig. 3 from Sato (below), Sato’s X
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`address decoder (XDCR) includes an address input (e.g., internal address input
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`(ax0-axi)) as shown in Fig. 3 and Fig. 4. The PDCR has four clock outputs (𝜙x0-
`𝜙x3). Sato’s Figure 3 shows wordline drivers (e.g., wordline drive circuits WD0-
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`WD3 along with precharge transistors Q19~Q20 and reset transistors Q29~Q30)1
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`coupled to respective wordlines (e.g., W0-W3) of memory array (e.g., M-ARY).
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`Each of the wordline drivers (e.g., WD0-WD3) is coupled to part of the address
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`input (bits ax2-axi) through the NAND gate decoding circuits, and to the rest of the
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`address input (bits ax0-ax1) through the predecoder PDCR. Each wordline driver
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`is also coupled to one of the clock outputs (𝜙x0-𝜙x3) as shown in Fig. 3.
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`1 For simplicity Sato’s wordline drivers are referred to by (WD0-WD3) throughout
`to avoid repeating the combination of Sato’s wordline drive circuits WD0-WD3,
`precharge transistors Q19~Q20, and reset transistors Q29~Q30.
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`23
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`
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`Sato Fig. 3 (annotated)
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`
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`59. Annotated Fig.3 (below) of Sato shows Sato’s X address decoder
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`including structures meeting the limitations of the first and second logic of the ’002
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`patent. Operations of Sato’s first and second logic are described in detail below.
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`24
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`
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`Sato Fig. 3 (annotated to highlight first and second logic)
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`
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`60. The annotations in Fig. 3 above show that the pre-decoder PDCR
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`meets the limitation for the first logic because it receives both a timing (clock)
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`signal and a portion of the memory address. PDCR decodes two bits of the
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`memory address, ax0 and ax1. PDCR in Fig.3 receives timing signal 𝜙ce while
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`PDCR in Fig.1 does not, although the same decoding function is described for
`
`these embodiments:
`
`address buffer XADB and generates selection signals 𝜙x0-𝜙x3.
`These selection signals 𝜙x0-𝜙x3 are formed selectively in
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`The pre-decoder PDCR decodes the lower 2-bit complementary
`internal address signals ax0 and axl supplied thereto from the X
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`accordance with the complementary internal address signals ax0
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`25
`
`
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`and ax1. In other words, the selection signal 𝜙x0 is set to the high
`𝜙x1, 𝜙x2 and 𝜙x3 are set to the high logic level when both the
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`logic level when both the inversed internal address signals ax0
`and ax1 are at the high logic level. Similarly, the selection signals
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`non-inversed internal address signal ax0 and the inversed internal
`address signal ax1 are at the high logic level, when both the
`inversed internal address signal ax0 and non-inversed internal
`address signal ax1 are at the high logic level and when both the
`non-inversed internal address signals ax0 and ax1 are at the high
`logic level, respectively.
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`Sato at 5:25-42 (emphasis added).
`61. The function of the timing signal input to PDCR in the third
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`embodiment is described as follows:
`
`In FIG. 3, the X address decoder XDCR of the CMOS static
`RAM of this embodiment includes one pre-decoder PDCR and
`k+1 decoding NAND gate circuits NAG0-NAGk in the same
`way as in the foregoing embodiments. …
`
`In the X address decoder XDCR of this embodiment, the afore-
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`supplied to the pre-decoder PDCR. Accordingly, the CMOS
`static RAM is brought into the selection state and the timing
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`mentioned timing signal 𝜙ce (selection control signal) is
`signal 𝜙ce is set to the high logic level so that the output signal
`of the pre-decoder PDCR, that is, the selection signal 𝜙x0-𝜙x3,
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`is set selectively to the high logic level.
`
`Sato at 9:44-59 (emphasis added).
`62. Sato does not provide a diagram the internals of XDCR in Fig. 3, but
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`the text description above provides enough detail for a POSITA to understand that
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`it performs a function equivalent to four AND gates as I have drawn below. This
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`structure is also equivalent to how a POSITA would have understood the operation
`
`26
`
`
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`of the ’002 patent’s conditional clock generator, as I described above in paragraphs
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`13-16.
`
`
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`Illustration of the internal structure of the PDCR decoder in Sato Fig. 3
`
`
`63. Furthermore, Brown’s digital logic textbook corroborates this
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`understanding. Brown describes the operation of a demultiplexer circuit that is the
`
`same as my illustration above. See Brown, 314-315, Fig. 3.16. In reference to Fig.
`
`3.16, which I have reproduced below, Brown describes:
`
`The demultiplexer can be implemented using a decoder circuit.
`For example, the 2-to-4 decoder in Figure 6.16 can be used as a
`1-to-4 demultiplexer. In this case the En input serves as the data
`input for the demultiplexer, and the y0 to y3 outputs are the data
`outputs. The valuation of w1w0 determines which of the outputs
`is set to the value of En. To see how the circuit works, consider
`the truth table in Figure 6.16a. When En = 0, all the outputs are
`set to 0, including the one selected by the valuation of w1w0.
`When En = 1, the valuation of w1w0 sets the appropriate output
`to 1.
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`Brown, 315 (emphasis added).
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`27
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`
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`Brown’s description also corresponds to the operations of Sato’s PDCR. Like
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`Brown’s signals w0 and w1, the values of Sato’s address signals (ax0 and ax1)
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`select one of four outputs (𝜙x0-𝜙x3) and force the non-selected outputs low. Like
`Brown’s enable signal En, the value of timing signal 𝜙ce is passed through to the
`selected output; when En (𝜙ce) is low, the selected output is low and when En
`(𝜙ce) is high, the selected output is high.
`
`
`
`28
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`
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`Clock signal
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`64. The operations of Sato’s address decoder are coordinated by a timing
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`similar to or equivalent to that of a clock signal because 1) “clock” is another name
`
`signal. A POSITA would have viewed the function of the timing signal 𝜙ce as
`for a timing signal, 2) the Greek symbol phi