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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Apple Inc.
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-01249
`Patent 7,693,002
`______________________
`
`PATENT OWNER RESPONSE TO PETITION FOR INTER PARTES
`REVIEW PURSUANT TO 37 C.F.R. § 42.220
`
`
`
`
`
`

`

`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`I. 
`THE ALLEGED GROUNDS OF UNPATENTABILITY ............................. 6 
`II. 
`III.  OVERVIEW OF THE ’002 PATENT ............................................................ 7 
`IV.  CLAIM CONSTRUCTION .......................................................................... 11 
`V. 
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 15 
`VI.  OVERVIEW OF THE CITED REFERENCES ............................................ 16 
`A.  Overview of Sato ................................................................................. 16 
`B.  Overview of Asano .............................................................................. 23 
`C.  Overview of Itoh ................................................................................. 26 
`VII.  SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`
`(GROUND 1) ................................................................................................. 27 
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`A. 
`
`over Sato. ............................................................................................. 28 
`B. 
`Sato Does Not Teach or Suggest the “Clock Signal” Required by the
`
`Claims. ................................................................................................. 30 
`1. 
`Used for Synchronization,” As Required Under the Proper
`
`Construction of the Term “Clock Signal.” ................................ 30 
`
`Sato Discloses an Asynchronous Memory System That Does
`2. 
`Not Use a Periodic Clock Signal. ............................................. 33 
`
`Petitioner’s Assertion That Sato’s Selection Control Signal
`3. 
`“Represents or Renders Obvious a Clock Signal” Is
`
`Erroneous. ................................................................................. 35 
`
`Sato Does Not Teach or Suggest the “Clock Output” Required by the
`Claims. ................................................................................................. 45 
`
`Sato’s Selection Control Signal (cid:2038)ce is Not a “Periodic Signal
`
`C. 
`
`
`

`

`VIII. 
`
`
`ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28,
`AND 31-36 OBVIOUS (GROUND 2) ............................................... 47 
`A.  Asano Does Not Disclose or Suggest a Circuit Device Including
`
`Distinct “First Logic” and “Second Logic.” ....................................... 48 
`B. 
`The Petition Does Not Sufficiently Articulate Why a POSA Would
`
`Allegedly Have Been Motivated to Combine Asano and Itoh............ 53 
`IX.  CONCLUSION .............................................................................................. 58 
`
` 
`
`

`

`Pursuant to the Board’s Decision – Institution of Inter Partes Review
`
`(Paper 6), entered January 15, 2019 – Patent Owner Qualcomm, Inc. (“Qualcomm”
`
`or “Patent Owner”) submits this response in opposition to the petition for inter partes
`
`review of U.S. Patent No. 7,693,002 (the “’002 patent”) filed by Apple Inc. (“Apple”
`
`or “Petitioner”).
`
`I.
`
`INTRODUCTION
`The ’002 patent describes and claims an improved wordline driver system. In
`
`that system, a received memory address specifying a particular wordline of a
`
`memory array is split into first and second portions. Ex. 1001 at 3:18-25. A first
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`logic receives and decodes the first portion of the memory address, and a second
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`logic receives and decodes the second portion. Id. at 3:26-28, 3:37-40. The first
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`logic also receives a clock signal and applies the clock signal to a selected clock
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`output based on the first portion of the memory address. Id. at 3:28-36, 9:35-40.
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`The second logic, by contrast, selectively activates a particular wordline driver based
`
`on the second portion of the memory address. Id. at 3:9-4:8. With this arrangement,
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`the clock loading for the synchronous memory circuit is significantly reduced.
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`Ex. 2001 at ¶¶34-35, 67. The first and second logics of the ’002 patent are shown
`
`in the annotated illustration below.
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`
`
`1
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`

`

`
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`Paper 2 at 8.
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`
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`The first and second logics operate independently of each other and apply
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`their respective outputs directly to wordline drivers in parallel, thus reducing a
`
`timing delay in providing the clock signal to a particular wordline driver. Ex. 2001
`
`
`
`2
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`

`

`at ¶¶35, 67. These and other benefits are described in the patent’s specification. See,
`
`e.g., Ex. 1001 at 1:61-2:19.
`
`
`
`In this IPR, Petitioner submits references that are far afield from the invention
`
`of the ’002 patent and do not provide any of its benefits. Petitioner’s Ground 1
`
`asserts that claims 1-28 and 31-37 of the ‘002 patent are obvious over a single
`
`reference, Sato (Ex. 1005). Petitioner’s presentation of Sato as an obviousness
`
`ground—rather than anticipation—shows that Sato does not disclose all limitations
`
`of the challenged claims, and the deficiencies of Sato are readily apparent. First,
`
`Sato does not disclose or suggest a “clock signal,” as claimed. The reference is
`
`directed to an asynchronous memory system that uses multiple, non-periodic timing
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`signals, and the person of ordinary skill in the art (POSA) would not consider any of
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`these signals to be a clock signal.
`
`
`
`The asynchronous memory system of Sato is fundamentally different than the
`
`synchronous memory system of the ’002 patent. As explained below, synchronous
`
`memory systems use a periodic clock signal to time all memory operations. By
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`contrast, asynchronous memory systems, like those of Sato, are configured to receive
`
`asynchronous inputs and generate multiple, non-periodic timing signals to control
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`the movement of data in the memory system. Accordingly, the POSA would not be
`
`motivated to modify Sato to use a periodic clock signal because the use of such a
`
`signal would be contrary to how asynchronous systems operate.
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`
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`
`
`3
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`

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`
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`Second, even if Sato could be understood to disclose a clock signal, the
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`reference does not disclose the claimed “clock outputs.” Petitioner argues that
`
`Sato’s predecoder PDCR generates signals (cid:2038)x0, (cid:2038)x1, (cid:2038)x2, and (cid:2038)x3 that are clock
`outputs. Paper 2 at 18-23. But Sato never refers to the signals (cid:2038)x0~(cid:2038)x3 as “timing
`(cid:2038)x0~(cid:2038)x3 exclusively as “selection signals.” See, e.g., Ex. 1005 at 5:25-28. Further,
`circuitry that would suggest the signals (cid:2038)x0~(cid:2038)x3 are clock outputs.
`
`signals,” much less “clocks” or “clock outputs.” Rather, Sato refers to the signals
`
`the predecoder PDCR is a black box—Sato provides no disclosure on its internal
`
`
`
`Petitioner’s Ground 2 fares even worse. This ground asserts that claims 1-17,
`
`20-28, and 31-36 are obvious over the combination of Asano (Ex. 1006) and Itoh
`
`(Ex. 1007). Petitioner relies on Asano as the “base reference” of Ground 2 (Paper 2
`
`at 33), but this reference fails to disclose fundamental aspects of the ’002 patent
`
`invention: The reference does not disclose splitting a memory address into a “first
`
`portion” and “second portion,” nor does it disclose sending the first and second
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`portions to distinct first and second decoding logics, respectively. In Asano, the
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`entire memory address is received and decoded by a single predecoder 202:
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`
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`4
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`

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`
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`Ex. 1007 at Fig. 2 (highlighting added).
`
`
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`Petitioner attempts to remedy the deficiencies of Asano with Itoh, arguing that
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`Asano’s predecoder 202 could be implemented with a specific implementation of
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`separate decoders disclosed by Itoh arranged in a specific way. Paper 2 at 35. But
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`Petitioner has not sufficiently articulated why the POSA allegedly would have been
`
`motivated to combine Asano and Itoh in the way suggested by Petitioner. Petitioner
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`and its declarant, Dr. Robert Horst, acknowledge that there are a variety of different
`
`ways to implement Asano’s predecoder 202. See, e.g., Ex. 1003 (Horst Decl.) at
`
`¶118, Ex. 2005 (Horst Depo. Transcript) at 50:7-52:18. Despite this, Petitioner fails
`
`to provide any reason why the POSA allegedly would have selected the decoders of
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`Itoh, specifically, from among the many different ways of implementing the
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`predecoder 202. Petitioner’s obviousness ground is therefore deficient.
`
`
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`5
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`

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`
`
`Additionally, Dr. Horst’s declaration (Ex. 1003) provides nothing more than
`
`a vague prior-art analysis without addressing the full language of a single claim of
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`the ’002 patent. In fact, Dr. Horst readily admits that his declaration fails to provide
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`analysis of any of the claims as a whole. Ex. 2005 at 54:19-57:11. Petitioner relies
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`on Dr. Horst’s vague and non-specific declaration testimony in support of its
`
`obviousness grounds, but an allegation of obviousness cannot be supported without
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`reference to the specific language of the claims, read in the context of the claim as a
`
`whole. See Stratoflex, Inc. v. Aeroquip Corp., 713 F.2d 1530, 1537 (Fed. Cir. 1983).
`
`Having admittedly failed to address any of the claims as a whole in his declaration,
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`Dr. Horst’s testimony cannot properly support a conclusion of obviousness and
`
`should therefore be given little to no weight.
`
`For at least these reasons and those detailed below, challenged claims 1-28
`
`and 31-37 of the ’002 patent should be confirmed.
`
`II. THE ALLEGED GROUNDS OF UNPATENTABILITY
`Pursuant to the Board’s institution decision (Paper 6 at 18), the alleged
`
`grounds of unpatentability for this trial are:
`
` Ground 1 – Claims 1-28 and 31-37 are unpatentable under 35 U.S.C.
`
`§ 103 over Sato; and
`
` Ground 2 – Claims 1-17, 20-28, and 31-36 are unpatentable under
`
`35 U.S.C. § 103 over Asano in view of Itoh.
`
`
`
`6
`
`

`

`(Paper 2 at 2.)
`
`III. OVERVIEW OF THE ’002 PATENT
`
`The ’002 patent, titled “Dynamic Word Line Drivers and Decoders for
`
`Memory Arrays,” was filed on October 10, 2006, and issued on April 6, 2010. The
`
`patent describes wordline driver systems and methods for selectively activating a
`
`wordline driver of a group of wordline drivers. Fig. 1 of the ’002 patent illustrates
`
`a wordline driver system 100 including groups of wordline drivers 104, 106 that are
`
`associated with a memory array 102 (id. at 2:53-56):
`
`
`
`7
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`

`

`
`
`Id. at Fig. 1.
`
`
`
`In the example of Fig. 1, a six-bit memory address specifying one of sixty-
`
`four wordlines in the memory array 102 is received. Id. at 3:18-20. The six-bit
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`memory address is divided into first and second portions, and a two-to-four bit
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`memory address decoder 112 receives the first portion (e.g., bits zero and one), and
`
`
`
`8
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`

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`a four-to-sixteen bit memory address decoder 108 receives the second portion
`
`(e.g., bits two to five) (id. at 3:20-25):
`
`
`
`Id. at Fig. 1 (highlighting added).
`
`
`
`
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`The two-to-four bit memory address decoder 112 decodes the first portion of
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`the memory address and provides the decoded portion to a conditional clock
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`generator 110. Id. at 3:26-28. The conditional clock generator 110 receives the
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`decoded portion and further “receives a clock signal via … clock input 118.” Id.
`
`at 3:28-31. The conditional clock generator 110 selectively applies the clock signal
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`to a selected one of clock outputs 124, 126, 128, 130 based on the first portion of the
`
`memory address. Id. at 3:28-31, 9:35-40. The non-selected clock outputs are held
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`at a fixed voltage level. Id. at 3:52-62.
`
`
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`9
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`

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`
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`Each of the clock outputs 124, 126, 128, 130 is coupled to a particular
`
`wordline driver of each of the groups of wordline drivers. Id. at 3:31-34. For
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`example, in Fig. 1, the clock output 124 may be coupled to the wordline driver
`
`having the lowest number in each group (e.g., WL<0> in group 104, WL<60> in
`
`group 106, and so on). See id. at 3:67-4:3. In a group of wordline drivers, the driver
`
`that receives the clock signal is in a dynamic evaluation state, whereas the other three
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`drivers of the group that do not receive the clock signal are in a static precharge state.
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`Id. at 3:52-62.
`
`
`
`The four-to-sixteen bit memory address decoder 108 decodes the second
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`portion of the memory address and “applies a partial address input to the wordlines
`
`that are related to the decoded memory address.” Id. at 3:37-40. The outputs of the
`
`conditional clock generator 110 and the four-to-sixteen bit memory address
`
`decoder 108 are used together to activate a particular wordline driver. Id. at 3:62-
`
`4:8. More specifically, “the decoded output of the two-to-four decoder 112 with
`
`clock generator 110 and the decoded output of the four-to-sixteen bit memory
`
`address decoder 108 may be utilized via a logical AND operation” to selectively
`
`activate a wordline driver. Id. at 4:3-8.
`
`
`
`The invention of the ’002 patent provides numerous advantages. Id. at 1:61-
`
`2:19. These advantages include, among others, reduced loading on the clock signal,
`
`increased capacitive noise-coupling immunity between wordline driver outputs,
`
`
`
`10
`
`

`

`lower timing delay from a clock to a particular wordline, and reduced power
`
`consumption. See id.; see also Ex. 2001 at ¶¶34-35.
`
`Claim 1 of the ’002 patent illustrates the claimed invention:
`
`1. A circuit device comprising:
`
`first logic to receive a clock signal and a first portion of a
`
`memory address of a memory array, the first logic to decode the first
`portion of the memory address and to apply the clock signal to a
`selected clock output of a plurality of clock outputs associated with a
`selected group of a plurality of wordline drivers that are associated
`with the memory array; and
`
`second logic to decode a second portion of the memory address,
`
`the second logic to selectively activate a particular wordline driver of
`the selected group of wordline drivers according to the second portion
`of the memory address.
`
`Id. at 10:65-11:10.
`
`IV. CLAIM CONSTRUCTION
`
`37 C.F.R. § 42.100(b) states that claims must be given their broadest reasonable
`
`interpretation in light of the specification (“BRI”).
`
`
`
`
`
`“Clock Signal”
`
`The term “clock signal,” as recited in each of the independent claims of
`
`the ’002 patent, should be interpreted to mean “a periodic signal used for
`
`synchronization.” This interpretation is consistent with the plain and ordinary
`
`
`
`11
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`

`

`meaning of the term as understood by the POSA. Ex. 2001 at ¶53. The POSA’s
`
`understanding of the term is reflected, for example, by the IEEE Dictionary, which
`
`defines the term “clock signal” as “[a] periodic signal used for synchronizing events.”
`
`Ex. 2002 at 9. The IEEE Dictionary is a reliable, unbiased authority that sets forth
`
`the definition of clock signal that would be understood by the POSA as of the filing
`
`date of the ’002 patent. Ex. 2001 at ¶53.
`
`
`
`Support for this interpretation is also found in the ’002 patent itself.
`
`Specifically, the POSA would understand that the ’002 patent describes a
`
`synchronous memory system that uses a periodic clock signal. Id. at ¶54.
`
`The ’002 patent does not describe an asynchronous memory system that uses
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`multiple, non-periodic timing signals. Id. This is explained below and in further
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`detail in the attached declaration of Dr. Massoud Pedram. Id. at ¶¶54-69.
`
`
`
`As explained by Dr. Pedram, certain memory systems are controlled
`
`asynchronously, which means that externally provided inputs to the memory system
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`can arrive at any time, for example, driven by a memory read or write event. Id.
`
`at ¶¶55-60. The timing of such inputs is not synchronized with rising or falling
`
`edges of a periodic clock signal. Id. Thus, asynchronous memory systems are event-
`
`driven and must include control circuitry for receiving the asynchronous inputs and
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`generating appropriately timed sequences of internal timing signals to control the
`
`movement of data in the memory. Id. Neither the asynchronous inputs nor the
`
`
`
`12
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`

`

`internal timing signals are periodic, and none of them are commonly referred to as
`
`“clocks” or “clock signals.” Id. The duration and precise timing of the internal
`
`timing signals is key to the correct operation of the asynchronous memory system,
`
`and multiple timing constraints among external control signals and address/data
`
`signals must be satisfied. Id.
`
`
`
`By contrast, in a memory system that is controlled synchronously, a single,
`
`periodic, synchronizing clock is used to time all memory operations. Id. at ¶¶61-64.
`
`In synchronous memory systems, this synchronizing clock is expressly referred to
`
`as a “clock,” “clock signal,” or an abbreviation such as “CLK” or “CK.” Id.
`
`Externally provided control signals and address/data signals are all synchronized
`
`with respect to the periodic clock, and the internal circuitry of the memory system
`
`operates in synchrony with the clock signal. Id. The timing constraints of
`
`synchronous memory systems are fundamentally different
`
`than
`
`those of
`
`asynchronous memory systems, and all such constraints are described with reference
`
`to edges of the single, periodic clock signal. Id.
`
`
`
`The POSA would understand that the ’002 patent discloses a synchronous
`
`memory system that uses a periodic clock signal, rather than an asynchronous
`
`memory system. Id. at ¶¶65-69. The invention of the ’002 patent does not use
`
`multiple, internal timing signals for controlling the movement of data within the
`
`memory system, nor does the patent describe control logic circuitry for generating
`
`
`
`13
`
`

`

`such signals. Id. at ¶65. As described above, such timing signals are necessary for
`
`correct operation of asynchronous memory systems, but they are generally not
`
`employed in synchronous memory systems that use a periodic clock signal. Id.
`
`Further, as confirmed by Petitioner’s declarant Dr. Horst (Ex. 2005 at 14:16-22), the
`
`memory system of the ’002 patent uses a single clock signal, rather than multiple
`
`timing signals, which is consistent with synchronous systems’ use of a single,
`
`periodic clock signal. Ex. 2001 at ¶66.
`
`
`
`Additionally, the ’002 patent does not describe any timing constraints among
`
`external control signals and address/data signals. Id. These timing constraints, as
`
`described above, are important considerations in asynchronous memory systems, but
`
`no such timing constraints exist in synchronous memory systems. Id. The ’002
`
`patent’s lack of any description of these important aspects of asynchronous memory
`
`systems evidences that the invention is not directed to an asynchronous system but
`
`rather a synchronous system that uses a periodic clock signal. The intrinsic evidence
`
`thus supports the interpretation of the claim term “clock signal” as “a periodic signal
`
`used for synchronization.” Id. at ¶¶65-69.
`
`
`
`Petitioner did not propose a construction for the term “clock signal” in its
`
`petition. See Paper 2 at 3-7. However, Petitioner’s expert in the related ITC
`
`proceeding involving the ’002 patent, Dr. Donald Alpert, previously provided
`
`relevant testimony. Specifically, in another IPR proceeding not directed to
`
`
`
`14
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`

`

`the ’002 patent, but addressing the meaning of the claim term “clock,” Dr. Alpert
`
`told the Board that the term “clock” should be interpreted as “a periodic signal used
`
`for synchronization.” Ex. 2004 at 3-4. Dr. Alpert stated that the “definition [‘a
`
`periodic signal used for synchronization’] is consistent with the broadest reasonable
`
`interpretation of the term [‘clock’].” Id. Dr. Alpert’s statement provides further
`
`support for Qualcomm’s proposed construction.
`
`
`
`For at least these reasons, the term “clock signal” should be interpreted to
`
`mean “a periodic signal used for synchronization.”
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`
`For purposes of the trial in this proceeding, Qualcomm accepts Petitioner’s
`
`proposed education and experience level of one of ordinary skill in the art, as
`
`modified by the Board’s institution decision. See Paper 2 at 2; Paper 6 at 6. Thus,
`
`for purposes of the trial in this proceeding, the POSA for the ’002 patent would have
`
`had an undergraduate degree in electrical engineering, or a related field, and three
`
`years of experience in the design of memory systems and circuits. Alternatively, a
`
`person of ordinary skill with less than the amount of experience noted above would
`
`have had a correspondingly greater amount of educational training such a graduate
`
`degree in a related field. See id.
`
`
`
`15
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`

`

`VI. OVERVIEW OF THE CITED REFERENCES
`A. Overview of Sato
`U.S. Patent No. 4,951,259 (“Sato”), titled “Semiconductor Memory Device
`
`
`
`with First and Second Word Line Drivers,” relates generally to semiconductor
`
`memory devices. Ex. 1005 at 1:6-9. Sato was filed on February 18, 1988, and issued
`
`on August 21, 1990.
`
`
`
`Sato explains that “[i]n large memory arrays, the word line driver circuits can
`
`place large capacitive loads on the output of the logic decoding circuit because the
`
`word line driver transistors must be relatively large. This large load on the logic
`
`decoding circuitry adversely effects the operating speed of the memory.” Id. at
`
`Abstract. To reduce this load, Sato describes a “switching arrangement [that] is
`
`provided between the output of the logic decoding circuitry and the word line
`
`drivers.” Id. In Fig. 3 of Sato, the switching arrangement comprises capacitance cut
`
`MOSFETs Q19 and Q20 disposed between output terminals of decoding NAND
`
`gate circuit NAG0 and the input terminals of wordline drivers WD0-WD3 (id. at
`
`9:60-65):
`
`
`
`16
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`

`

`Id. at Fig. 3 (highlighting added). Through the use of the capacitance cut MOSFETs
`
`Q19 and Q20, the decoding NAND gate circuit NAG0 is isolated from the wordline
`
`
`
`drivers WD0-WD3, and the capacitive load on the output terminals of the decoding
`
`NAND gate circuit NAG0 is thereby reduced. Id. at 2:21-35, 10:60-66. The
`
`capacitance cut MOSFETs are controlled by selection signals (cid:2038)x0, (cid:2038)x1, (cid:2038)x2, and
`(cid:2038)x3 generated by predecoder PDCR. Id. at 9:68-10:4.
`
`
`
`The petition cites to Fig. 3 of Sato as allegedly meeting claim limitations of
`
`the ’002 patent. See, e.g., Paper 2 at 9-32. Petitioner provides an annotated Fig. 3
`
`showing the alleged disclosure of certain claim limitations:
`
`
`
`17
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`

`

`Id. at 10. Fig. 3 of Sato depicts “a circuit a diagram showing [an] X address decoder
`
`of [a] static RAM.” Ex. 1005 at 2:57-39.
`
`
`
`
`
`The X address decoder of Fig. 3 includes a predecoder PDCR that “decodes
`
`thereto … and generates selection signals (cid:2038)x0~(cid:2038)x3.” Id. at 5:25-28. The “selection
`signals (cid:2038)x0~(cid:2038)x3 are formed selectively in accordance with the complementary
`
`the lower 2-bit complementary internal address signals ax0 and axl supplied
`
`internal address signals ax0 and ax1.” Id. at 5:28-31. Further, “[t]he timing signal
`
`
`
`18
`
`

`

`(cid:2038)ce … is supplied to the pre-decoder PDCR,” and the PDCR’s “output signal, that
`is, the selection signal (cid:2038)x0~(cid:2038)x3, is generated in accordance with this timing signal
`(cid:2038)ce.” Id. at 10:36-39.
`PDCR meets the claimed “first logic,” and that the signals (cid:2038)x0~(cid:2038)x3 disclose the
`signals (cid:2038)x0~(cid:2038)x3 as “timing signals,” much less “clocks” or “clock outputs.” Rather,
`Sato refers to the signals (cid:2038)x0~(cid:2038)x3 exclusively as “selection signals” to reflect the
`
`
`
`As seen in the annotated Fig. 3 above, Petitioner argues that the predecoder
`
`claimed “plurality of clock outputs” of the first logic. But Sato never refers to the
`
`function and purpose of those signals, which is to selectively turn on one of the
`
`capacitance cut MOSFETs. See, e.g., id. at 5:25-28. In contrast, the first logic output
`
`of the ’002 patent claims is a clock signal provided to wordline drivers for
`
`synchronization. Sato also provides no details on the internal circuitry of the
`
`predecoder PDCR that would suggest the signals (cid:2038)x0~(cid:2038)x3 are clock outputs.
`Likewise, Petitioner argues that the signal (cid:2038)ce discloses the claimed “clock signal,”
`but Sato only refers to the signal (cid:2038)ce as a “timing signal” or “selection control signal.”
`
`See, e.g., id. at 3:59-61.
`
`
`
`The X address decoder of Fig. 3 further includes NAND gate circuits NAG0-
`
`NAGk, though the illustration “shows only the NAND gate circuit NAG0.” Id.
`
`at 9:34-35. As seen in Figs. 1 and 3 of Sato, the NAND gate circuits NAG0-NAGk
`
`receive (i) complementary internal address signals ax2-axi, and (ii) the selection
`
`
`
`19
`
`

`

`control signal (cid:2038)ce. The NAND gate circuits NAG0-NAGk use these received
`signals in generating selection signals (cid:1845)0(cid:3364)(cid:3364)(cid:3364)~(cid:1845)(cid:1863)(cid:3364)(cid:3364)(cid:3364). See, e.g., id. at 5:66-6:4 (“(cid:1845)0(cid:3364)(cid:3364)(cid:3364) … is
`set to the low logic level in synchronism with the timing signal (cid:2038)ce when all the
`The timing signal (cid:2038)ce and additional timing signals (cid:2038)we, (cid:2038)sa, and (cid:2038)oe are
`
`inversed internal address signals ax2~axi are at the high logic level”).
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`
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`generated by a timing control circuit TC shown in Fig. 4 of Sato:
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`
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`20
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`

`

`Id. at Fig. 4 (highlighting added). The timing control circuit TC generates the (cid:2038)ce,
`(cid:2038)we, (cid:2038)sa, and (cid:2038)oe timing signals “on the basis of a chip enable signal (cid:1829)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364), a write
`enable signal (cid:1849)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) and an output enable signal (cid:1841)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364) supplied as control signals from
`outside.” Id. at 5:7-12. No clock signal is used in the generation of the (cid:2038)ce, (cid:2038)we,
`(cid:2038)sa, and (cid:2038)oe timing signals. Ex. 2001 at ¶90.
`The (cid:2038)ce, (cid:2038)we, (cid:2038)sa, and (cid:2038)oe signals are internal timing signals that control
`different portions of Sato’s memory system. Id. at ¶¶90-95. The (cid:2038)ce signal, as
`
`
`
`described above, is a “selection control signal” that is provided to both the
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`predecoder PDCR and NAND gate circuits NAG0-NAGk and subsequently
`
`provided to a selected output of these respective circuits. Id. at 3:59-61, 5:43-6:59,
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`10:36-39. The (cid:2038)we signal is a timing signal that controls a write amplifier WA (id.
`at 4:63-5:6), the (cid:2038)sa signal is a timing signal that controls a sense amplifier SA (id.
`at 4:40-46), and the (cid:2038)oe signal is a timing signal that controls a data output buffer
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`DOB (id. at 4:47-57).
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`
`
`In contrast to the ’002 patent, Sato is directed to asynchronous memory
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`systems and does not disclose a synchronous memory system that uses a periodic
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`clock signal. Ex. 2001 at ¶100-04. As explained in Section IV above, asynchronous
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`memory systems include control circuitry for receiving external inputs and
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`generating appropriately timed sequences of internal timing signals for controlling
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`movement of data in the memory. Sato’s timing control circuit TC is an example of
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`21
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`inputs for different components and operations. Id. at ¶102. Thus, in Sato, there is
`
`no single, periodic clock signal to which all memory operations are synchronized,
`
`such “control circuitry”: It receives external input signals (cid:1829)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364), (cid:1849)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) and (cid:1841)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364) and
`generates multiple internal timing signals (cid:2038)ce, (cid:2038)we, (cid:2038)sa, and (cid:2038)oe based on the
`but rather multiple internal timing signals (cid:2038)ce, (cid:2038)we, (cid:2038)sa, and (cid:2038)oe for controlling
`the inputs (cid:1829)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364), (cid:1849)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) and (cid:1841)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364) or outputs (cid:2038)ce, (cid:2038)we, (cid:2038)sa, and (cid:2038)oe of the timing control
`indicates that the signal (cid:2038)ce is not periodic, stating that the signal (cid:2038)ce is “kept at a
`high level” based on a value of the chip enable signal (cid:1829)(cid:1831)(cid:3364)(cid:3364)(cid:3364)(cid:3364). Ex. 1005 at 3:59-65;
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`different components of the memory. Moreover, Sato does not suggest that any of
`
`circuit TC are periodic. Id. at ¶103. Rather, the only relevant disclosure in Sato
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`Ex. 2001 at ¶96.
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`
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`Additionally, the alleged “first logic” and “second logic” of Sato operate in a
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`serial manner that differs from the parallel arrangement described in the ’002 patent.
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`Specifically, in the ’002 patent, the first and second logics operate independently of
`
`each other and apply their respective outputs directly to wordline drivers in parallel,
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`thus reducing a timing delay in providing the clock signal to a particular wordline
`
`driver. See, e.g., Ex. 1001 at Fig. 1. By contrast, in Sato, outputs of the NAND gate
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`circuits (i.e., the alleged “second logic”) are not applied to the wordline drivers until
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`selected by outputs of the predecoder PDCR (i.e., the alleged “first logic”), which
`
`are received by the capacitance cut MOSFETs (e.g., Q19, Q20, etc.). Ex. 1005
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`
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`22
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`at 9:68-10:4. With this slower serial operation, Sato thus fails to achieve the
`
`advantage of reduced timing delay described in the ’002 patent.
`
`B. Overview of Asano
`U.S. Patent Publication No. 2006/0098520 (“Asano”), titled “Apparatus and
`
`
`
`Method of Word Line Decoding for Deep Pipelined Memory,” relates generally to
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`memory arrays, and more particularly to wordline decoding for memory arrays.
`
`Ex. 1006 at ¶[0001]. Asano was filed on November 5, 2004, and published on
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`May 11, 2006.
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`
`
`The purpose of Asano is to reduce the number of latches in a deep pipeline
`
`wordline decoder. Id. at Abstract. Asano explains that conventional systems used a
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`single local clock buffer (LCB) to provide a driving signal to wordline drivers, and
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`that these conventional systems required “a large number of latches.” Id.; see also
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`id. at Fig. 1 (prior-art system with single LCB 108 driving wordline drivers 106).
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`“To reduce this latch usage,” Asano provides a system in which multiple “LCBs are
`
`employed, such that one latch can enable an increased number of [wordlines].” Id.
`
`at Abstract. This reduces the area occupied by the latches and results in less power
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`consumption. Id.
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`
`
`Petitioner cites to Fig. 2 of Asano as allegedly meeting limitations of
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`the ’002 patent. See, e.g., Paper 2 at 33-50. This figure is a block diagram of a
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`memory 200 (Ex. 1006 at ¶[0015]):
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`23
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`
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`Id. at Fig. 2.
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`
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`“To begin the access cycle for the memory 200,” a 6-bit memory address is
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`received at a predecoder 202. Id. at ¶[0016]. In contrast to what is described in
`
`the ’002 patent, the 6-bit memory address is not split into first and second portions
`
`that are sent to respective first and second logics. Rather, in Asano, all six bits are
`
`received by the single predecoder 202. See id. Further, Asano’s two-page
`
`description provides no details on the internal circuitry of the predecoder 202, and
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`there is nothing in the reference suggesting that the predecoder 202 would include
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`distinct first and second logics. Ex. 2001 at ¶¶127-29.
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`
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`Using the received 6-bit memory address, the predecoder 202 generates an 8-
`
`bit X wordline select signal and a 4-bit Y wordline select signal that are provided to
`
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`24
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`a final decoder 204. Ex. 1006 at ¶[0016]. Using the received X wordline select
`
`signal and Y wordline select signal, the final decoder 204 “determines which of …
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`32 wordline drivers 206 are to be enabled.” Id. at ¶[0017]. Each of the 32 wordline
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`drivers 206 drives two wordlines, and each wordline driver includes a latch and two
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`AND gates. Id. at ¶[0019]. “For the sake of illustration, a single latch 210, first
`
`AND gate 212, and a second AND gate 236 are depict