Kiyoo ItthLSI
`Memory
`Chu)
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`
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`F'%.."Brinler
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`
`Apple v. Qualcomm
`|PR2018—01249
`
`Page 1
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`QUALCOMM EXHIBIT 2003
`Apple v. Qualcomm
`IPR2018-01249
`Page 1
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`

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`Springer Series in
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`Spnnger
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`ADVANCED MICROELECTRONICS _5
`
`Physics andAstronomymfl“flung
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`Page 2
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`ADVANCED MICROELECTRONICS
`
`Series editors: K. Itoh, T. Sakurai
`
`The Springer Series in Advanced Microelectronics provides systematic information on
`all the topics relevant for the design, processing, and manufacturing ofmicroelectronic
`devices. The books, each prepared by leading researchers or engineers in their fields,
`cover the basic and advanced aspects of topics such as wafer processing, materials,
`device design, device technologies, circuit design, VLSI implementation, and subsys-
`tem technology. The series forms a bridge between physics and engineering and the
`volumes will appeal to practicing engineers as well as research scientists.
`
`1 Cellular Neural Networks
`Chaos, Complexity and VLSI Processing
`By G. Manganaro, P. Arena, and L. Fortuna
`
`2
`
`3
`
`Technology of Integrated Circuits
`By D. Widmann, H. Mader, and H. Friedrich
`Ferroelectric Memories
`By]. F. Scott
`
`4 Microwave Resonators and Filters for Wireless Communication
`Theory, Design and Application
`By M. Makimoto and S. Yamashita
`
`5 VLSI Memory Chip Design
`By K. Itoh
`
`
`
`
`Series homepage — httpzl’a’wwwspringer.deiphyslbookslssam:rm
`
`
`
`Page 3
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`

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`VLSI
`
`1 Memory Chip Design
`
` Kiyoo Itoh
`
`With 416 Figures and 26 Tables
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`'cj'.‘ ,,I:+-‘ Sprmger
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`Page 4
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`1-280, Higashi-Koigakubo
`Kokubunji-shi
`Tokyotss 8601
`Japan
`e-mail: k itoh@crl.hitachi.co.jp
`
`Series Editors:
`
`Dr. Kiyoo Itoh
`Hitachi Ltd., Central Research Laboratory
`1 280 Higashi-Koigakubo
`Kokubunji- shi
`Tokyo 185-860:
`Japan
`
`Professor Takayasu Sakurai
`Center for Collaborative Research
`University of Tokyo
`7-22-1 Roppongi, Minato-ku,
`Tokyo 106—3558
`Japan
`
`CPO-068735
`
`Library of Congress Cataloging-in—Publication Data
`
`
`ltoh. Kiyoo, 194l-
`
`VLSI memory chip design .- Kiyoo Itoh.
`
`13. cm. -- (Spnnger series in advanced microelectronics ; 5)
`Includes bibliographical references and index.
`
`ISBN 3540678204 (alk. paper)
`
`I. Semiconductor storage devices--Desrgn and construction. 2. Integrated
`
`circuits—Very large scaEe integration-Design and construction. I. Title. II. Series.
`'l'K.7895.M4 183'6 2001
`
`621.39'732 -dc2|
`
` ISSN 1437-0387
`ISBN 3 540-67820-4 Springer Verlag Berlin Heidelberg New York
`
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`This work is subject to copyright. All rights are reserved, whether the whole or part of the material is
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`reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or
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`Page 5
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`l'lie VLSI memory era truly began when the first production of semiconduc-
`Im memory was announced by IBM and Intel in 1970. The announcement
`Imd n. profound impact on my research at Hitachi Ltd., and I was forced
`In elmnge fields: from magnetic thin film to semiconductor memory. This
`« hinge was so exceptionally sudden and difficult, I felt like a victim of fate.
`1.1lelllg back, however, I realize how fortunate I was. I have witnessed an
`unprecedented increase in memory capacity (DRAM, for example, has had
`in (i order increase in the last three decades
`from the 1-Kb level in 1970 to the
`
`
`rest of the book. Chapter 3 focuses on DRAM chip design. After the catalog
`
`I (ll: level today). I have contributed to this progress with full involvement
`Ill memory-chip development over my career. Such rapid progress would have
`been impossible without many of the inventions and innovative technologies,
`n ml without the effort of many talented people. Unfortunately, few systematic
`hooks on memory chip design have been written by experts. This is a result of
`Iwo factors: the difliculty of involving university professors because of rapidly
`rliunging technology requiring huge investments and development resources,
`and a shortage of time on the part of chip designers in industry clue to severe
`m unpetition in the memory—chip business. Therefore, LSI memory-chip design
`Inns been isolated from the outside, preventing a deeper understanding of the
`technology.
`This book is based on my 30-year memory-chip [particularly DRAM)
`design career. In addition to memory circuits and subsystem design issues,
`1 describe boundary issues between processes, devices, and circuits. I also
`ntteinpt to systematically describe concepts that remain unclear, and discuss
`slnte-of-the—art memory—chip design. This book will be beneficial to students
`lllltl engineers interested in memory-chip design, and also to process and
`device engineers involved in memory-chip development.
`Chapter 1 describes the basics of various VLSI memory chips including
`DRAM, SRAM, and nonvolatile memory. Particular emphasis is paid to
`internal organization, operation principles and general trends in chip perfor—
`mance. Chapter 2 deals with the basics of RAM design and technology. The
`elements constituting a memory chip (MOSFETs, capacitors, and resistors),
`MOS memory circuits, the scaling law, and other relevant technologies are
`discussed. The first two chapters lay the groundwork for understanding the
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`cribed. Then, refreshing schemes and redundancy are explained. Chapter 4
`discusses the signal-to—noise (SEN) issue in DRAM which strongly influences
`stable operation in the memory cell and, thus,
`in the chip. The relation—
`ship between memory-cell structure and its drivingfsensing is explained in
`relation to the S_,-"N issue. Chapter 5 describes on—chip voltage generators
`used for power supply conversion. These generators are essential for power-
`supply standardization and stable operation. Chapter 6 discusses subsystem-
`memory architectures. These are increasingly important in providing wide
`bandwidth (i.e. throughput) for modern DRAMS. Chapters 7 and 8 describe
`low-powerflowwoltage memory circuits, emphasizing the importance of the
`partial activaiton of multi—divided arrays. and of lowering power-supply vol-
`tage. Low voltage inevitably needs the subthreshold—current reduction which
`is the key to future LSI design.
`I am indebted to many people including colleagues and the office admi—
`nistration staff members, Ms. Hosoda and Ms. Ohta, at Hitachi Ltd. They
`offered support, advice, and the material needed to finalize my work. Special
`thanks go to my wife, Kyoko. Without her continuing support and patience
`this book would not have been possible.
`
`
`
`Stanford, January 2001
`
`Kiyoo Itch
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`Page 7
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`

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`Contents
`
`An Introduction to Memory Chip Design .................
`1.1
`Introduction ...........................................
`
`1
`1
`
`3
`3
`5
`6
`6
`11
`11
`15
`19
`24
`24
`26
`29
`
`1.2 The Internal Organization of Memory Chips ...............
`1.2.1 The Memory Cell Array ...........................
`1.2.2 The Peripheral Circuit ............................
`1.2.3 The 1,30 Interface Circuit .........................
`1.3 Categories of Memory Chip ..............................
`1.4 General "fiends in DRAM Design and Technology ..........
`1.4.1 The History of Memory-Cell Development ...........
`1.4.2 The Basic Operation of The l-T Cell ...............
`1.4.3 Advances in DRAM Design and Technology .........
`l .5 General Trends in SRAM Design and Technology ...........
`1.5.1 The History of Memory-Cell Development ...........
`1.5.2 The Basic Operation of a SRAM Cell ...............
`1.5.3 Advances in SRAM Design and Technology ..........
`1.6 General Trends in Non Volatile Memory Design
`31
`and Technology ........................................
`31
`1.6.1 The History of Memory—Cell Development ...........
`34
`1.6.2 The Basic Operation of Flash Memory Cells .........
`1.6.3 Advances in Flash-Memory Design and Technology .
`.
`. 46
`
`74
`
`The Basics of RAM Design and Technology .............. 49
`2.1
`Introduction ........................................... 49
`2.2 Devices ............................................... 49
`2.2.1 MOSFETs ......................................
`49
`2.2.2 Capacitors .......................................
`57
`2.2.3 Resistors ........................................
`60
`
`61
`2.2.4 Wiring and Wiring Materials ......................
`65
`2.2.5 Silicon Substrates and CMOS Latch—Up .............
`67
`2.2.6 Other Devices ....................................
`67
`2.3 NMOS Static Circuits ...................................
`2.3.1 The dc Characteristics of an Inverter ............... 68
`2.3.2 The ac Characteristics of an Inverter ................
`70
`2.3.3 The Improved NMOS Static Inverter ................
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`2.5
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`2.4.2 The Bootstrap Driver .............................
`{fit-IDS Circuite ........................................ T9
`2.3.! The de Charmteristim ............................
`2.3.2 The at Uhatactet‘ietim ............................
`2.6 Basie Memory Circuits .................................. 33
`2.6.1 The Inverter and the Bash: Logic Gate ..............
`2.3.2 The Current Mirror ...............................
`2.11.3 The Differential Amplifier .........................
`2.3.4 The ‘i’oitage Booster ..............................
`2.15.3 The have} Shifter ............. . ...................
`2.6.3 The Ring Cecilielor ............................... 33
`3.15.7 The Counter .....................................
`2.7 The Sealing Law .......................................
`2.7.] Constant Eieetrie—Fielii Sealing .....................
`2.7.2 {Torment Operation-L'oitage Seating ................ 92
`2.3.3 Combined Scaling ................................ 92
`2.3 Lithography ........ . .................................. 93
`2.9 Packaging .............................................
`
`3. DEAL! Circuits .......................................... *3?
`3.]
`introduction ........................................... 9?
`3.1.1 High-Density Technology ..........................
`3.1.2 High—Performance Circuits ......................... 100
`3.2 The catalog Specifications of the Standard DRAM .
`_
`.
`.
`.
`3.2.1 Operational Conditions ........................... 102
`3.2.2 Modes oi Operation anti 'l‘iming Specifieatione .
`.
`3.3 The Basic Configuration and Operation of the DRAM Chip. . 1111
`3.3.1 Chip Configuration ............................... 110
`3.3.2 Address Liultipifl'xiflg ............................. 111
`3.41 Fundamental Chip Technologies .......................... i 13
`3.4.1
`A Larger Memory Capacity and Sealed-Dim Devices. 113
`3.4.2 High SIN Ratio {'Iireuite .......................... 113
`3.4.3 Low Power Circuila ............................... I 1?
`3.4.4 High-Speed Cirroita .............................. 123
`3.4.3 The Multidivieion of a Memory Array ............... 123
`3.3 The Multiditriried Data Line and Word Line ............... 131
`3.3.1 The Muftioit—ided Data Line ....................... 132
`3.5.2 The Multidivided Word Line. ....................... 139
`3.11 Read and Relevant Circuits .............................. Irll
`3.11.1 The Address Butler ............................... 141
`3.13.2 The Adt'h‘PE-fl-i Decoder ............................. 144i
`3.3.3 The Word Driver ................................. 14?
`3.5.41 The Sewing {iitt‘uit .............................. 15?
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` Contents
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`IX
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`3.6.5 The Common LEO-Line Relevant Circuit ............ 167
`3.6.6 The Data-Output Buffer .......................... 172
`.I. F Wl'llt' and Relevant Circuits ............................. 174
`.l H Refresh Relevant Circuits ................................ 175
`3 8.] Refresh Schemes ................................. 175
`3.8.2 The Extension of Data-Retention Time
`
`
`
`
`
`
`
`
`in Active Mode .................................. 176
`
`3.8.3 Current Reduction Circuits in Data-Retention Mode .
`. 176
`
`3 'l Redundancy Techniques ................................. 178
`
`
`3.9.1
`Issues for Large-Memory-Capacity Chips ............ 184
`3.9.2
`Intra-Subarray Replacement Redundancy ............ 185
`
`3.9.3
`Inter-Subarray Replacement Redundancy ............ 189
`
`3.9.4 The Repair of dc Characteristics Faults ............. 191
`
`:1. ll) On—Chip Testing Circuits ................................ 192
`
`
`High Signal-to—Noise Ratio
`DRAM Design and Technology ........................... 195
`I
`I
`Introduction ........................................... 195
`1.2 Trends in High SEN Ratio Design ......................... 195
`4.2.1 The Signal Charge ................................ 197
`4.2.2 Leakage Charge .................................. 204
`4.2.3 The Soft—Error Critical Charge ..................... 208
`4.2.4 The Data-Line Noise Charge ....................... 210
`1.3 Data—Line Noise Reduction .............................. 210
`4.3.1 Noise Sources and Their Reduction ................. 210
`4.3.2 Word—Line Drive Noise ............................ 213
`4.3.3 Data-Line and Sense-Amplifier Imbalances ........... 217
`4.3.4 Word-Line to Data—Line Coupling Noise ............. 230
`4.3.5 Data-Line Interference Noise ....................... 237
`4.3.6 Power-Supply Voltage Bounce ...................... 240
`4.3.7 Variation in the Reference Voltage .................. 241
`4.3.8 Other Noises ..................................... 244
`4.4 Summary .............................................. 247
`
`5. On-Chip Voltage Generators .............................. 249
`5.1
`Introduction ........................................... 249
`5.2 The Substrate-Bias Voltage (VBB) Generator ............... 251
`5.2.1 The Roles of the V33 generator .................... 251
`5.2.2 Basic Operation and Design Issues .................. 256
`5.2.3 Power-On Characteristics .......................... 258
`5.2.4 Characteristics in the High-VD.) Region ............. 264
`5.2.5 The VBB Bump .................................. 266
`5.2.6 Substrate-Current Generation ...................... 269
`5.2.7 Triple-Well Structures ............................ 272
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`Page 10
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`5.3.2 Design Approaches and Issues ...................... 278
`5.3.3 High Boost-Ratio Converters ...................... 283
`5.3.4 Low-Power, High Supply Current Converters ......... 285
`The Voltage Down-Converter ............................ 290
`5.4.1 The Roles of the Voltage Down-Converter ........... 290
`5.4.2 The Negative-Feedback Converter and Design Issues .
`5.4.3 Optimum Design ................................. 297
`5.4.4 Phase Compensation .............................. 301
`5.4.5 Reference-Voltage Generators ...................... 316
`5.4.6 Burn-In Test Circuits ............................. 323
`
`5.4.7 Voltage Trimming ................................ 327
`5.4.8 Low-Power Circuits ............................... 329
`5.5 The Half-V1313 Generator ................................ 332
`
`5.6 Examples of Advanced On-Chip Voltage Generators ........ 333
`
`7.2.3 The Low-Voltage Data-Bus Interface ................ 396
`
`High-Performance Subsystem Memories .................. 339
`6.1
`Introduction ........................................... 339
`6.2 Hierarchical Memory Systems ............................ 341
`6.2.1 Memory Hierarchy ................................ 341
`6.2.2
`Improvements in Memory—Subsystem Performance .
`6.2.3 Memory-Chip Performance ........................ 349
`Memory-Subsystem Technologies ......................... 354
`6.3.1 Wide-Bit II'O Chip Configurations .................. 354
`6.3.2 Parallel Operation of Multidivided Arrays ........... 354
`6.3.3 Multibank Interleaving ............................ 357
`6.3.4 Synchronous Operation ........................... 358
`6.3.5 Pipelinefr'Prefetch Operations ...................... 362
`6.3.6 High-Speed Clocking Schemes ...................... 363
`6.3.7 Terminated Ilr'O Interfaces ......................... 363
`6.3.8 High-Density Packaging ........................... 364
`High-Performance Standard DRAMs ...................... 365
`6.4.1 Trends in Chip Development ....................... 365
`6.4.2 Synchronous DRAM .............................. 368
`6.4.3 Rambus DRAM .................................. 380
`6.5 Embedded Memories .................................... 383
`
`Low-Power Memory Circuits ............................. 389
`7.1
`Introduction ........................................... 389
`
`7.2 Sources and Reduction of Power Dissipation
`in a RAM Subsystem ................................... 392
`7.2.1 Wide-Bit III'O Chip Configuration .................. 393
`7.2.2 Small Package ................................... 394
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`Page 11
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` Contents
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`XI
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`7 :1 Sources of Power Dissipation in the RAM Chip ............. 402
`7.3.l Active Power Sources ............................. 402
`7.3.2 Data-Retention Power Sources ..................... 405
`7 | Low-Power DRAM Circuits .............................. 406
`7.4.! Active Power Reduction ........................... 406
`7.1.2 Data-Retention Power Reduction ................... 412
`7 f: Low-Power SRAM Circuits .............................. 413
`7.5.1 Active Power Reduction ........................... 413
`7.5.2 Data-Retention Power Reduction ................... 423
`
`U ltra-Low—Voltage Memory Circuits ...................... 425
`H.|
`Introduction ........................................... 425
`34.2 Design Issues for Ultra-Low—Voltage RAM Circuits ......... 426
`8.2.1 Reduction of the Subthreshold Current .............. 426
`8.2.2 Stable Memory-Cell Operation ..................... 432
`8.2.3 Suppression of, or Compensation for,
`Design Parameter Variations ....................... 433
`8.2.4 Power-Supply Standardization ..................... 435
`8.3 Ultra-Low-Voltage DRAM Circuits ....................... 437
`8.3.1 Gate Boosting Circuit ............................. 439
`8.3.2 The Muiti-VT Circuit ............................. 440
`8.3.3 The Gate-Source Back-Biasing Circuit .............. 442
`8.3.4 The Well Control Circuit .......................... 456
`8.3.5 The Source Control Circuit ........................ 461
`8.3.6 The Well and Source Control Circuit ............... 462
`8.4 Ultra—Low—Voltage SRAM Circuits ........................ 463
`8.5 Ultra-Low-Voltage SOI Circuits .......................... 466
`
`References .................................................... 473
`
`Index ......................................................... 489
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`6.3 Memory-Subsystem Technologies
`
`It is obvious that wide-bit 1,50 chip configurations combined with parallel 0| n
`ration of multidivided arrays increases the throughput. Moreover, to lIIIIJIUH
`the traditional DRAM performance discussed in Chap. 3 modern DRAM
`incorporate memory-subsystem technologies such as multibank interlcm im-
`synchronous operation with a latch function, pipelineg’prefetch operaiium:
`high-speed clocking schemes, and terminated interfaces combined with Ingli
`density packaging. These technologies are supported by command operatmim.
`on-chip mode registers, and packet protocols.
`
`130 line without imposing any restriction on YL activation timing. Mom In I.
`the non-destructive read—out characteristics of SRAM cell allow write clutn In
`be inputted to the selected data line at the earliest timing, eliminating Ilu
`rewrite operation that is necessary for DRAM. Even so, the resultant high
`voltage swing on the selected data line does not destroy small read voltage . on
`the adjacent data lines, despite capacitive coupling, since the small voitngun
`are static ones and thus are immune to various noises, unlike the floating mum
`of the DRAM. Thus, the necessary word pulse can be shortened, enabling funl
`row access and cycle times. If the sum of the data-replacing time involvml in
`a write operation and the equalizing time on the data lines is equal to lin-
`sum of the column delay (TC) and the equalizing time on the I_.-’0 lines, mi
`in usual SRAM designs, the row access time is equal to the row cycle Lilli“
`The column speeds are faster than the row speed, as in the DRAM. If nmlfi
`stage pipelining is used, even the cycle time faster than the access iimr: i~.
`achievable [6.11].
`
`|
`
`6.3.1 Wide—Bit I/O Chip Configurations
`
`These configurations [6.4, 6.17: offer high throughput as well as ease of II .1
`which is realized by reducing the chip count needed by the system and In
`adding flexible add-on memory capability. Despite the possibility of at Inn-4
`256 b organization, compared to the 32 b organization for current experinu-II
`tal 1 Gb chips [6.4, 6.17l, the number of 1,30 pins is eventually restricted In
`the following drawbacks: the chip power increases rapidly with an increasi- In
`the pin count, because the number of simultaneously charged and discharged
`DLs (Le. m in the logical array) increases. The chip area also increases rim
`to an increase in the HO relevant circuits. The details are given in Chap 7
`
`6.3.2 Parallel Operation of Multidivided Arrays
`
`The concept of the multidivided array [6.4, 6.17], a combination of multiclm
`ded data lines (DLSJ and multidivided word lines (WLs), shown in Fig. ii
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` 6.3 Memory-Subsystem Technologies
`
`355
`
`any
`
`(b)
`
`Fig. 6.11. The concept of a multidivided RAM array [6.14.6.17]: the shading
`=lc-notes the activated area. M — n’m’ — nm. (a) A non—divided array; (b) a mul-
`Iulivided array; (0) a logical array
`
`Internal IfO line. In an actual design, in addition to the shared Y decoders
`
`:3 the key to designing a high-performance RAM. The division of a DL and its
`partial activation dramatically increases the inherently small signal voltage
`and reduces the DL power dissipation that dominates the total chip power.
`l‘he division of a WL is also essential to improve the ever-increasing WL delay
`with increasing memory capacity. A multidivided array realizes the high per-
`formance of a resulting subarray, if low-resistivity multilevel metal wiring and
`high—speed subarray-selection circuits are adopted. Multilevel metal wiring
`nlso minimizes the additional increases in area at the divisions. Any com-
`bination of a number of subarrays could be simultaneously activated, since
`ouch subarray could be randomly accessed. The parallel operation capability
`of subarrays enables multibank interleaving, if each bank in a memory system
`is asserted by each subarray. However, for DRAMs the number of simulta-
`m-ously activated subarrays is restricted by the DL power dissipation and the
`maximum refresh time (the data-retention time of the cell), tREFmax, which
`is specified in the catalog for the chip. The activation for the complicated
`physical array is simplified by using the logical array comprising an virtual
`Wm‘d lines shown in Fig. 6.11c. Here, n is the number of refresh cycles in the
`catalog specification, which are usually distributed within tREqu; and m
`is the number of simultaneously activated DLs, taking his to MIns, where
`M, as, and m5 are the memory capacity of the chip, the number of sub-
`WLs, and the number of sub-DLs in a subarray, respectively. Here, as is less
`than 1k in the megabit era, which is determined by the minimum signal
`voltage for a successful sensing, while ms is 256 or 512 in terms of the WL
`:lvlay. Figure 6.12s. shows a more detailed multidivided array, widely used in
`multimegabit DRAM products, featuring the DL orthogonally aligned to the
`
`Page 14
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`Local X-Dec.
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`Ito (metal) Main WL (metal)
`
`[inE
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`available number of data, with at least one unit of data from each subarray.
`
`shown in the figure, a combination of a shared sense amplifier (SA) and
`a shared 150 is used to further reduce the DL charging capacitance, as well
`as the chip area. The details are discussed in Chap. 3.
`The DRAM array is a built-in structure capable of a massively parallel
`operation at the expense of large DL power. This stems from the refresh
`operation requirement of the 1 T cell, that needs simultaneous activation ol‘
`all the cells along the selected WL. A multidivided array further increases the
`
`(b)
`
`N Main Amp.
`
`Fig. 6.12. An actual multidivided DRAM array [6.4, 6.17]: the paired-line arran
`gement is actually applied for each DL and each ifo line. (a) DL orthogonal to i_ u
`line; :b) DL parallel to ifo line
`
`Page 15
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` 6.3 Memory-Subsystem Technologies
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`
`
`357
`If the 1/0 line is arranged in parallel to the corresponding DL, as shown in
`Fig. 6.12b, the available number is maximized by one unit of data from each
`I)L. Thus, the DRAM array inherently favors embedded DRAM designs, in
`which high throughput is the first priority, although increases in the DL
`and I/O power become serious concerns. To achieve high throughput of
`multidivided arrays while reducing the area, a large logic—gate block in an
`
`li.3.3 Multibank Interleaving
`
`
`
` memory RAS. CAS. WE
`bus
`cu<+i mcnr
`
`Ai
`.p,‘
`(Nae. Inc)
`
`0. av
`
`
`
`
`. mam memory
`.5— system
`
`
`
`system width Nae
`
`
`H+____H,w___....
`
`..
`
`Multibank interleaving has been widely used to increase the throughput with
`a substantially parallel operation of the multibank. In this scheme, a memory
`system consists of N banks, which are sequentially addressed from bank 1 to
`hunk N, as shown in Fig. 6.13. Each bank is composed of a memory module
`using many DRAM chips, so that the memory bus has an NMB-bit data-
`lms (i.e. Iij width. When N words, each of which comprises NMB bits, are
`
`embedded DRAM chip will require additional layers of metal wiring.
`
`_l—Ll—L. l"? lmn
`i‘
`
`an“ mg 43:!
`
`1..
`
`fis‘ |
`
`|l-"
`
`Do . _....
`
`
`
`_... W.I_,T_..
`l
`nullputolMUX “m ........... m
`
`Fig. 6.13. Conventional multibank interleaving :6.8|. MUX, multiplexer; MCRL,
`memory controller
`
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`

`bit data are available every system-clock cycle tsc on the system bus. Since
`it continues for the memory cycle time {tMc) of bank, the throughput is
`increased from NMBf'tMC to NMBN,e'tMC, with an N-fold increase. However .
`this approach causes an increase in the minimum add on memory capacity.
`which is expressed as MNMBNEj , where M and j are the memory capacity
`of the chip and the IIO pin count of chip, respectively. Moreover, it enables
`an increase in the number of bus lines and relevant devices with NMBN.
`preventing flexible design, miniaturization, and a low cost for the whole sy-a
`tern. Increasing j is beneficial to increasing the throughput for a fixed add on
`memory capacity, or to reducing the minimum add—on memory capacity ion
`a fixed throughput. However, an excessively large 3' causes increased powvl
`dissipation, chip area, and package size, as discussed in Chap. 7. It would
`also degrade the chip speed, with increased noise at the IIO pins.
`The multibank interleaving that memory-system designers have taken i'm
`granted can be implemented on one chip, if the multidivided array structm:
`is utilized. This is because the subarray shown in Fig. 6.11 can be regardm
`as a bank, if each subarray equips its own peripheral circuit and each addro
`buffer of the bank, and thus it can latch the input address signal so tln
`different banks can be successively selected at the minimum system clml
`cycle. When a certain bank is selected, the corresponding address signal
`are latched at the address buffers of the bank, so that address input 1th
`are ready for the next addressng for a different bank. While the memo:
`operation of the succeeding circuits in the bank proceeds with the latclu-«I
`address signals, the diHerent bank is selected with the different addressv
`Thus, the MPU can successively access different banks without having 1::
`wait by the memory cycle of the bank. Moreover, while a bank is accessr-u
`other banks could perform precharge or refresh operations, enabling tin-s
`inherent DRAM operations to be hidden.
`
`as the page mode, nibble mode, static column mode, and extended-data-onl
`
`6.3.4 Synchronous Operation
`
`In this scheme, all of the inpui,-"output signals of chip are latched at tin
`1,30 interface circuits of the chip, synchronously with the system clock. 'l'hi
`scheme not only allows chip designers to incorporate various high-speed fun
`ctions, but it also allows system designers to improve the system speed, wit I:
`an easier timing on the board.
`asynchronous— 21ml
`Figures 6.14 and 6.15 show the concepts behind
`synchronous operation :63], assuming a non-divided data line. Synchronml
`operation has been used for modern DRAMs, such as the synchronous DRA M
`
`[SDRAM}, The double-data—rate {DDR} DRAM, and the Rambus DRAM
`while asynchronous operation has been used for traditional DRAMs, Hill I:
`
`Page 17
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`6.3 Memory-Subsystem Technologies
`
`periphery
`
`memory array
`
`
`359
`
`
`WUDU 0L2 DLa DL4
`'i-
`I'-
`'i-
`'-
`
`
`
`
`
`
`
`
`.., vIvIvIvIv
`
`
`
`Fig. 6.14. The asynchronous operation of a DRAM chip [6.8]. AB, address buffers;
`0B, data-output buffer; X, row; Y, column
`
`(EDO) DRAMs. In synchronous operation, a row address strobe signal RSI
`is generated from the chip-select signal a at the rising edge of the system
`clock CLK, so that row addresses are strobed and the corresponding word
`line (for example, WLl) is activated. The resulting cell signals on m data
`lines are amplified in the usual manner. On the other hand, a column ad
`dress strobe signal 031 is generated by the next CLK, so that the column
`addresses are strobed and the amplified signal on the corresponding data
`line (for example, DL1) is outputted on the common 13"0 bus line. Then, the
`clata output Do is available from the chip synchronously with the succeeding
`CLK. The synchronous operation widens the timing margins between the
`internal control signals. Easier timing designs due to the use of simple latch
`circuits that work synchronously with the system clock are responsible to the
`wider margins On the other hand, in asynchronous operation the internal
`timing designs are complicated, because they are closely related to many so—
`phisticated set-up/hold timing specifications between external inputfoutput
`signals. Moreover, the latch function achieves high throughput with the re-
`sultant pipeline operation (discussed later) and multibank interleaving. The
`
`
`
`Page 18
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`

`row address set up time Lisa, the row—address hold time from, the column
`
`synchronous operation can eliminate the m and m functions that no
`familiar in asynchronous operation, since the same functions are carried will
`by the internal signals R31 and 031. The operation also eliminates lnnu
`hold-signals such as E in Fig. 6.15 if the command instruction schemv u
`adopted. Various operation modes are set by the combination of command
`signals whose pulse widths are almost equal to that of the system clock! in:
`seen in SDRAMs (see Fig. 6.32).
`The synchronous operation of DRAM chips also increases the systt-m
`speed. The asynchronous operation in Fig. 6.16, in which many control signnh
`are generated at a timing generator (similar to control circuits in Fig. 6.13) hv
`using the system clock, makes it complicated to synchronize address signal:
`with the control signals andfor the system clock. For example, although
`various signal skews exist as a result of running on the memory board of 1 III
`bank, the minimum timing specifications of the DRAM chip regarding 1h:
`
`Fig. 6.15. The synchronous operation of a DRAM chip :6.8:. LT, latch; 'I'." H
`control circuit; OB, data-output bufler
`
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`6.3 Memory-Subsystem Technologies
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`361
`
`bank
`
`I DRAM .000
`chip
`
`' s
`
`address switching must take place at the falling edge II. In addition. even
`if the chip can output the data at timing ({3}, the bank actually outputs it
`at timing (it. Such redundancies in timing fail to fully bring out the high
`speed of the chip. On the contrary, the synchronous operation shown in
`Fig. 617 allows the memory