‘
`
`eeeee
`
`Kiyooltoh
`
`easke(oa
`
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`BS)
`Memory—
`Chip
`—
`Design
`
`BS socinae
`D4
`pring
`
`OI WIN,
`
`>
`
`Apple v. Qualcomm
`IPR2018-01249
`
`QUALCOMM EXHIBIT 2003
`Apple v. Qualcomm
`IPR2018-01249
`Page 1
`
`

`

`SpringerSeries in
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`ADVANCED MICROELECTRONICS
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`Series editors: K. Itoh, T. Sakurai
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`The Springer Series in Advanced Microelectronics provides systematic information on
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`2
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`1 Cellular Neural Networks
`Chaos, Complexity and VLSI Processing
`By G. Manganaro,P. Arena, and L. Fortuna
`Technology ofIntegrated Circuits
`By D. Widmann,H. Mader,and H.Friedrich
`Ferroelectric Memories
`ByJ. F. Scott
`4 Microwave Resonators and Filters for Wireless Communication
`Theory, Design and Application
`By M. MakimotoandS. Yamashita
`5 VLSI Memory Chip Design
`By K.Itoh
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`VLSI
`MemoryChip Design
`With 416Figuresand26Tables
`
` KiyooItoh
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`“Q)) Springer
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`1-280, Higashi-Koigakubo
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`e-mail: k-itoh@crl.hitachi.co.jp
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`Series Editors:
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`Dr. Kiyoo Itoh
`Hitachi Ltd., Central Research Laboratory
`1-280 Higashi-Koigakubo
`Kokubunji-shi
`Tokyo 185-8601
`Japan
`
`Professor Takayasu Sakurai
`Center for Collaborative Research
`University ofTokyo
`7-22-1 Roppongi, Minato-ku,
`Tokyo 106-8558
`Japan
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`Library of Congress Cataloging-in-Publication Data
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`Itoh, Kiyoo, 1941-
`VLSI memory chip design / Kiyoo Itoh.
`p. cm, -- (Springer series in advanced microelectronics ; 5)
`Includes bibliographical references and index.
`ISBN 3540678204 (alk. paper)
`I, Semiconductor storage devices--Design and construction,2. Integrated
`circuits--Very large scale integration--Design and construction. I. Title. II. Series.
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`ISSN 1437-0387
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`

` Preface
`
`
`Che VLSI memory era truly began when thefirst production of semiconduc-
`imemory was announced by IBM and Intel in 1970. The announcement
`hie! a profound impact on my research at Hitachi Ltd., and I was forced
`to change fields: from magnetic thin film to semiconductor memory. This
`change was so exceptionally sudden and difficult, I felt like a victim of fate.
`looking back, however, I realize how fortunate I was. I have witnessed an
`unprecedented increase in memory capacity (DRAM, for example, has had
`n G-orderincrease in the last three decades—from the 1-Kb level in 1970 to the
`I-Gh level today}. I have contributed to this progress with full involvement
`in mermory-chip development over my career. Such rapid progress would have
`lean impossible without many of the inventions and innovative technologies,
`and without the effort of many talented people. Unfortunately, few systematic
`hooks on memory-chip design have been written by experts. This is a result of
`iwo factors: the difficulty of involving university professors because of rapidly
`chatging technology requiring huge investments and development resources,
`aul a shortage of time on the part of chip designers in industry due to severe
`conipetition in the memory-chip business. Therefore, LSI memory-chip design
`has been isolated from the outside, preventing a deeper understanding of the
`technology.
`This book is based on my 30-year memory-chip (particularly DRAM)
`ilesign career. In addition to memory circuits and subsystem design issues,
`| describe boundary issues between processes, devices, and circuits. I also
`atlompt to systematically describe concepts that remain unclear, and discuss
`state-of-the-art memory-chip design. This book will be beneficial to students
`iil engineers interested in memory-chip design, and also to process and
`device engineers involved in memory-chip development.
`Chapter 1 describes the basics of various VLSI memory chips including
`DRAM, SRAM, and nonvolatile memory. Particular emphasis is paid to
`internal organization, operation principles and general trends in chip perfor-
`mance. Chapter 2 deals with the basics of RAM design and technology. The
`elements constituting a memory chip (MOSFETs, capacitors, and resistors),
`MOS memory circuits, the scaling law, and other relevant technologies are
`discussed. The first two chapters lay the groundwork for understanding the
`rest of the book. Chapter 3 focuses on DRAM chip design. After the catalog
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`cribed. Then, refreshing schemes and redundancy are explained. Chapter 4
`discusses the signal-to-noise (S/N) issue in DRAM which strongly influences
`stable operation in the memory cell and, thus,
`in the chip. The relation-
`ship between memory-cell structure and its driving/'sensing is explained in
`relation to the S/N issue. Chapter 5 describes on-chip voltage generators
`used for power-supply conversion. These generators are essential for power-
`supply standardization and stable operation. Chapter 6 discusses subsystem-
`memory architectures. These are increasingly important in providing wide
`bandwidth(i.e. throughput) for modern DRAMS. Chapters 7 and 8 describe
`low-powerlow-voltage memorycircuits, emphasizing the importance of the
`partial activaiton of multi-divided arrays, and of lowering power-supply vol-
`tage. Low voltage inevitably needs the subthreshold-current reduction which
`is the key to future LSI design.
`I am indebted to many people including colleagues and the office admi-
`nistration staff members, Ms. Hosoda and Ms. Ohta, at Hitachi Ltd. They
`offered support, advice, and the material needed to finalize my work. Special
`thanks go to my wife, Kyoko. Without her continuing support and patience
`this book would not have been possible.
`
`
`
`Stanford, January 2001
`
`Kiyoo Itoh
`
`Page 7
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`

`

`Contents
`
`An Introduction to Memory Chip Design.................
`L.L
`Introduction 2.0.0.0... 2. c cece eee eee e cena
`1.2 The Internal Organization of Memory Chips ...............
`1.2.1. The Memory Cell Array....2..........000eeeceeue,
`1.2.2 The Peripheral Circuit ...............0 0000 eee eeeee
`1.2.3 The I/O Interface Circuit
`..............0000000000-
`1.3 Categories of Memory Chip..........0...00...cceceee ev eee
`1.4 General Trends in DRAM Design and Technology ..........
`1.4.1 The History of Memory-Cell Development ...........
`1.4.2 The Basic Operation of The 1-T Cell ...............
`1.4.3 Advances in DRAM Design and Technology .........
`1.5 General Trends in SRAM Design and Technology...........
`1.5.1 The History of Memory-Cell Development ...........
`1.5.2 The Basic Operation of a SRAM Cell ...............
`1.5.3 Advances in SRAM Design and Technology ..........
`1.6 General Trends in Non-Volatile Memory Design
`31
`and Technology 2.2.0.0... 0c:
`cece eee ence eee anes
`31
`1.6.1 The History of Memory-Cell Development ...........
`34
`1.6.2 The Basic Operation of Flash Memory Cells .........
`1.6.3 Advances in Flash-Memory Design and Technology ... 46
`
`74
`
`1
`1
`3
`3
`5
`6
`6
`11
`11
`15
`19
`24
`24
`26
`29
`
`The Basics of RAM Design and Technology .............. 49
`
`2.1 Introduction 2.0.0.0... 000.0ccece cece ee eee cece eee e eens 49
`2.2 Devices... 2. cc ccc cee ener etaenenees
`49
`2.2.1 MOSFETs 1.0.0.0... ccc eee eee cece eee ees
`49
`2.2.2 Capacitors... 0.0.0... cece cc cee eee erence eeenenas
`57
`2.2.3 Resistors ..... 0... ccc eect eee cance ees
`60
`2.2.4 Wiring and Wiring Materials ....................-.
`61
`2.2.5 Silicon Substrates and CMOS Latch-Up.............
`65
`2.2.6 Other Devices... 0.2.00... c cece ccc cence es
`67
`2.33 NMOS Static Circuits..........0.00.00 0000 cee cece eee eee es
`67
`2.3.1 The de Characteristics of an Inverter ............... 68
`2.3.2 The ac Characteristics of an Inverter.............00.
`70
`2.3.3 The Improved NMOSStatic Inverter................
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`Page 8
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`2.4.2 The Bootstrap Driver ..........0..0.00.000c cee eeess
`2.5 CMOS Circuits ......00000 000.000 c ccc cece cece eccucees
`a0-l
`“The de Characteristics... .cecsscancpeaceraxky nad 80)
`20.2 The ac -Charactéristits ec. jsiwn/enivriwecinea elie.
`25: Basic Memory Clecuits 2c: ence aig: ge cdsee eae eee Bo
`2.6.1 The Inverter and the Basic Logic Gate ..............
`26.2 The Current Mirror. ...........0000e0ccc cece ceceees
`2.6.3 The Differential Amplifier ...................00000.
`2.6.4 The Voltage Booster ......0.0..0000 cc ccc caceecueees
`2.6.5 The Level Shifter............. fle gyece, eozengs mumeeom, arash: ae BS
`2.6.6 The Ring Oscillator. 2... ..00000. 0. ccc cca ceeeeeuucs
`2.6.7 The Counter. ......0 000. c ccc e cece eee e eee ceeeees
`2.7 The Sealing Law 2.0.0... eee cece eceeuueeeuuuues
`2.7.1 Constant Electric-Field Scaling................-....
`2.7.2 Constant Operation-Voltage Scaling ................ 92
`2.7.3 Combined Pea bd SN CLARE RI ele Stee 92
`Sk:
`TACORTEDNY occ nin pre
`cag eeere ieee eg iw MEATS dateg hee 93
`2 Peelcesta pie ested a ase og SOE ECan 94
`
`3.3
`
`3.4
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`3. DRAMCircuits 2.0.0.0. 00 c eee wee ee cecuueee
`SoD! Cabri pepcapeeee eevee nce ay acaeaeetinn V8 we EN We Oe EN o7
`3.1.1 High-Density Technology ...............02..0.0000-
`3.1.2 High-Performance Circuits............0.c00eceeeees 100
`3.2 The catalog Specifications of the Standard DRAM.......... 102
`3.2.1 Operational Conditions ...........00cccccceuseesae 102
`3.2.2 Modes of Operation and Timing Specifications ....... 105
`The Basic Configuration and Operation of the DRAM Chip.. 110
`3.3.1 Chip Configuration .......0..000000. cc ccc caceeueeces 110
`3.3.2 Address Multiplexing .... 2.0.0.0... 0ccccueveueees lll
`Fundamental Chip Technologies .........0..000000ccccueees 113
`3.4.1
`A Larger Memory Capacity and Scaled-Down Devices. 113
`3.4.2 High S/N Ratio Circuits ............0.0.0.c0cceeeee 116
`3.4.3 Low Power Circuits ......000.0 00.0002 cc cece eeceee 117
`Rel; PghSBA CunoSEB oon a
`yyce cages eaten on een VATE 123
`3.4.5 The Multidivision of a Memory Array............... 128
`The Multidivided Data Line and Word Line ............... 131
`3.5.1 The Multidivided Data Line ...............-.02225, 132
`3.5.2 The Multidivided Word Line.................0.200- 139
`Read and Relevant Circuits .......5.. 6000) eo 0c cs edeeacns 141
`$0.1. The Addresa: Buller 2. stein ie Pen es BS pas 141
`
`3.6.2 The Address Decoder .... 2.2.0.0... 00 ccccccecceues 144
`
`69; The. Word: Driver 2 (ice eee ee 00 id ot oe mcne oon 147
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`3.6
`
`3.6.4 The Sensing Circuit ...........0 000.002 ccc cece cece 157
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`Page 9
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`

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` Contents
`
`5. On-Chip Voltage Generators.................0 0000000 ece ee 249
`5.1
`Introduction ........ 20... c cece cece eee ee ceceeuucceeee 249
`5.2 The Substrate-Bias Voltage (Vgp) Generator............... 251
`5.2.1 The Roles of the Vag generator ............--..20.. 251
`5.2.2 Basic Operation and Design Issues.................. 256
`5.2.3 Power-On Characteristics..........00000 00.0. ceeeeee 258
`5.2.4 Characteristics in the High-Vpp Region ............. 264
`5.2.9 The Veg Bump ................. 0. cece eae e wees 266
`5.2.6 Substrate-Current Generation....................4. 269
`5.2.7 Triple-Well Structures .........00...cccccaeeeeseee 272
`
`
`IX
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`4.6.5 The Common I/'O-Line Relevant Circuit ............ 167
`4.6.6 The Data-Output Buffer ............0.0.000.0-00005 172
`
`
`i Write and Relevant Cirenits ..200....0..000 00 c ccc eaeeecee 174
`
`4M Refresh-Relevant Circuits. ....0.0.0.000. 000.0: cc ecceccevveees 175
`4.8.1 Refresh Schemes ............00.0 0000 cc eee eeeeeuee 175
`
`4.8.2 The Extension of Data-Retention Time
`
`
`in Active Mode ............00 00. ccc eee e eae ees 176
`
`4.8.3 Current Reduction Circuits in Data~Retention Mode .. 176
`
`4{) Redundancy Techniques ..........00.. 0.000 cece eee ee eees 178
`
`4.9.1
`Issues for Large-Memory-Capacity Chips ............ 184
`3.9.2
`Intra-Subarray Replacement Redundancy............ 185
`
`4.9.3
`Inter-Subarray Replacement Redundancy............ 189
`
`4.9.4 The Repair of de-Characteristics Faults ............. 191
`4.10 On-Chip Testing Circuits ........0.0. 00.00 .c cece ee eeeens 192
`
`
`High Signal-to-Noise Ratio
`DRAM Design and Technology ....................0000225 195
`ld
`Introduction ............00 0000 c ccc ete e ec ceeeuveeus 195
`1.2 Trends in High S/N Ratio Design...................0000.. 195
`4.2.1 The Signal Charge........0.. 00... cc cee eee ee ee 197
`4.2.2 Leakage Charge ..........0 0... c cc cee eee eceenaees 204
`4.2.3 The Soft-Error Critical Charge..................... 208
`4.2.4 The Data-Line Noise Charge................-.0005. 210
`1.3 Data-Line Noise Reduction ........0000...cccceeeeueuccee 210
`4.3.1 Noise Sources and Their Reduction ................. 210
`4.3.2 Word-Line Drive Noise ........000.0.0 000.0 cece cee 213
`4.3.3 Data-Line and Sense-Amplifier Imbalances........... 217
`4.3.4 Word-Line to Data-Line Coupling Noise............. 230
`4.3.5 Data-Line Interference Noise.................2..0-. 237
`4.3.6 Power-Supply Voltage Bounce............---.00000- 240
`4.3.7 Variation in the Reference Voltage................., 241
`4.3.8 Other Noises........0000 00000. c cece cece eaeenaes 244
`4.4 Summary. ... 0.0... ccc ec ccc cece eee eee eennecneees 247
`
`
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`Page 10
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`7.2.3 The Low-Voltage Data-Bus Interface................ 396
`
`High-Performance Subsystem Memories .................. 339
`6.1
`Introduction ...... 0... cece cece e neces 339
`6.2 Hierarchical Memory Systems ...............0.2.-.-20000> 341
`6.2.1 Memory Hierarchy................000 0000 cceeeaaee 341
`6.2.2
`Improvements in Memory-Subsystem Performance .... 344
`6.2.3 Memory-Chip Performance ..............000000000. 349
`Memory-Subsystem Technologies .................0000000e 354
`6.3.1 Wide-Bit I/O Chip Configurations.................. 354
`6.3.2 Parallel Operation of Multidivided Arrays ........... 354
`6.3.3 Multibank Interleaving................0...20-. 0000s 357
`6.3.4 Synchronous Operation ..................00 0c. e eee 358
`6.3.5 Pipeline/Prefetch Operations ....................4. 362
`6.3.6 High-Speed Clocking Schemes...................0.. 363
`6.3.7 Terminated I/O Interfaces ...........22-. 0.000 ce ees 363
`6.3.8 High-Density Packaging ........................02. 364
`High-Performance Standard DRAMS.................0000. 365
`6.4.1 Trends in Chip Development.................2..... 365
`6.4.2 Synchronous DRAM ............. 0c ccc cee cece ees 368
`6.4.3 Rambus DRAM ................0 cece c eee cence ees 380
`6.5 Embedded Memories.............. 0.000 cece cece eee eee eae 383
`
`5.3.2 Design Approaches and Issues...................00- 278
`5.3.3 High Boost-Ratio Converters ............00cce0eee, 283
`5.3.4 Low-Power, High Supply Current Converters......... 285
`The Voltage Down-Converter ...........0cccceeecueeeeees 290
`5.4.1 The Roles of the Voltage Down-Converter ........... 290
`5.4.2 The Negative-Feedback Converter and Design Issues .. 293
`5.4.3 Optimum Design ........... 0002 cece eee een 297
`5.4.4 Phase Compensation..............000 0.000. cee eves 301
`5.4.5 Reference-Voltage Generators ..........00...00cueee 316
`5.4.6 Burn-In Test Circuits ........0.0.0.0 0000s 323
`5.4.7 Voltage Trimming ................. 0c cee u ee eee 327
`5.4.8 Low-Power Circuits...........0 000.0 cece eee eens 329
`5.5 The HalfVpp Generator ........... 0.00 cc cece eee cece en 332
`5.6 Examples of Advanced On-Chip Voltage Generators ........ 333
`
`Low-Power Memory Circuits ...............0..000.0 ecu ees 389
`7.1
`Introduction ......... 2. ccc cee cece ence eens 389
`7.2 Sources and Reduction of Power Dissipation
`in a RAM Subsystetn ......0.. 2... ccc eee ee eee eeu cece 392
`7.2.1 Wide-Bit I/O Chip Configuration .................. 393
`7.2.2 Small Package ....... 2... ccc cece ee eee eee eens 394
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`Page 11
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` Contents
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`XI
`
`7.4 Sources of Power Dissipation in the RAM Chip..........22., 402
`7.3.1 Active Power Sources ..... 0000... 00.0 ceecceee eee. 402
`7.3.2 Data-Retention Power Sources ..................... 405
`7.1 Low-Power DRAM Circuits.......0.....0..00.00-0000-0... 406
`7.4.1 Active Power Reduction.....................--.... 406
`7.1.2 Data-Retention Power Reduction ................... 412
`7.4 Low-Power SRAM Circuits .......00000 000-0. cc cece eee. 413
`7.0.1 Active Power Reduction................,......--.. 413
`7.5.2 Data-Retention Power Reduction................... 423
`
`4. Ultra-Low-Voltage Memory Circuits...................... 425
`M1
`Introduction «2.0.0... ccc cece cece nccececes 425
`8.2 Design Issues for Ultra-Low-Voltage RAM Circuits ......... 426
`8.2.1 Reduction of the Subthreshold Current.............. 426
`8.2.2 Stable Memory-Cell Operation..................... 432
`8.2.3 Suppression of, or Compensation for,
`Design Parameter Variations....................... 433
`8.2.4 Power-Supply Standardization ..................... 435
`8.3 Ultra-Low-Voltage DRAM Circuits ....................... 437
`8.3.1 Gate Boosting Circuit.......00.0.00.0 00000000 ee 439
`8.3.2 The Multi-Vp Circuit ......0.0000 00.0000. .-000006-. 440
`8.3.3 The Gate-Source Back-Biasing Circuit .............. 442
`8.3.4 The Well Control Circuit .......................... 456
`8.3.5 The Source Control Circuit ...........,............ 461
`8.3.6 The Well and Source Control Circuit ............... 462
`8.4 Ultra-Low-Voltage SRAM Circuits........................ 463
`8.5 Ultra-Low-Voltage SOI Circuits .....................0-.., 466
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`References .. 1.1.06. ccc cece ce cence eeccceee. A73
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`Index... cece cee ccc n cence cece cence. 489
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`Page 12
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`1/O line without imposing anyrestriction on YL activation timing. Morecvet,
`the non-destructive read-out characteristics of SRAMcell allow write data (1
`be inputted to the selected data line at the earliest timing, eliminating iha
`rewrite operation that is necessary for DRAM.Evenso, the resultant high
`voltage swing on theselected data line does not destroy small read voltayes oli
`the adjacent data lines, despite capacitive coupling, since the small voltngay
`are static ones and thus are immuneto various noises, unlike the floating oii
`of the DRAM. Thus, the necessary word pulse can be shortened, enabling, fi
`row access and cycle times. If the sum of the data-replacing time involved {y
`& write operation and the equalizing time on the data lines is equal Lo thu
`sum of the column delay (Tg) and the equalizing time on the I/O lines, up
`in usual SRAM designs, the row access time is equal to the row cycle tinw
`The column speeds are faster than the row speed, as in the DRAM.If imtlt|
`stage pipelining is used, even the cycle time faster than the access time {5
`achievable[6.11].
`
`ded data lines (DLs) and multidivided word lines (WLs), shown in Fig. 6.1 |
`
`6.3 Memory-Subsystem Technologies
`It is obvious that wide-bit I/O chip configurations combined with paralle! ayy
`ration of multidivided arrays increases the throughput. Moreover, to inapreys
`the traditional DRAM performance discussed in Chap. 3 modern DRAM
`incorporate memory-subsystem technologies such as multibank interloay jag
`synchronous operation with a latch function, pipeline/prefetch Operation
`high-speed clocking schemes, and terminated interfaces combined with Irighi
`density packaging. These technologies are supported by command operation,
`on-chip moderegisters, and packet protocols.
`
`6.3.1 Wide-Bit I/O Chip Configurations
`These configurations [6.4, 6.17] offer high throughput as well as ease of ii
`which is realized by reducing the chip count needed by the system and |i
`adding flexible add-on memory capability. Despite the possibility of at lend
`256 b organization, compared to the 32 b organization for current experi
`tal 1 Gb chips(6.4, 6.17], the number of 1/O pins is eventually restricted |)
`the following drawbacks: the chip powerincreases rapidly with an increase in
`the pin count, because the number of simultaneously charged and discharyei|
`DLs{i.e. m in the logical array) increases. The chip area also increases atau
`to an increase in the I/O relevant circuits. The details are given in Chap. 7
`
`6.3.2 Parallel Operation of Multidivided Arrays
`The concept of the multidivided array [6.4, 6.17], a combination of multidiv|
`
`Page 13
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` 6.3 Memory-Subsystem Technologies
`
`355
`
`Wig. 6.11. The concept of a multidivided RAM array [6.14,6.17]: the shading
`‘lenotes the activated area. M = n'm’ = nm. (a) A non-divided array; (b) a mul-
`tidivided array; (c) a logical array
`
`internal I/O line. In an actual design, in addition to the shared Y decoders
`
`ix Lhe key to designing a high-performance RAM. The division of a DL andits
`partial activation dramatically increases the inherently small signal voltage
`and reduces the DL power dissipation that dominates the total chip power.
`lhe division of a WLis also essential to improve the ever-increasing WL delay
`with increasing memory capacity. A multidivided array realizes the high per-
`forinance of a resulting subarray,if low-resistivity multilevel metal wiring and
`high-speed subarray-selection circuits are adopted. Multilevel metal wiring
`ulso minimizes the additional increases in area at the divisions. Any com-
`bination of a number of subarrays could be simultaneously activated, since
`ench subarray could be randomly accessed. The paralle! operation capability
`of subarrays enables multibank interleaving, if each bank in a memory system
`is asserted by each subarray. However, for DRAMs the number of simulta-
`neously activated subarrays is restricted by the DL powerdissipation and the
`inaximum refresh time (the data-retention time of the cell), tgermax, which
`ik specified in the catalog for the chip. The activation for the complicated
`physical array is simplified by using the logical array comprising n virtual
`word lines shown in Fig. 6.11¢c. Here, m is the numberof refresh cycles in the
`catalog specification, which are usually distributed within tarrmax; and m
`lu the number of simultaneously activated DLs, taking m, to M/'n,, where
`Af, ns, and m, are the memory capacity of the chip, the number of sub-
`WLs, and the numberof sub-DLs in a subarray, respectively. Here, n, is less
`than 1k in the megabit era, which is determined by the minimum signal
`voltage for a successful sensing, while m, is 256 or 512 in terms of the WL
`delay. Figure 6.12a shows a more detailed multidivided array, widely used in
`tultimegabit DRAM products, featuring the DL orthogonally aligned to the
`
`Page 14
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`

`

`MainX-Dec.
`
`i/o (metal) Main WL (metal)
`Local X-Dec.
`AX (metal)
`/Suh-Array
`
`MainX-Dec.
`
`available number of data, with at least. one unit of data from each subarray.
`
`shown in the figure, a combination of a shared sense amplifier (SA) aul
`a shared I/O is used to further reduce the DL charging capacitance, as well
`as the chip area. The details are discussed in Chap.3.
`The DRAM array is a built-in structure capable of a massively paralle!
`operation at the expense of large DL power. This stems from the refresh
`operation requirement of the 1T cell, that needs simultaneous activation of
`all the cells along the selected WL. A multidivided array further increases the
`
`eReAe
`
`i
`
`S4Main Amp.
`
`o F
`
`ig. 6.12. An actual multidivided DRAM array [6.4,6.17]: the paired-line arran
`gementis actually applied for each DL andeach i/o line. (a) DL orthogonal to i/u
`line; (b) DL parallel to i/o line
`
`Page 15
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`

`
`
`357
`6.3 Memory-Subsystem Technologies
` If the 1/0 line is arranged in parallel to the corresponding DL, as shown in
`lig. 6.12b, the available number is maximized by one unit of data from each
`DL. Thus, the DRAM array inherently favors embedded DRAM designs, in
`which high throughput is the first priority, although increases in the DL
`und I/Q power become serious concerns. To achieve high throughput of
`uultidivided arrays while reducing the area, a large logic-gate block in an
`cmbedded DRAM chip will require additional layers of metal wiring.
`
`0.3.3 Multibank Interleaving
`
`Multibank interleaving has been widely used to increase the throughput with
`« substantially parallel operation of the multibank. In this scheme, a memory
`system consists of N banks, which are sequentially addressed from bank 1 to
`bank N, as shown in Fig. 6.13. Each bank is composed of a memory module
`using many DRAM chips, so that the memory bus has an Nyyp-bit data-
`lus (ie. I/O) width. When N words, each of which comprises Nup bits, are
`
`:
`CLK: MCRL
`Ai >
`Di
`
`memory
`
`bus
`
`
`
`
`
`
`
`system [width Nee
`
`
`main memory
`'~ system
`
`
`
`
`
`Vareggg$n al
`dock CLK Pe PeaY ye
`bank 4 “aeL_| {Be| =
`Ras L_ (ae | _.
`|
`rn ce
`+
`output of MUX ee pees r ya BXINEXG
`Fig. 6.13. Conventional multibank interleaving [6.8]. MUX, multiplexer; MCRL,
`inemory controller
`
`
`
`
`
`Page 16
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`

`next accessing. As a result of multiplexing of data from each bank, Nun
`bit data are available every system-clock cycle ¢,, on the system bus. Since
`it continues for the memory cycle time (tyc) of bank, the throughput ix
`increased from Nup/tme to NupN/tmc, with an N-fold increase. However,
`this approach causes an increase in the minimum add-on memory capacity,
`which is expressed as MNypN/j, where M and j are the memory capacil
`of the chip and the I/O pin count of chip, respectively. Moreover, it enables
`an increase in the number of bus lines and relevant devices with Nupi,
`preventing flexible design, miniaturization, and a low cost for the whole sys
`tem. Increasing j is beneficial to increasing the throughputfor a fixed add-on
`memory capacity, or to reducing the minimum add-on memory capacity for
`a fixed throughput. However, an excessively large j causes increased powec!
`dissipation, chip area, and package size, as discussed in Chap. 7. It wonl|
`also degrade the chip speed, with increased noise at the I/O pins.
`The multibank interleaving that. memory-system designers have taken{01
`granted can be implemented on one chip, if the multidivided array structun
`is utilized. This is because the subarray shownin Fig. 6.11 can be regarde
`as a bank, if each subarray equips its own peripheral circuit and each addre
`buffer of the bank, and thus it can latch the input address signal so tha
`different banks can be successively selected at the minimum system cloc}
`cycle. When a certain bank is selected, the corresponding address signal
`are latched at the address buffers of the bank, so that address input lim
`are ready for the next addressing for a different bank. While the mem
`operation of the succeeding circuits in the bank proceeds with the latchi|
`address signals, the different bank is selected with the different. addresse
`Thus, the MPU can successively access different banks without having to
`wait by the memory cycle of the bank. Moreover, while a bank is accessc
`other banks could perform precharge or refresh operations, enabling thes
`inherent DRAM operations to be hidden.
`
`as the page mode, nibble mode, static column mode, and extended-data-11|
`
`6.3.4 Synchronous Operation
`
`In this scheme, all of the input/output signals of chip are latched at (tv
`I/O interface circuits of the chip, synchronously with the system clock. ‘Thi
`scheme not only allows chip designers to incorporate various high-speed fun
`ctions, but it also allows system designers to improve the system speed, wit|:
`an easier timing on the board.
`asynchronous- aul
`Figures 6.14 and 6.15 show the concepts behind
`synchronous operation [6.8], assuming a non-divided data line. Synchronoi
`operation has been used for modern DRAMs, such as the synchronous DRAN|
`(SDRAM}, The double-data-rate (DDR) DRAM, and the Rambus DRAM
`while asynchronous operation has been used for traditional DRAMs, sucli
`
`Page 17
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` 6.3 Memory-Subsystem Technologies
`
`
`359
`
`
`
`
`periphery
`
`wrrelt Ol2 DL3 Dts
`rt + fo
`
`memory array
`
`
`
`
`= SASAKI~~62
`
` -(G2}—
`
`Fig. 6.14. The asynchronous operation of a DRAM chip [6.8]. AB, address buffers;
`ORB, data-output buffer; X, row; Y, column
`
`(EDO) DRAMs.In synchronous operation, a row address strobe signal RS1
`is generated from the chip-select signal CS at the rising edge of the system
`clock CLK, so that row addresses are strobed and the corresponding word
`line (for example, WL;) is activated. The resulting cell signals on m data
`lines are amplified in the usual manner. On the other hand, a column ad
`dress strobe signal CS1 is generated by the next CLK, so that the column
`addresses are strobed and the amplified signal on the corresponding data
`line (for example, DL;) is outputted on the common I/O bus line. Then, the
`data output Dois available from the chip synchronously with the succeeding
`CLK. The synchronous operation widens the timing margins between the
`internal control signals. Easier timing designs due to the use of simple latch
`circuits that work synchronously with the system clock are responsible to the
`wider margins. On the other hand, in asynchronous operation the internal
`timing designs are complicated, because they are closely related to many so-
`phisticated set-up/hold timing specifications between external input/output
`signals. Moreover, the latch function achieves high throughput with the re-
`sultant pipeline operation (discussed later) and multibank interleaving. The
`
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`

`row-address set-up time tasp, the row-address hold time tray, the column
`
`synchronous operation can eliminate the RAS and CAS functions that ar
`familiar in asynchronous operation, since the same functions are carried oul
`by the internal signals RS1 and C51. The operation also eliminates lony
`hold-signals such as CS in Fig. 6.15 if the commandinstruction schemeij
`adopted. Various operation modes are set by the combination of commani|
`signals whose pulse widths are almost equal to that of the system clock, 1
`seen in SDRAMs(see Fig.6.32).
`The synchronous operation of DRAM chips also increases the systuis
`speed. The asynchronous operation in Fig. 6.16, in which many control signal
`are generated at a timing generator (similar to control circuits in Fig. 6.13) by
`using the system clock, makes it complicated to synchronize address signal
`with the control signals and,'or the system clock. For example, althoug)
`various signal skews exist as a result of running on the memory board of tln
`bank, the minimum timing specifications of the DRAM chip regarding tlu
`
`Do
`
`Fig. 6.15. The synchronous operation of a DRAM chip [6.8]. LT, latch; Cl!
`control circuit; OB, data-output buffer
`
`Page 19
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`6.3 Memory-Subsystem Technologies
`
`bank
`
`| DRAM ooee
`
`
`
`
`chip se
`
`system access time
`
`Fig. 6.16. The asynchronous operation of the memory system [6.8]. TG, timing
`generator; X, row; Y, column
`
`address set-up time tasc, and the column-address hold time éc4py must be
`ensured. Obviously, four kinds of skews are added to the minimum cycle time
`achieved by the chipitself, degrading the memory-bank cycle time. A timing
`inismatch between the control signals and the system clock further degrades
`the cycle time. For example, even if tran exists bet