IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`
`US007256486B2
`
`(12) United States Patent
`Lee et al.
`
`(io) Patent No.:
`(45) Date of Patent:
`
`US 7,256,486 B2
`Aug. 14, 2007
`
`(54) PACKAGING DEVICE FOR
`SEMICONDUCTOR DIE, SEMICONDUCTOR
`DEVICE INCORPORATING SAME AND
`METHOD OF MAKING SAME
`
`(75)
`
`Inventors: Kong Weng Lee, Penang (MY); Kee
`Yean Ng, Penang (MY); Yew Cheong
`Kuan, Penang (MY); Gin Ghee Tan,
`Penang (MY); Cheng Why Tan,
`Penang (MY)
`
`(73) Assignee: Avago Technologies ECBU IP
`(Singapore) Pte. Ltd., Singapore (SG)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 10/608,605
`
`(22) Filed:
`
`Jun. 27, 2003
`
`(65)
`
`Prior Publication Data
`US 2004/0262738 Al
`Dec. 30, 2004
`
`6,191,477 Bl*
`6,268,654 Bl *
`6,362,525 Bl
`6,383,835 Bl
`6 , 6 2 0 , 7 2 0 B l *
`6,707,247 B2
`6,828,510 Bl
`7,098,593 B2 *
`2002/0139990 Al *
`
`2/2001 Hashemi
`7/2001 Glenn et al. .
`3/2002 Rahim
`5/2002 Hata et al.
`9/2003 Moyer et al.
`3/2004 Murano
`12/2004 Asai et al.
`8/2006 Teng
`10/2002 Suehiro et al.
`
`257/706
`257/704
`
`438/612
`
`313/581
`. 257/99
`
`(Continued)
`OTHER PUBLICATIONS
`
`Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr.,
`"Handbook of Multilevel Metallization for Integrated Circuits," N
`oyes Publ., Westwood, New Jersey (1993), pp. 868-872.*
`
`(Continued)
`Primary Examiner—Sara Crane
`
`(57)
`
`ABSTRACT
`
`The packaging device includes a substrate, a mounting pad,
`a connecting pad and an interconnecting element. The
`substrate is substantially planar and has opposed major
`surfaces. The mounting pad is conductive and is located on
`one of the major surfaces. The connecting pad is conductive
`and is located on the other of the major surfaces. The
`conductive interconnecting element extends through the
`substrate and electrically interconnects the mounting pad
`and the connecting pad. The packaging device has a volume
`that is only a few times that of the semiconductor die and can
`be fabricated from materials that can withstand high-tem­
`perature die attach processes. The packaging device can be
`configured as the only packaging device used in the semi­
`conductor device or as a submount for a semiconductor die
`that requires a high-temperature die attach process.
`
`6 Claims, 8 Drawing Sheets
`
`(51) Int. CI.
`H01L 29/22
`(2006.01)
`257/690; 257/784; 257/690
`U.S. CI
`(52)
`(58) Field of Classification Search
`257/690,
`257/784, 700, 689, 774, 783, 99, 100; 361/707,
`361/718,719, 706,717, 720
`See application file for complete search history.
`References Cited
`U.S. PATENT DOCUMENTS
`2,907,925 A
`10/1959 Parsons
`4/1991 Freyman et al.
`5,006,673 A
`1/1993 Abe
`5,177,593 A *
`3/1994 Rapoport et al.
`5,298,687 A
`8/1995 Kawakita et al.
`5,440,075 A
`6/1997 Selna
`5,640,048 A *
`9/1997 Okazaki
`5,670,797 A
`11/1999 Wyland
`5,986,885 A *
`7/2000 Horiuchi et al.
`6,084,295 A *
`
`(56)
`
`257/98
`
`257/738
`
`361/704
`257/690
`
`310
`
`y1^
`
`^30V 400
`
`340
`
`320
`
`of
`
`z •312
`
`300
`
`330
`250
`
`1J
`
`314^_
`
`340
`
`320
`
`400
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`US 7,256,486 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`2002/0179335 A1
`2003/0017645 Al
`2003/0020126 Al
`2003/0040138 Al
`2003/0168256 Al
`
`12/2002 Curcio et al.
`1/2003 Kabayashi et al.
`1/2003 Sakamoto et al.
`2/2003 Kobayashi et al.
`9/2003 Chien
`
`OTHER PUBLICATIONS
`Electronic Packaging and Production, "Innovative PCB Reinforce-
`ment," (Feb. 1997), p. 1.*
`Johannes Adam, "New Correlations Between Electrical Current and
`Temperature Rise in PCB Traces," Proc. 20th IEEE Semi-Therm
`Symp., (Mar. 2004), pp. 1-8.*
`* cited by examiner
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 1 of 8
`
`US 7,256,486 B2
`
`100
`
`132
`
`118
`
`110
`
`1 1 2
`
`130
`
`122
`
`120
`
`1 1 6
`
`250
`
`132
`
`254
`
`13Q
`
`FIG.1 A
`
`200
`
`252
`
`100
`
`FIG.2A
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 2 of 8
`
`US 7,256,486 B2
`
`112 \ ^30
`110
`
`1 1 6
`
`132
`
`V8 /100
`
`114
`
`140
`
`1 2 0
`FIG.1B
`110^112^ p
`IF
`130
`CL
`
`142
`
`122
`
`100 Z
`
`100
`112
`130
`
`120 <
`
`132
`122 (
`
`\
`
`1
`
`110
`
`114
`
`140
`
`120
`
`1 1 6
`
`FIG.1C
`
`IF
`FIG.1D
`
`110
`
`100
`112
`130
`
`122
`
`142
`
`L
`
`110
`
`114
`
`140
`
`120
`
`116
`
`100 z
`140 r
`120 <
`
`FIG.1F
`
`FIG.1E
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 3 of 8
`
`US 7,256,486 B2
`
`252
`
`250
`
`254
`
`200
`
`132
`
`130
`112—v.
`110
`
`114
`
`100
`
`J
`
`1 4 0
`
`^ ^ 1 2 2
`142
`
`120
`FIG.2B
`^11^ r
`\ ^10V
`2F 252
`
`z 112
`
`100
`
`130
`250
`
`254
`
`114
`
`140
`
`120
`
`/ 252
`200
`FIG.2C
`z 112
`100
`130
`% 250
`
`114—
`
`140
`
`254
`
`/
`
`A
`
`X.
`
`/ 252
`200
`FIG.2F
`
`110
`
`200
`
`120
`
`)
`
`—-130
`
`132
`1 2 2 (
`
`^ r \
`
`r 254
`
`--250
`
`*
`
`2F
`FIG.2D
`
`110
`
`1 2 2
`
`142
`
`L
`
`100 z
`140 r
`
`120
`
`/'"A
`
`FIG.2E
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 4 of 8
`
`US 7,256,486 B2
`
`330
`
`300
`
`320
`
`316
`
`310
`
`312
`
`250
`
`330
`
`FIG.3A
`
`FIG.4A
`
`400
`
`300
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 5 of 8
`
`US 7,256,486 B2
`
`312\ 330
`310
`
`314
`
`340
`
`310^ 312^
`
`300
`312
`330
`
`310
`
`314
`
`340
`
`320
`
`316
`
`FIG.3C
`
`310
`
`300
`312
`330
`
`310
`
`314
`
`340
`
`320
`
`316
`
`z.
`
`316
`
`300 z
`
`z
`
`300
`
`300
`
`Z
`
`320
`FIG.3B
`3F
`
`•*
`
`330 a
`
`)
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`•*
`
`3F
`FIG.3D
`
`340
`CL
`320 K
`
`\ ^
`
`FIG.3F
`
`FIG.3E
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 6 of 8
`
`US 7,256,486 B2
`
`250
`
`330
`
`400
`
`310
`
`314
`
`300
`
`7
`7^
`320
`340
`FIG.4B
`
`400
`310
`^ 312. p— 4F/300/
`
`-320
`
`1
`v ^
`
`-330
`
`250
`
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`
`4F
`
`FIG.4D
`
`310
`^ 314.
`
`yioy 400
`
`300 Z
`
`312
`330
`250
`
`314
`
`340
`
`320
`
`7
`400
`FIG.4C
`Z 312
`300
`
`314v
`
`340
`
`320
`
`330
`250
`
`340
`{2
`
`-320
`
`)
`
`7
`400
`FIG.4F
`
`FIG.4E
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 7 of 8
`
`US 7,256,486 B2
`
`512
`510
`
`514
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`512
`510
`
`514
`
`516
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`T
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`518
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`I
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`517
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`FIG.5A
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`i
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`520
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`516
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`522
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`FIG.5B
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`517
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`FIG.5C
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`523
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`7
`514' 5 4 1
`FIG.5D
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Aug. 14,2007
`
`Sheet 8 of 8
`
`US 7,256,486 B2
`
`512
`5 1 0 ( j
`
`£
`
`250
`530 ^,532
`iT
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`
`252 250
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`FIG.6D
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`US 7,256,486 B2
`
`1
`PACKAGING DEVICE FOR
`SEMICONDUCTOR DIE, SEMICONDUCTOR
`DEVICE INCORPORATING SAME AND
`METHOD OF MAKING SAME
`
`RELATED APPLICATION
`
`2
`packages. Modifying such processes to use a new semicon­
`ductor device package can be expensive and can interrupt
`production. Therefore, what is additionally needed is a way
`to mount a semiconductor die that requires a high-tempera-
`ture die attach process in a conventional packaging device.
`
`5
`
`SUMMARY OF THE INVENTION
`
`BACKGROUND OF THE INVENTION
`
`This application is related to a simultaneously-filed U.S.
`The invention provides a packaging device for a semi-
`patent application Ser. No. 10/608,606 entitled Method for
`Fabricating a Packaging Device for Semiconductor Die and 10 conductor die. The packaging device includes a substrate, a
`mounting pad, a connecting pad and an interconnecting
`Semiconductor Device Incorporating Same of inventors
`element. The substrate is substantially planar and has
`Kong Weng Lee, Kee Yean Ng, Yew Cheong Kuan, Cheng
`opposed major surfaces. The mounting pad is conductive
`Why Tan and Gin Ghee Tan.
`and is located on one of the major surfaces. The connecting
`15 pad is conductive and is located on the other of the major
`surfaces. The conductive interconnecting element extends
`Many types of conventional semiconductor device are
`through the substrate and electrically interconnects the
`composed of a semiconductor die mounted in a packaging
`mounting pad and the connecting pad.
`device. One type of packaging device widely used in the
`The packaging device has a volume that is only a few
`industry includes a metal lead frame. A metallization layer 20 times that of the semiconductor die and can be fabricated
`of aluminum located on the bottom surface of the semicon-
`from materials that can withstand a high-temperature die
`ductor die is bonded to a conductive surface that forms part
`attach process. The packaging device can be configured as
`the only packaging device of the semiconductor device. The
`of the lead frame to attach and electrically connect the die to
`packaging device can alternatively be configured as a sub-
`the lead frame. Additionally, electrical connections are made
`between bonding pads on the top surface of the die and other 25 mount for a semiconductor die that requires a high-tempera-
`ture die attach process. The submount with attached semi­
`leads of the lead frame to provide additional electrical
`conductor die can be handled as a conventional, albeit
`connections to the die. The lead frame and semiconductor
`die are then encapsulated to complete the semiconductor
`slightly larger, semiconductor die that is then mounted in a
`conventional packaging device, such as a lead frame based
`device. The packaging device protects the semiconductor
`die and provides electrical and mechanical connections to 30 packaging device, using a conventional semiconductor
`the die that are compatible with conventional printed circuit
`device assembly process, including conventional tempera­
`tures.
`board assembly processes.
`In such conventional semiconductor devices, the bottom
`The invention also provides a semiconductor device that
`surface of the die is typically bonded to the conductive
`includes a substrate, a mounting pad, a connecting pad, an
`surface of the lead frame using a silver epoxy adhesive that 35 interconnecting element and a semiconductor die. The sub-
`cures at a relatively low temperature, typically about 120° C.
`strate is substantially planar and has opposed major surfaces.
`The curing temperature of the silver epoxy adhesive is
`The mounting pad is conductive and is located on one of the
`compatible with the other materials of the packaging device.
`major surfaces. The connecting pad is conductive and is
`The volume of the packaging device used in such con­
`located on the other of the major surfaces. The conductive
`ventional semiconductor devices, i.e., the lead frame and the 40 interconnecting element extends through the substrate and
`encapsulant, is typically many times that the semiconductor
`electrically interconnects the mounting pad and the connect­
`die. This makes such conventional semiconductor devices
`ing pad. The semiconductor die is affixed to the mounting
`unsuitable for use in applications in which a high packing
`pad.
`density is required. A high packing density allows minia­
`The semiconductor device as just described can be
`turization and other benefits. Therefore, what is needed is a 45 mounted in a conventional packaging device as described
`semiconductor packaging device that is comparable in vol­
`above. Alternatively, the semiconductor device may addi­
`ume with the semiconductor die and that is compatible with
`tionally include a bonding pad, an additional connecting
`conventional printed circuit board assembly processes.
`pad, an additional interconnecting element and a bonding
`Recently, semiconductor die having a substrate surface
`wire. The bonding pad is conductive and is located on the
`metallization layer of a gold-tin alloy (80% Au:20% Sn 50 one of the major surfaces. The additional connecting pad is
`approximately) have been introduced in light-emitting
`conductive and is located on the other of the major surfaces.
`devices. Such semiconductor die typically have a substrate
`The additional interconnecting element is conductive and
`of sapphire, silicon carbide or a Group III-V semiconductor
`extends through the substrate and electrically interconnects
`material, such as gallium arsenide. Semiconductor devices
`the bonding pad and the additional connecting pad. The
`having substrates of the first two substrate materials have 55 bonding wire extends between the semiconductor die and
`layers of Group III-V semiconductor materials, such as
`the bonding pad. Such a semiconductor device constitutes a
`gallium nitride, deposited on their substrates. The die attach
`stand-alone semiconductor device that has a low profile and
`process for such semiconductor die uses a gold-tin eutectic,
`that can be used in high packing density applications. The
`which has a melting point of about 280° C. Temperatures as
`semiconductor device may additionally include an encapsu-
`high as about 350° C. can be encountered in the die attach 60 lant that encapsulates the semiconductor die and at least a
`process for such die. Such high temperatures are incompat­
`portion of the major surface of the substrate on which the
`ible with the materials of many conventional packaging
`mounting pad is located.
`devices. Thus, what is also needed is a packaging device for
`semiconductor die that use a high-temperature die attach
`process.
`Many printed circuit assembly processes and assembly
`equipment require the use of standard semiconductor device
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`65
`
`FIGS. 1A, IB, 1C, ID, IE and IF are respectively an
`isometric view, a side view, a front view, a top view, a
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`US 7,256,486 B2
`
`3
`4
`bottom view and a cross-sectional view of a first embodi-
`The material of substrate 110 is a thermally-conductive
`ment of a packaging device in accordance with the inven­
`ceramic such as alumina or beryllia. In an embodiment, the
`tion. The cross-sectional view of FIG. IF is along the section
`material of the substrate was Kyocera® Type A440 ceramic
`line IF—IF in FIG. ID.
`sold by Kyocera Corp., of Kyoto, Japan. Typical dimensions
`FIGS. 2A, 2B, 2C, 2D, 2E and IF are respectively an 5 of the substrate are in the range from about 0.5 mm square
`isometric view, a side view, a front view, a top view, a
`to about 2 mm square. Rectangular configurations are also
`possible. Alternative substrate materials include semicon­
`bottom view and a cross-sectional view of a first embodi­
`ductors, such as silicon, and epoxy laminates, such as those
`ment of a semiconductor device in accordance with the
`used in printed-circuit boards. Other materials that have a
`invention. The cross-sectional view of FIG. 2F is along the
`10 high thermal conductivity and a low electrical conductivity
`section line 2F—2F in FIG. 2D.
`can be used instead of those exemplified above. The coef­
`FIGS. 3A, 3B, 3C, 3D, 3E and 3F are respectively an
`ficient of thermal expansion of the substrate material relative
`isometric view, a side view, a front view, a top view, a
`to that of the semiconductor die to be mounted on packaging
`bottom view and a cross-sectional view of a second embodi­
`device 100 should also be considered in choosing the
`ment of a packaging device in accordance with the inven­
`tion. The cross-sectional view of FIG. 3F is along the section 15 substrate material.
`line 3F—3F in FIG. 3D.
`As will be described in more detail below, substrate 110
`FIGS. 4A, 4B, 4C, 4D, 4E and 4F are respectively an
`is part of a wafer (not shown) from which typically several
`hundred packaging devices 100 are fabricated by batch
`isometric view, a side view, a front view, a top view, a
`bottom view and a cross-sectional view of a second embodi-
`processing. After fabrication of the packaging devices, the
`ment of a semiconductor device in accordance with the 20 wafer is singulated into individual packaging devices. Alter-
`natively, the packaging devices may be left in wafer form
`invention. The cross-sectional view of FIG. 4F is along the
`after fabrication. In this case, singulation is not performed
`section line 4F—4F in FIG. 4D.
`FIGS. 5A-5C are side views illustrating a method in
`until after at least a die attach process has been performed to
`attach a semiconductor die to each mounting pad 130 on the
`accordance with the invention for fabricating a packaging
`25 wafer. In some embodiments, wafer-scale wire bonding,
`device for a semiconductor die.
`encapsulation and testing are also performed prior to singu­
`FIG. 5D is a side view illustrating an optional additional
`lation. Full electrical testing, including light output testing,
`process that may be included in the method illustrated in
`FIGS. 5A-5C.
`may be performed on the wafer.
`FIGS. 6A-6D are side views illustrating a method in
`The material of interconnecting elements 120, 122 is
`accordance with the invention for fabricating a semiconduc- 30 metal or another electrically-conductive material. In an
`tor device.
`embodiment, the material of the interconnecting elements is
`tungsten, but any electrically-conductive material capable of
`forming a low-resistance electrical connection with the pads,
`i.e., mounting pad 130, bonding pad 132 and connecting
`35 pads 140, 142, and capable of withstanding the temperature
`FIGS. 1A-1F are schematic diagrams illustrating a first
`of the die-attach process may be used. As noted above,
`exemplary embodiment 100 of a packaging device for a
`packaging device 100 may be subject to a temperature as
`semiconductor die in accordance with the invention. Pack­
`high as about 350° C. when a gold-tin eutectic is used to
`aging device 100 is composed of a substrate 110, intercon­
`attach a semiconductor die to the mounting pad 130 of the
`necting elements 120 and 122, a mounting pad 130, a 40 packaging device. Interconnecting elements 120, 122 may
`bonding pad 132 and connecting pads 140 and 142 (FIG.
`be located relative to mounting pad 130 and bonding pad
`IE).
`132, respectively, elsewhere than the centers shown. More­
`Substrate 110 is substantially planar, has opposed major
`over, more than one interconnecting element may be located
`surfaces 112 and 114 and defines through holes 116 and 118
`within either or both of the mounting pad and the bonding
`that extend through the substrate between major surfaces 45 pad.
`112 and 114. Interconnecting element 120 is electrically
`The material of pads 130, 132, 140, 142 is metal or
`conductive and is located in through hole 116. Interconnect­
`another electrically-conductive material. Important consid­
`ing element 122 is electrically conductive and is located in
`erations in selecting the material of the pads are adhesion to
`through hole 118. Mounting pad 130 and bonding pad 132
`substrate 110, an ability to form a durable, low-resistance
`are electrically conductive, are separate from one another 50 electrical connection with interconnecting elements 120 and
`and are located on the portions of the major surface 112 of
`122 and an ability to withstand the temperature of the die
`substrate 110 in which through holes 116 and 118 are
`attach process. In an embodiment, the structure of the pads
`respectively located. Connecting pads 140 and 142 are
`is a seed layer of tungsten covered with layer of nickel about
`electrically conductive, are separate from one another and
`1.2 jxm to about 8.9 jxm thick that is in turn covered with a
`are located on the portions of the major surface 114 of 55 layer of gold about 0.75 (im thick. Other metals, alloys,
`substrate 110 in which through holes 116 and 118 are
`conductive materials and multi-layer structures of such
`respectively located.
`materials can be used.
`Mounting pad 130 and connecting pad 140 are electrically
`Packaging device 100 is used to package a semiconductor
`connected to opposite ends of interconnecting element 120.
`die. A semiconductor device in which a semiconductor die
`Thus, interconnecting element 120 extending through sub- 60 is packaged using packaging device 100 described above
`strate 110 in through hole 116 electrically connects mount-
`will be described next.
`ing pad 130 to connecting pad 140. Bonding pad 132 and
`FIGS. 2A-2F are schematic diagrams illustrating an
`connecting pad 142 are electrically connected to opposite
`exemplary embodiment 200 of a semiconductor device in
`ends of interconnecting element 122. Thus, interconnecting
`accordance with the invention. Semiconductor device 200
`element 122 extending through substrate 110 in through hole 65 incorporates packaging device 100 in accordance with the
`118 electrically connects bonding pad 132 to connecting pad
`invention. Elements of semiconductor device 200 that cor­
`respond to elements of packaging device 100 described
`142.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`US 7,256,486 B2
`
`5
`6
`above with reference to FIGS. 1A-1F are indicated using the
`The material of encapsulant 252 is clear epoxy. Alterna­
`same reference numerals and will not be described again in
`tive encapsulant materials include silicone. Embodiments of
`semiconductor device 200 that neither emit nor detect light
`detail.
`can use an opaque encapsulant.
`Semiconductor device 200 is composed of packaging
`In the example of semiconductor device 200 described
`device 100 described above with reference to FIGS. 1A-1F, 5
`above, semiconductor die 250 is embodied as a light-
`a semiconductor die 250, encapsulant 252 and a bonding
`emitting diode. Semiconductor die 250 may alternatively
`wire 254. In the example shown, semiconductor die 250
`embody another type of diode without modification to
`embodies a light-emitting diode and has anode and cathode
`packaging device 100. Versions of packaging device 100
`electrodes (not shown) covering at least parts of its opposed
`major surfaces. Semiconductor die 250 is mounted on pack- 10 may be used to package semiconductor die other than those
`that embody such electrical components as diodes that have
`aging device 100 with the metallization on its bottom major
`only two electrodes. Versions of packaging device 100 may
`surface attached to mounting pad 130. Encapsulant 252
`be used to package semiconductor die that embody such
`covers the semiconductor die and the part of the major
`electronic circuit elements as transistors and integrated
`surface 112 of substrate 100 where mounting pad 130 and
`bonding pad 132 are located. Bonding wire 254 extends 15 circuits that have more than two electrodes. Such versions of
`packaging device 100 have a number of bonding pads,
`between a bonding pad located on the top major surface of
`interconnecting elements and connecting pads correspond­
`semiconductor die 250 and bonding pad 132.
`ing to the number of bonding pads located on the top major
`The bonding pad on the top major surface of semicon­
`surface of the semiconductor die. For example, a version of
`ductor die 250 is typically part of or connected to the anode
`20 packaging device 100 for packaging a semiconductor die
`electrode of the light-emitting diode. The metallization on
`that embodies a transistor having collector, base and emitter
`the bottom major surface of semiconductor die 250 typically
`electrodes, and in which the substrate metallization provides
`constitutes the cathode electrode of the light-emitting diode.
`the collector electrode, has two bonding pads, two intercon­
`Thus, the anode electrode of semiconductor die 250 is
`necting elements and two connecting pads. Wire bonds
`electrically connected to connecting pad 142 by bonding
`wire 254, bonding pad 132 and interconnecting element 122, 25 connect the emitter bonding pad on the semiconductor die to
`one of the bonding pads on the packaging device and the
`and the cathode electrode of semiconductor die 250 is
`base bonding pad on the semiconductor die to the other of
`electrically connected to connecting pad 140 by mounting
`the bonding pads on the packaging device.
`pad 130 and interconnecting element 120.
`The connecting pads, e.g., connecting pads 140 and 142,
`Encapsulant 252 has a thickness greater than the maxi­
`30 of embodiments of packaging device 100 having multiple
`mum height of bonding wire 254 above major surface 112.
`connecting pads may be arranged to conform with an
`In the example shown, the encapsulant is transparent to
`industry standard pad layout to facilitate printed circuit
`enable semiconductor device 200 to emit the light generated
`layout. In such embodiments, the interconnecting elements
`by semiconductor die 250.
`may be offset from the centers of the respective mounting
`Semiconductor die 250 is composed of one or more layers
`35 pads, bonding pads and connecting pads to allow the con­
`(not shown) of any semiconductor material composed of
`necting pad layout to conform with such a standard pad
`elements from Groups II, III, IV, V and VI of the periodic
`layout. In some embodiments, one or more of the mounting
`table in binary, ternary, quaternary or other form. Semicon­
`pad, bonding pads and connecting pads may have a shape
`ductor die 250 may additionally include a non-semiconduc­
`that differs from the regular shapes illustrated. Some irregu-
`tor substrate material, such as sapphire, metal electrode
`40 lar shapes include two main regions electrically connected
`materials and dielectric insulating materials, as is known in
`by a narrow track. For example, an irregularly-shaped
`the art.
`bonding pad includes a region to which the bonding wire is
`In an embodiment of the above-described example in
`attached, a region connected to the interconnecting element
`which semiconductor die 250 embodies a light-emitting
`and a narrow track interconnecting the two regions.
`diode, semiconductor die 250 is composed of a substrate of 45
`Some versions of packaging device may accommodate
`silicon carbide that supports one or more layers of (indium)
`two or more semiconductor die. In such versions, mounting
`gallium nitride. Such a light-emitting diode generates light
`pad 130 is sized large enough to accommodate the two or
`in a wavelength range extending from ultra-violet to green.
`more semiconductor die. Additionally, such versions include
`The bottom major surface (not shown) of the substrate
`sufficient bonding pads, interconnecting elements and con-
`remote from the layers of (indium) gallium nitride is coated 5o necting pads to make the required number of electrical
`with a metallization layer of a gold-tin alloy. A gold-tin
`connections to the semiconductor die. Alternatively, the
`eutectic attaches the semiconductor die to mounting pad
`packaging device may include two or more mounting pads.
`130, as described above, to provide a mechanical and
`The mounting pads may be electrically connected to one
`electrical connection between the semiconductor die and the
`another and thence to a common interconnecting element
`mounting pad.
`55 and connecting pad. Alternatively, each mounting pad may
`The material of bonding wire 254 is gold. A process
`be electrically connected to a corresponding connecting pad
`by a respective interconnecting element.
`known in the art as low-loop wire bonding is used to connect
`the bonding wire between the anode electrode of semicon­
`Semiconductor device 200 is used by mounting it on a
`printed circuit board or other substrate using conventional
`ductor die 250 and bonding pad 132. Using low-loop wire
`bonding minimizes the maximum height of the bonding wire 60 surface-mount techniques or other techniques known in the
`above substrate 110, and, therefore, reduces the overall
`art. Semiconductor device 200 is placed on a surface of the
`height of semiconductor device 200. Other processes for
`printed circuit board with connecting pads 140 and 142
`providing an electrical connection between a bonding pad on
`aligned with respective pads on the printed circuit board.
`a semiconductor die and a bonding pad on a packaging
`The printed circuit board is then passed across a solder wave
`device are known in the art and may be used instead, 65 to form a solder joint between connecting pads 140 and 142
`especially in applications in which device height is a less
`and the respective pads on the printed circuit board. Alter­
`important consideration.
`natively, semiconductor device 200 may be aflBxed to a
`
`EVERLIGHT ELECTRONICS CO., LTD. ET AL.
`Exhibit 1001
`
`

`

`US 7,256,486 B2
`
`7
`8
`Materials and other details of substrate 310, interconnect­
`printed circuit board by a process known as infra-red reflow
`ing element 320, mounting pad 330 and connecting pad 340
`soldering in which a pattern of solder is applied to the
`are the same as those of substrate 110, interconnecting
`printed circuit board using a stencil, semiconductor device
`element 120, mounting pad 130 and connecting pad 140,
`200 and, optionally, other components are loaded onto the
`printed circuit board and the printed circuit board assembly 5 respectively, of packaging device 100 described above with
`is irradiated with infra-red light to heat and reflow the solder.
`reference to FIGS. 1A-1F and will therefore not be
`Other processes for attaching electronic components to
`described again here.
`A semiconductor device in which a semiconductor die is
`printed circuit boards are known in the art and may alter­
`natively be used. Packaging device 100 and semiconductor
`packaged using packaging device 300 described above will
`device 200 may additionally include adhesive regions on the 10 be described next,
`FIGS. 4A-4F are schematic diagrams illustrating an
`major surface 114 of substrate 110 external to connecting
`exemplary embodiment 400 of a semiconductor device in
`pads 140 and 142 to hold the semiconductor device in place
`accordance with the invention. Semiconductor device 400
`on the printed circuit board during soldering.
`In semiconductor device 200, packaging device 100 and
`incorporates packaging device 300 in accordance with the
`encapsulant 252 collectively have a volume that is only 15 invention. Elements of semiconductor device 400 that cor-
`about 15 times the volume of semiconductor die 250. Thus,
`respond to elements of semiconductor device 200 described
`packaging device 100 is well suited for use in high packing
`above with reference to FIGS. 2A-2F and of packaging
`density applications. Moreover, packaging device 100 is
`device 300 described above with reference to FIGS. 3A-3F
`fabricated from materials capable of withstanding the high
`are indicated using the same reference numerals and will not
`temperatures involved in a die attach process that uses a 20 be described again in detail,
`Semiconductor device 400 is composed of a semiconduc­
`gold-tin eutectic. Accordingly, packaging device 100 is well
`tor die 250 mounted on packaging device 300 described
`suited for packaging semiconductor die, such as the die of
`certain light-emitting devices, that require a die attach
`above with reference to FIGS. 3A-3F. In the example
`shown, semiconductor die 250 embodies a light-emitting
`process that uses a gold-tin eutectic.
`As noted above, many printed circuit board assembly 25 diode and has anode and cathode electrodes (not shown)
`processes are designed to use standard device packages, but
`covering at least parts of its opposed major surfaces. Spe­
`cifically, semiconductor die 250 is mounted on packaging
`many standard device packages are incapable of withstand­
`device 300 with the metallization on its bottom major
`ing the high temperatures involved in a die attach process
`surface attached to mounting pad 330. The metallization on
`that uses a gold-tin eutectic. FIGS. 3A-3F are schematic
`drawings showing a second embodiment 300 of a packaging 30 the bottom major surface of semiconductor die 250 typically
`device in accordance with the invention. Packaging device
`constitutes the cathode electrode of the light-emitting diode.
`300 takes the form of a submount that enables semiconduc-
`Thus, the cathode electrode of semiconductor die 250 is
`tor die that are mounted using a gold-tin eutectic or other
`electrically connected to connecting pad 340 by mountin